在SCH与PCB比较中出现如下信息:PCB Net List Errors Report - led-2.sch - Wed Dec 07 14:41:54 2011" j5 g' _! a% e& u2 l
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Design to Library Part Consistency Check1 @6 ?2 b( A' q
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No Library consistency checking errors.6 c$ i' P& e0 h6 m8 T! e3 E
$ X& P( ]) [7 `6 D3 WSingle/Zero Pin Net Warnings
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: q$ Z, b9 P! w5 o7 j, u. bNet $$$2 has less than two pins in PCB net list file.1 g; m. ?2 u# H
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Schematic Connectivity Errors: Y8 ?! S4 C' m; W" y
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0 V' [1 n U9 K% t! ?No connectivity errors or warnings.
/ E5 z9 r/ \. a****************************************, ^7 m$ D- _" G; z/ H {$ }. b. x
UNMATCHED NET PINS IN Schematic
0 ?$ b; n0 d7 u) ?2 V- c/ Z$ \-------------------------------
8 Z8 }2 G: T; z9 K8 Z$$$10827 C11.1
; d1 A! V/ \( A. R$ e* j' e) M: |$$$2 R37.1
: N5 ~$ E& e7 R( E3 L, z: m0 VGND-2 C11.2 * q) H7 ?, @# [, P8 f
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UNMATCHED NET PINS IN PCB
6 \% ]5 z1 w: c* b* [8 T7 c-------------------------1 h& Y2 _; O. `6 {6 \2 e( z
$$$10827 C11.2
# z# x# K( d3 Y( Z% \* I( J, E$$$2 R37.1 R7.3 ) v6 [: `# D) q" Q
GND-2 C11.1 R7.2 " ]+ |' W' x1 j& L1 Q9 z7 g
检查PCB与原理图中连接相同,但为何会这样报错?
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