Hotfix SPB16.60.008已经发布，附bt种子，求网盘连接

Jason022

% M+ m* K( _* R% b% Y" n6 m% \- iDATE: 04-26-2013 HOTFIX VERSION: 008
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9 u0 O! w$ R+ }/ F6 bCCRID PRODUCT PRODUCTLEVEL2 TITLE
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876711 allegro_EDITOR GRAPHICS Mouse wheel will only zoom out using Win7 64 bit
1080386 concept_HDL CORE Unable to highlight netclass on every schematic page using Global Navigation
1082587 FSP FPGA_SUPPORT Support of Xilinx's Zync device
4 R& J$ r* z0 N! v, p. E) O1105286 FSP DE-HDL_SCHEMATIC FSP crashes while creating board in Schgen if it does not find any available license.
1105461 ALLEGRO_EDITOR DRAFTING Dimension Enviroment deletes Diameter symbol whenever we add anything to Text section
/ h2 z( {3 Y/ c! w5 s6 Z1105504 PCB_LIBRARIAN CORE PDV on Linux Move pins by arrows does not stop when release arrow key but keeps on running
2 t3 A1 a& I1 M0 N1110126 ALLEGRO_EDITOR GRAPHICS Display Hole displays strange color.
+ k) t' ]; j* G: W  {! O1113518 CIS DESIGN_VARIANT Incorrect Variant information in Variant View Mode for multi-section parts with occurrence
1117580 SCM OTHER DSMAIN-335: Dia file(s) error has occurred.
1117845 FSP DE-HDL_SCHEMATIC Schematic Generation fails without a reason
1119864 FSP TERMINATIONS Auto-increment the pin number while mapping terminations.
* [' @7 _8 E8 s8 _. ~1120250 ALLEGRO_EDITOR MANUFACT Why is the parameter File altered?
7 Z5 s& R) c. M& I8 w$ O: h1120414 ADW LRM TDO Cache design issue
1121044 SIP_LAYOUT skill axlDBAssignNet returns t even when no net name is assigned to via
) @8 J- j: x+ J+ Y2 V: a3 n1121148 ALLEGRO_EDITOR PLACEMENT Ratsnests turns off when moving symbols with Net Groups
1122440 ALLEGRO_EDITOR DATABASE Cannot unlock database using the password used to lock it
1122449 ALLEGRO_EDITOR DRC_CONSTR Uncoupled length DRC for diff pair shows different actual length value between show element and CM.
2 R3 B& e) m0 N+ V. Y0 c5 d; A7 B1122990 ALLEGRO_EDITOR INTERACTIV RF PCB Symbol which is part of Reuse Module cannot be replaced
- ]4 ~% v  r/ I( T% ~7 ]7 [+ B1123083 ALLEGRO_EDITOR PLACEMENT Saving after mirroring a Place replicate mdd create a .SAV board file.
/ ]4 F1 e$ x7 S/ l( T+ f1123257 SIG_INTEGRITY SIMULATION some of the data signals at the receiver are not simulatable
; n  M7 c/ q6 k3 p6 {! d. i1123764 CONSTRAINT_MGR OTHER Allegro crash while importing DCF file
' |  N1 {+ @& U+ j& k6 T( q# A1123816 CAPTURE PART_EDITOR Movement of pin in part editor
  ^, _6 o5 A/ {6 k1124183 ALLEGRO_EDITOR EXTRACT Output from EXTRACTA gets corrupted with refdes 50
, K- C, a. W* k5 \DATE: 04-13-2013 HOTFIX VERSION: 007
# z5 m* @- i/ d- g% |) G===================================================================================================================================
CCRID PRODUCT PRODUCTLEVEL2 TITLE
1 c9 W, b. K& u& N2 @6 {===================================================================================================================================
4 y8 b- k1 s( {1107397 SIP_LAYOUT PLACEMENT Place Manual-H rotates die
1111184 ALLEGRO_EDITOR PLACEMENT NO_SWAP_PIN property does not work in 16.6
1112295 APD DXF_IF padstacksї offset Y cannot be caught by DXF.
. |0 N9 Z  R. j; r+ a1113284 ALLEGRO_EDITOR INTERFACE_DESIGN Rats disappear after moving components
1113317 CONCEPT_HDL SKILL skill code to traverse design not working properly
7 Z* ]* Y8 j0 k! Z$ l1115491 ALLEGRO_EDITOR SKILL telskill freezes command window
1115625 ALLEGRO_EDITOR SKILL Design extents corrupted when axlTrigger is used.
1115708 ALLEGRO_EDITOR INTERFACES Export DXF is outputting corrupt data on one layer.
1115850 ALLEGRO_EDITOR GRAPHICS Text edit makes infinite cursor disappear
1116530 ALLEGRO_EDITOR MANUFACT Import artwork show missing padstacks
( d, H0 {% ^7 L, K$ L1117498 ALLEGRO_EDITOR DATABASE Why does dbstat flag LOCKED?
6 k. ~/ X& ?! D( q% M1118407 SIP_LAYOUT DIE_EDITOR net connectivity is getting lost when running die abstract refresh
1118413 SIP_LAYOUT DIE_EDITOR pin number is getting changed when running die abstract refresh
1118526 CONCEPT_HDL CONSTRAINT_MGR Upreved design now has Constraint packaging errors
1118830 ALLEGRO_EDITOR SHAPE Performance issue when moving/refreshing shapes in 16.6
. I) l$ z( p# ~! X4 W1119784 ALLEGRO_EDITOR INTERACTIV ipickx command gives drawing extent error inconsistently
7 E* d. ^) o% {) q1120469 SIP_LAYOUT DIE_ABSTRACT_IF use different padstack for different, but look-alike bumps
4 I7 \9 e  o2 @: l0 i1120669 CONCEPT_HDL CORE DEHDL crash on multiple replace of hier blocks
0 c; E9 i4 p8 R  [+ g; h1120810 ALLEGRO_EDITOR EDIT_ETCH Cannot slide cline segment.
7 T. H# Z* h. `6 dDATE: 03-29-2013 HOTFIX VERSION: 006
===================================================================================================================================
  E, u- |1 E5 R9 `CCRID PRODUCT PRODUCTLEVEL2 TITLE
* \& T: _/ |5 V- k# l  W9 y===================================================================================================================================
4 E! O7 S) {8 F. D' O  W2 g! s! `  d" c" B& w110139 FIRST_ENCOUNTE GUI Error in Save OA Design form
625821 CONCEPT_HDL CORE publishpdf from command line doen not work if temp directory does not exist.
642837 Pspice SIMULATOR Option to disable Bias Points when Primary Analysis in Active Simulation Profile is DC Sweep
  o8 i! L4 x1 A6 B* H650578 ALLEGRO_EDITOR SHAPE Allegro should do void only selected Shape without "Update Shape".
. a9 x. W& M* ~0 |! y" o! N  S653835 ALLEGRO_EDITOR MANUFACT Double character drill code overlaps with "cross" in NC drill legend
1 U' g( y: V6 o( d2 X687170 SIP_LAYOUT DRC_CONSTRAINTS Shape to Route Keepout spacing DRC display incorrect
787041 FSP DE-HDL_SCHEMATIC FSP Refdes inconsistency when gen schematics
. I7 h- e% o* \825813 CONCEPT_HDL CORE HDL crashes when copying a property from one H block to other
834211 ALLEGRO_EDITOR SHAPE Constant tweaking of shape oversize values is time consuming
835944 ALLEGRO_EDITOR OTHER Customer want to change for Jumper symbol by other Alt symbol.
/ f2 o* q- u. V- ]+ q868981 SCM SETUP SCM responds slow when trying to browse signal integrity
871899 CONCEPT_HDL CORE 'Multiple:' column of Grid window in DE-HDL option is too wide
" I( G: D, @/ s9 X873917 CONCEPT_HDL CORE Markers dialog is not refreshed
887887 CONCEPT_HDL CORE Option to find unconnected Pins/Nets with DEHDL L License
888290 APD DIE_GENERATOR Die Generation Improvement
892857 CONCEPT_HDL CORE packager treats R? as a unique reference designator
902908 PSPICE SIMULATOR Support of CSHUNT Option in Pspice
908254 ALLEGRO_EDITOR INTERACTIV Enhancement request for DRC marker to have a link to CM
922422 CAPTURE NETLIST_ALLEGRO Netlist errors when using mix of convert and normal symbols
6 Z9 ?, {5 ~! R' p, h1 R923361 ALLEGRO_EDITOR INTERACTIV Stop writting PATH variables in env file if no modifications are done using User Preferences
935155 CAPTURE DRC No any warning messages listed in the On line DRC window even executed "Check & Save" to on line DRC
- T. G5 C. R' |, [: H4 f6 z945393 FSP OTHER group contigous pin support enhancement
$ U2 i1 k$ j3 |( i( I& x2 h969342 ALLEGRO_EDITOR DATABASE Enhanced password security for Allegro database
$ {4 B( a( _/ f) v+ z5 i/ e1005078 CAPTURE ANNOTATE Copy paste operation does not fill the missing refdes
1005812 F2B BOM bomhdl fails on bigger SCM Projects
' h& K- P& i! k- c3 e! T0 S1010988 CAPTURE OPTIONS ENH: ADD ISO 8601 Date Time format to Capture
. q' B8 \2 S0 |' n, r1011325 ALLEGRO_EDITOR PLACEMENT Placement replication creates modules with duplicate names
3 ?+ C/ o3 T2 O& d. B1016640 ALLEGRO_EDITOR PLACEMENT Error/Warning Message for not finding or unmatched mechanical symbol or fiducials or which are not on a net
8 c# U, e; C+ S' C+ ?% O5 T$ F1018756 CONCEPT_HDL CONSTRAINT_MGR Match Groups with Pin Pairs are not getting imported into the schematic CM during Import Physical
( M. A" t% [! Y" [6 e8 y1032387 FSP OTHER Pointer to set Mapping file for project based library.
1032609 FSP IMPORT_CONSTRAIN Import qsf into FSP fails with їLL PLL_3 does not exist in device instanceї
; p5 \$ G' z7 d2 E- w! ]4 V7 v& m4 D1040678 ALLEGRO_EDITOR MANUFACT Text spacing is inconsistant for top and bottom SM layer in xsection chart
1042025 APD WIREBOND Order placement of power rings for power/ground rings generation with using Perform Auto Bonding
8 R" q: Y) R6 o, I% g# x1045500 CONCEPT_HDL CORE Why Search results does not display the correct Physical Pages.
: e: ?  A% @0 G# j3 |1047259 CIS EXPLORER Sorting in CIS Explorer is not Numeric even for columns which are of Numeric data type
1047756 CAPTURE NETLISTS Not adding user defined properties in netlist generated by orDump.dll
4 K: D* _' b( x1052455 RF_PCB DISCRETE_LIBX_2A RFPCB IFF Export to fix port direction for ADS for footprint having the same pin rotation
5 ^' J  J" h( P1054314 CONCEPT_HDL CORE Zoom of custom text is different from other schematic objects
1061529 CONCEPT_HDL CORE Space can be included in LOCATION value and cannot be checked by checkplus
) G. s1 k2 @" ?$ W5 P+ v5 D1064035 CONCEPT_HDL COMP_BROWSER Component Browser crashes on part number search using a library containing >23K parts
1064604 ALLEGRO_EDITOR MANUFACT Enh - Include ability to add slot notes to designs
1065636 CONCEPT_HDL OTHER Text not visible in published pdf
1065843 CIS PART_MANAGER time stamp on library from different time zones triggers part manager lib out of date warnings
1066701 ALLEGRO_EDITOR OTHER Missing padstack warnings not in Symbol refresh log summary
1067283 SCM PACKAGER ALLOW_CONN_SWAP does not work for lower level schematic parts
/ Q: j6 i) d$ T% d' q; z- ]1067400 CONCEPT_HDL CORE ERROR(SPCOCD-171): Port exists in symbol but not in the schematic
1068878 CONCEPT_HDL CORE Rotating symbol causes the pin name to be upside down
3 d' r0 W. p8 J! ]& M- O1069896 ALLEGRO_EDITOR EDIT_ETCH Cline changes to arc when routing even when Line lock is set to Line 45
1070465 CONCEPT_HDL CORE Why does ConceptHDL crash on renaming a Port Signal
1071037 PSPICE SIMULATOR Provide option to disable Index Files Time Stamp Check
+ [( G# }9 M+ i4 I. S3 p1072311 CONCEPT_HDL OTHER Schematics are incorrect after importing design.
: F5 i& }. u9 i' ~" ]# H) a1072691 CONCEPT_HDL CORE Customer has the crash from Run Script of DE-HDL 16.51 again(#3)
1072859 SIP_LAYOUT DIE_EDITOR padstack selection window crash from Die Editing: Component editing of Co-Design Die
9 p! K# f: _" V/ x+ T3 }1073354 CONCEPT_HDL CORE Bubble defined on symbol pin is not visible on the schematic
1073837 ALLEGRO_EDITOR GRAPHICS Some objects disappear on ZoomIn ZoomOut
3 i& j9 q6 X0 O0 ]4 K1074243 ALLEGRO_EDITOR GRAPHICS Allegro WorldView window does not always refresh after dehighlight of objects
- Q+ A  m$ P* R# m) Y1 {1074606 ALLEGRO_EDITOR INTERACTIV Enh - Cosmetic change in Filter Option UI of Replace padstack to indicate multiple pin entry format
; `* {6 s1 A% z1074794 ALLEGRO_EDITOR REPORTS add commonly reguested via reports to Allegro and ICP reports. Via per net, via per layer per net
- n; L% f$ q4 s4 a1075587 CONCEPT_HDL PAGE_MGMT Unable to insert page in schematic
1076117 PSPICE PROBE Copy & Paste text/label in probe window changes font size and later gets invisible
1076145 SIP_LAYOUT DIE_ABSTRACT_IF Issue message in Add Codesign and Refresh Die Abstract if Pin Numbers from Die Abstract exceed 31 chars.
1076566 ALLEGRO_EDITOR EDIT_ETCH Sliding diff pair cline that has a min/max prop rule displays the HUD meter inconsistently.
1076604 ALLEGRO_EDITOR SHAPE Sliding via in pad corrupts surrounding shape and generates false DRC Errors
% q6 f. u5 G* [! k1076820 SPECCTRA FANOUT Fanout fails to stack vias in bga pads.
1076868 ALLEGRO_EDITOR PARTITION Symbols become 'read only' inside a design partition
" t$ V5 P1 ~' @- S  w1 W; G% M, Y1076879 GRE IFP_INTERACTIVE Plan Column should not be present in Visibility tab for Symbol Editor
- F$ F& |! }" ]3 K) O# B- Y1076898 CONCEPT_HDL CORE User can not increase logic grid size value continuously using Up button on Design Entry HDL Options
1077026 CIS LINK_DATABASE_PA fonts changes while linking db part in 16.5
) L0 O$ l+ T7 _' o, z1077187 ALLEGRO_EDITOR DATABASE DBDoctor appears to fix database but nothing is listed in the log file.
; k1 V. F% b' a" w. K, I4 N' {1077527 CONCEPT_HDL CORE ConceptHDL net with name U cannot be found using Global navigate
) M* d2 P, I, e1077621 CONCEPT_HDL CORE DEHDL crashes when saving page 3
1078270 SCM UI Physical net is not unique or not valid
$ [9 l6 Y/ d9 G+ B  h- `9 V; l1079616 CONSTRAINT_MGR CONCEPT_HDL Packager error in 16.5 which is resolved when system is re-booted
; c. E$ U, e0 V4 u+ ]- g5 O5 s3 H1079821 CONCEPT_HDL CORE Project Setup does not respect $TEMP variable for temp_dir and creates a directory in project calle
1080142 CIS CONFIGURATION peated entries in Allowed Part Ref Prefs
1080207 ALLEGRO_EDITOR INTERACTIV Separate the 2 types of SOV violations."Segments over voids & Segments with missing plane coverage"
: T. n! s* `3 |0 f8 n* L( A1080261 PSPICE SIMULATOR Encryption support for lines longer than 125 characters
! o* B1 }/ {/ P! N9 ~1080336 CONCEPT_HDL CORE Backannotation error message ehnancement
# m, I3 m* _$ o; P3 ]% W* N1081001 ALLEGRO_EDITOR PLACEMENT Package boundary is not visible while manually placing a component when using orcad license
1081237 ALLEGRO_EDITOR PLACEMENT Place replicate > apply does not apply component pin properties stored in .mdd
1081284 MODEL_INTEGRIT TRANSLATION Space in the file path will create a bogus error
2 g3 o6 K4 y- h  _* y# a1081346 ALLEGRO_EDITOR INTERACTIV With Place manual, rotation of the symbol is not updated.
5 H3 ?# W0 A8 G& R) J1081760 FSP CONFIG_SETTINGS Content of їFPGA Input/Output Onchip terminationї columns resets after update csv command
+ T- K) `$ _/ S. I" `1082220 FLOWS OTHER Error SPCOCV-353
9 Z$ P! Z6 y. W! f: ?1082492 ALLEGRO_EDITOR PLACEMENT Place replicate create does not highlight symbols.
* \: f0 @0 j$ e* q2 I. f# A$ B, E1082676 ALLEGRO_EDITOR EDIT_ETCH HUD meter doesnot display while sliding / add command
$ B. s: e) R  m2 s% i. }8 M1082737 CAPTURE GENERAL The їArea selectї icon shows wrong icon in Capture canvas.
1082739 CAPTURE OTHER The product choices dialogue box shows incorrect name
1082785 CONCEPT_HDL CORE DE HDL should clean the design with non sync properties in some automated way
5 Z& J, i% d: b" t+ B; E' H! b1083761 CONCEPT_HDL OTHER AGND text missing from PDF Publisher
/ H5 r# Z/ `( R' u$ d& T1 Q1 b8 {1083964 CONCEPT_HDL OTHER Do not display Value and other attributes on variant parts which are DNI
/ b+ |9 N1 b! W6 i1084023 PSPICE MODELEDITOR Model Editor is slow/unresponsive while opening a Model by double-clicking on .lib file
1084178 ALLEGRO_EDITOR SHAPE Spike create on dynamic void.
0 j/ F. y# s4 i3 m9 W) K1084637 ALLEGRO_EDITOR INTERACTIV Enhancement: Pick dialog should automatically be set to enter coordinates
1085010 CONCEPT_HDL CREFER Crefer crashes if the property value in the dcf file has more than 255 characters
1085347 CAPTURE SCHEMATIC_EDITOR Replace cache results is loss of net graphic changes.
7 L2 u) T1 Z$ E5 K- _# }9 j1085522 ALLEGRO_EDITOR INTERACTIV Allegro add angle to Display->Measure results
2 D+ g: L7 v. N. ^% k1085791 CONCEPT_HDL CORE Publish PDF can not output Constraint Manager properties into PDF file.
1085891 ALLEGRO_EDITOR INTERACTIV about DRC update
7 A5 a1 g" J! {- q1 j9 Q7 |2 c1085990 CAPTURE DRC B1: "ERROR(ORCAP-2207) Check Bus Width Mismatch" should be INFO
+ U; y; I, y* j; u. U1086514 CONCEPT_HDL COMP_BROWSER Component Browser placement restrictions not working
1086576 CONCEPT_HDL CHECKPLUS CheckPlus hangs when running Graphic rules.
" E' Z1 [$ C3 x- Z1086671 PSPICE SIMULATOR SPB16.6 pspice crashes with attached design
9 |2 l' b! r- _1 _3 c1086749 ALLEGRO_EDITOR mentor mbs2brd: DEFAULT_NET_TYPE rule is not translated
1086886 CAPTURE PROPERTY_EDITOR "Is No Connect" check box in property editor doesn't work for power pins
' L) \* _, N$ |$ }1 `1086902 CONCEPT_HDL INFRA Problems occurred while loading design connectivity
1 r% h6 h: a2 h% b# D# X0 V1086937 PSPICE ENVIRONMENT PSpice Color map getting doubled leading to crash after colors are modified number of times.
$ Z. i6 I: x) A8 a7 M9 N3 x& w+ }0 }1087221 CONCEPT_HDL OTHER Part manager could not update any parts.
& g& Z) e0 b2 E9 S' s3 H1087223 CAPTURE CROSSREF Cross Probing issue when login into system with user name containing white space
1087295 SIP_LAYOUT EXPORT_DATA Enable "ackage Overlay File for IC" for concurrent co-design dies too
' x4 F1 R6 X- T8 o! i1087658 CAPTURE PRINT/PLOT/OUTPU Lower level design pages are getting print twice
7 f, X, J) q6 Q+ P2 V: a1088231 F2B PACKAGERXL Design fails to package in 16.5
+ c( p, J; c; k: A1088252 CONCEPT_HDL CORE Menu commands grayed out after Save (with 16.5-s035) when launched from ASA.
1088606 ALLEGRO_EDITOR INTERACTIV Pin Number field do not support Pin Range for Symbol Editor
1088983 CONSTRAINT_MGR CONCEPT_HDL Units resolution changed in 16.6 Constraint Manager
4 X  E8 J9 D! A$ e* i' @. R1089017 ALLEGRO_EDITOR SHAPE What is the cause of the shape not filling?
1089259 SCM IMPORTS Cannot import block into ASA design
! P; d8 k, H/ w1089356 SIP_LAYOUT DIE_EDITOR Distributed co-design : launching die editor taking more than an hour to bring up edit form
/ u0 a) W" I4 c( o+ @0 J2 A1089362 PSPICE STABILITY Pspice crash on pspice > view simulation result on attached project
1089368 SCM OTHER Can't do Save - cp: cannot stat ... No such file or directory
1089605 CONCEPT_HDL CONSTRAINT_MGR Power net missing from the CM opened from DEHDL Schematic editor.
1090068 ALLEGRO_EDITOR SHAPE shape priority issue in SPB165
8 g  p& B  a+ i5 ?1090125 ALLEGRO_EDITOR DATABASE Q- The rename resequence log file is not giving correct message.
1090181 GRE CORE AiDT fails for the nets with errors SPGRE-21 & SPGRE-22
1090930 CONSTRAINT_MGR CONCEPT_HDL DEHDL-CM does not retain customized worksheet.
" ~" I! L( W( E1091335 CONCEPT_HDL OTHER Color change cannot remain in some situation.
1091347 CAPTURE TCL_INTERFACE The Project New link on Start Page doesn't work when Journaling is enabled
1091359 CAPTURE GENERAL Toolbar Customization missing description
1091662 CONCEPT_HDL CORE Incorrect behavior with the SHOW_PNN_SIGNAME directive
1091714 CAPTURE PART_EDITOR More than one icons gets selected in part editor at the same time
1092411 CONSTRAINT_MGR INTERACTIV In v16.6 CM multiple net name selection under net column is not working as in v16.5
1092426 CONCEPT_HDL CORE Getting ERROR(SPCOCN-1993) while saving a Hierarchical Design
1092874 CONCEPT_HDL CORE DEHDL wire short during move not detected with check enabled
1092882 ALLEGRO_EDITOR EDIT_ETCH AICC should be removed from orcad PCB Designers design parameters
1092918 CAPTURE GENERATE_PART Generate part functionality gives no/misleading information in sesison log in case of error
9 E' i* b& b$ a: ~; C/ u1 p1092933 CONCEPT_HDL OTHER PDF Publisher saves the pdf generated in the previous project folder
$ t( P# A' Z' n' z2 J1093327 CONCEPT_HDL OTHER Getting error SPCODD ї 369 Unable to load physical part in variant editor
, n' t( i. N0 Q' d) o" \( V1093391 CONSTRAINT_MGR OTHER Setup > Constraints > (domain), doesn't open correct worksheet with OrCAD PCB Editor Professional license.
: ^6 r' G1 T0 G! ^! u7 z, V1093886 SPECCTRA HIGHSPEED Pin delay does not work in PCB Router when specified in time
  I# Q; h) s2 A* S" j1094223 CAPTURE PROPERTY_EDITOR CTRL+S does not work in Property Editor but RMB > Save.
  U) `9 m; t( [6 j& f1094513 CONCEPT_HDL CORE How to display $PNN for which SIG_NAME is not visible?
2 B# Q  U( v$ ?' g( R1094611 CAPTURE PROPERTY_EDITOR E1: 'Tools->Update Properties' should list parts which are present in .UPD, but not schematic
3 G& C1 d$ @7 Z. b  Y* \1094618 CONCEPT_HDL INFRA Unable to uprev the design in 16.5
. X% t. @6 I$ K; w; g* E. Z- d0 |1094867 CONCEPT_HDL CORE Page Up / Down Keys are hard-coded assigned to Next /Previous Sheet
1095449 SIP_LAYOUT LOGIC Allow netlist-in wizard to work on a co-design die
1095701 CONCEPT_HDL CORE Replace part in replicated block only preserves the Refdes in 1st instance of the replicated block
1095705 CONCEPT_HDL CREFER Cref_to_list not updated on repl icated blocks in 16.5 release worked fine in 16.3
1095861 F2B BOM Using Upper-case Input produces incorrect BOM results
- n! a7 C2 h! O  O1096318 ALLEGRO_EDITOR INTERFACES IDF import not removing MCAD tagged objects during import
  ]& E2 |) P5 K  r9 }( M1097241 CONCEPT_HDL CORE Concepthdl - zoom in to first object in Find result automatically
& j+ P7 ?6 b; ?) U1097468 ALLEGRO_EDITOR INTERACTIV Need ability to hilight and assign color to vias
: y! V- `; G! w1 q1097675 CAPTURE ANNOTATE Enhancement:Option to have Incremental reference Update to be checked at all times when we click on Tool>Annotate
1099151 SIG_INTEGRITY SIMULATION All Neighbor crosstalk numbers reported when there are no aggressors
$ j' k- V, |; V) |1099175 CONCEPT_HDL CORE CPM directive that enables the Command Console Window in DE-HDL
/ s1 S1 J) T) G4 f* P1099838 CAPTURE TCL_INTERFACE TCL library correction utility is not working correctly.
. b! |$ V! Q+ A! Z1099903 ALLEGRO_EDITOR PLACEMENT Mirror and rotating component places component mirror side
, c- k$ M; N! |1099941 ALLEGRO_EDITOR PLACEMENT Problem in rotating bottom components when using Place Manual or place manual -h command
1099998 CONCEPT_HDL CHECKPLUS CheckPlus marker file not locating signal when signal name includes the # character.
1100018 CONCEPT_HDL COPY_PROJECT CopyProject gives errors about locked directives
1100449 ALLEGRO_EDITOR ARTWORK Pad with Net_short property and shorted to shape supressed wrongly with Pad Supression in Artwork
1100758 CAPTURE LIBRARY Import properties does not update pin numbers of multi section parts
1101009 CONCEPT_HDL CORE Cursor stays as arrow after performing File > Save Hierarchy
8 b( N- A1 A# e, }8 g7 _1101497 ALLEGRO_EDITOR UI_FORMS Allegro PCB Editor crashes using attached script when working with RF PCB Clearances.
1101813 SIP_LAYOUT DIE_ABSTRACT_IF Support die abstract properties
1102531 ALLEGRO_EDITOR GRAPHICS Allegro graphics distortion infinite cursor 16.6
1102623 ALLEGRO_EDITOR SHAPE Strange void around the pad
1103246 FSP FPGA_SUPPORT New FPGA request - Arria V - 5AGXMA1D6F31 - IN2P3
1103631 MODEL_INTEGRIT OTHER Model Integrity license when using orcad
1103703 F2B DESIGNSYNC Toolcrash with Design Differences
1103712 CONCEPT_HDL COPY_PROJECT Copy Project crashes on customer design attempting to update symbol view
! B7 Q( X* H. S, K; v1104068 CAPTURE DRC "Check single node connection" DRC gets reset in 16.6
1104121 PSPICE AA_OPT їarameter Selectionї window not showing all the components : on WinXP
1104575 CONCEPT_HDL CORE Allign does not allign offgrid symbols correctly
1 N9 l/ L+ K5 ]! a: w: n4 O1104727 CONSTRAINT_MGR SCM Net Group created in sip does not transfer to SCM
1105128 CONSTRAINT_MGR DATABASE Import dcf does not clear out user defined schedule.
1105195 SIP_LAYOUT WIREBOND Request that Tack points default to a "fixed" position after Generate Bond Wires.
, }3 |7 M' x4 E1105249 ALLEGRO_EDITOR OTHER PDF out--- component user defined prop doesn't list the prop selection form
; @  \0 j7 ~" U- u0 C1105443 PSPICE AA_OPT Parameter selection window in optimizer does not list param part
1105818 ALLEGRO_EDITOR INTERACTIV Menu-items seperators are clickable and menu goes away when clicked
1105822 ALLEGRO_EDITOR SCHEM_FTB Netrev failing with compact pin syntax
6 A8 G5 e4 d! f! c9 F1 T+ p, p# h1105993 SIP_LAYOUT LOGIC Import netlist no longer works with co-design die in SiP 16.6
1106332 SIP_LAYOUT OTHER sprintf for axlSpreadsheetDefineCell writes characters in upper case only
1106786 CAPTURE SCHEMATICS Bug: Pointer snap to grid
1107132 FSP OTHER Altera ArriaV (5AGXMA5GF31C4) support.
) I! B8 {& B! M7 r1107151 ALLEGRO_EDITOR ARTWORK Shape filling removed when changing artwork format to RS274X in Global Dynamic Param
1107237 SIP_LAYOUT WIZARDS Updating a Die using the Die Text In Wizard will error out and not finish
1107371 ADW COMPONENT_BROWSE ADW preset Warning filter is spelt incorrectly. (Wraning).
1107599 CAPTURE STABILITY Capture 16.6 crash when trying to invoke
, ~/ v+ V( a& _1108118 ALLEGRO_EDITOR OTHER PDF Publisher pad rotation messed up with flashed pad.
$ z# Y5 o$ r) F" W: W1108574 ADW COMPONENT_BROWSE LifecycleStatus functionality does not work when in Metadata mode. Work correctly in PPT Mode
/ r! S' i# u) l1109095 SIP_LAYOUT WIREBOND Bondfinger move in hug mode create drcs
! @* o% _+ K! t8 z: H1109113 ALLEGRO_EDITOR DATABASE Allegro Netrev crash with SPB 16.6
) `( @6 Z& A8 {+ J, Y1109622 SIP_LAYOUT DATABASE In a wirebond design, the ratsnests with 'Closest Endpoint' should not point to the die pins.
1110077 ALLEGRO_EDITOR DRC_CONSTR Duplicate Drill Hole DRC's are not shown for Pins overlapped in same symbol unless "Min metal to metal" DRC is turned ON
: y# M# B8 e5 V& z( a! T1110256 ALLEGRO_EDITOR SHAPE Auto void on dynamic shape is not correct in 16.6
4 S* I  f" h+ B) s# X1110264 RF_PCB FE_IFF_IMPORT IFF Import in DEHDL has component offset
1 {' J$ k+ c8 h' u# K0 j9 ]1111226 ALLEGRO_EDITOR DATABASE Name too long error with Uprev command when output file name exceeds 31 characters
3 E* I, j; ]# \9 q1111234 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figures triangle, hexagon and octagon in NC drill legend
. S0 ?6 G. v4 C: e  c2 l1112431 SIP_LAYOUT COLOR Frequent crash while working with latest version of CDNSIP
3 e3 N! y) K6 ?4 P# I1112493 ALLEGRO_EDITOR DATABASE Customer does not like 16.6 Ratsnest points Closest Endpoint
- I7 G/ v' f5 j# ~/ r! s1112774 GRE CORE Allegro GRE not able to commit plan after topological plan
1113908 ALLEGRO_EDITOR COLOR Dehilight command fails to remove highlight pattern on a cline, without removing net custom color.
6 r$ C% Y) i9 i0 P1114815 ALLEGRO_EDITOR OTHER Q1: Switchversion error when reading -fa file
1114994 ALLEGRO_EDITOR DATABASE Getting an error after upreving components to 16.6

游客，如果您要查看本帖隐藏内容请回复

weigaozu

感谢分享，呵呵。
/ |8 q4 _8 C9 U2 j

l81004666

最新的补丁包含了之前版本的补丁内容吗？

lgl2466

Jason022

l81004666 发表于 2013-5-2 23:38
) t% t: t( \! s: {最新的补丁包含了之前版本的补丁内容吗？

包含，只需装最新的补丁就行。

l81004666

谢谢

wolf343105

谢谢,ding

wxmcumtb

更新的好快呀。。。。。。。。。

ydw13

感谢分享，呵呵。 百度网盘已经被干掉了

icebluexiong

谢谢分享

wkls201

下来看看~~~~