|
|
08的是这样的，装了09会多出前两项，我没有忽悠大家，冤枉啊
) |# V( O8 d' K3 ]8 m
. l" n$ h1 A5 u6 I" F; H: _! @DATE: 10-21-2011 HOTFIX VERSION: 008
' ^/ R- `1 i. U1 m, N===================================================================================================================================
$ V: V3 y/ G4 TCCRID PRODUCT PRODUCTLEVEL2 TITLE
) f' G8 b, J) G% O===================================================================================================================================
2 m- c- C1 ~& m' e( V906827 ALLEGRO_EDITOR DATABASE Logic > Parts logic does not work correctly.* k) F8 [, r. F# Q1 E# h4 i" l7 l
923346 CONCEPT_HDL CORE Not able to move the reference designators inside hierarchal blocks after uprev to 16.55 \/ U D3 D2 U9 O, H) f3 }- q w
926347 ADW COMPONENT_BROWSE Usability- Libflow Part check in comment should end up in Comments attribute for UCB/Designer to see it
! D( Y; u S" i1 _% g929348 F2B BOM Warning 007: Invalid output file path name
' A3 A9 Y5 h7 q( g6 R$ {929777 CONCEPT_HDL OTHER Component Revision Manager gives internal error
7 D, H2 w1 A. G" P X+ u930783 CONCEPT_HDL CORE Painting with groups with default colors! X" H& G. l; `; K1 ^8 |
936748 ALLEGRO_EDITOR INTERACTIV "Unplace Component" menu inconsistent between General Edit and Placement Edit Mode.
+ C. f0 |% X/ T: s/ h, a6 G0 F: B$ f9 |, C; V938143 ALLEGRO_EDITOR CREATE_SYM Why is this Extra Property 'ECSET_MAPPING_ERROR+ K. J5 k8 A; m
938281 SIP_RF OTHER export_chips creating bad data when symbol is split and contains V- V+ pins! A+ b8 }* ~" f% D
938812 ALLEGRO_EDITOR SYMBOL Cannot create a BSM with this DRA, errors out but does not state a reason.& B7 X f4 v; I) L* N' R
939075 CAPTURE TCL_INTERFACE Texts are getting garbled in command window
: z9 x8 d% U; p1 `9 s939193 F2B PACKAGERXL ERROR(SPCODD-439): Connectivity server is unable to load the design.
: @9 e2 `3 n. s4 k939199 CONCEPT_HDL DOC "Retain electrical constraint on net" mismatch between schematic (YES) and design (NO)
8 ^* c* I" R) v# k& t0 v939346 ALLEGRO_EDITOR SHAPE Shape disappears when updating with variable shape_rki_autoclip set.
" A* w9 |1 ]# B2 Y: d- A1 ~/ I939901 CONCEPT_HDL INFRA NET_SPACING_TYPE shows ??on lower hierarchy level nets after Upreving to 16.5 version.
) c6 ?$ l, i. t6 L7 p: A8 ]939918 PSPICE PROBE Print > Preview for output file causes Pspice crash.
9 x9 l4 ~3 Q9 C. N2 T: G940217 CONCEPT_HDL COMP_BROWSER UCB reports 'No Symbol found for the part'
5 n7 x9 W3 h$ E2 k& K7 p! n: Y& @940835 CONCEPT_HDL INFRA Desing package different after uprev to 16.5 where comp instance propeties are lost lost1 Z/ {+ g! ^; s H
941125 ALLEGRO_EDITOR DATABASE Performance advisor doesn't skip non plated slot padstacks
( ~7 o7 i# o+ [0 F6 @6 l941876 SIG_INTEGRITY OTHER Illegal model name cause pxl fail in 16.3
! S3 t+ ]. }" m9 J& a942210 SCM OTHER Is the Project File argument is being correctly passed?
) L4 b* u2 u5 q6 j5 Q( F942274 CAPTURE PROJECT_MANAGER Crash on renaming a Design Cache part in Project Manage after doing replace cache$ \0 v7 _* A% ]6 o/ O
942839 ALLEGRO_EDITOR GRAPHICS Graphics Issue- Pads are not visible* }. H4 |, o2 d
943055 ALLEGRO_EDITOR SKILL axlDBCreatePropDictEntry causes application to crash |
|
[复制链接]
/1 
发表于 2011-10-28 19:40
收藏
淘帖
支持！
反对！
楼主
发表于 2011-11-1 12:55
