关于FPGA的DS18B20模块的时序问题，感觉一点错都没有啊...

littlestupid

求大神指导一下到底哪里错了，已经调试了三四天了，不管怎么调temp的值都是0.。。

module DS18B20
(
0 w. n2 s7 r! ACLK48M,
1 \3 r$ u) [0 w//RST,
DQ,
6 L2 o+ y) e& |2 W/ P. Btemp
( @2 \0 z; U% s);
# [$ [# F9 D1 \# u/ ?1 l( f0 Y//Port declaration
( U2 L. k' K1 |8 L( ninput CLK48M;
% @5 I1 b8 q1 ~* [//input RST;
) e; |- U- E2 |3 T8 a8 p7 i- Jinout DQ;
7 A! W4 [9 d  `; ]! aoutput [11:0] temp;

reg [7:0] Cnt;
reg clk1MHz;

always@(posedge CLK48M)
begin
if(Cnt==8'd23)
, W" v+ {8 ^& ]  }2 x( E0 l# ^1 n: Tbegin
, T: m) p2 e; sCnt<=8'd0;
clk1MHz<=~clk1MHz;
$ }0 B6 B& @+ D9 B, W& ^/ u" e% qend
7 {8 o) s+ |9 F9 \6 `/ m3 a, telse
Cnt<=Cnt+8'd1;
' f+ L" G1 v1 C# Q/ H) a' G' Mend

* L9 R3 }2 Y8 `2 Y7 x; X9 bparameter IDLE = 11'b000_0000_0001,
DO_RESET = 11'b000_0000_0010,
CMD_CC = 11'b000_0000_0100,
CMD_44 = 11'b000_0000_1000,
CMD_BE = 11'b000_0001_0000,
WRITE_BYTE = 11'b000_0010_0000,
Write_High = 11'b000_0100_0000,
Write_Low = 11'b000_1000_0000,
+ u+ Z4 m/ s4 v) s3 U' A0 @WAIT_750ms = 11'b001_0000_0000,
READ_BIT = 11'b010_0000_0000,
GET_TMP = 11'b100_0000_0000,
% Y+ N% \9 m5 k; F  `WAIT_4MS = 11'b100_1000_1000;
6 s5 ~% J# w$ ?  K5 E  ]//-------------------------------------------------------------------
reg [10:0] state;
reg [31:0] counter;
" l# Q6 y0 y) N/ Sreg DQ;
; u2 E- [& o7 J1 F+ o: |0 Y7 Mreg [7:0] write_byte;//中间寄存器,保存主机要写的指令字节
reg [3:0] write_byte_cnt;
1 C& x0 O& S5 S+ c; X* N! mreg [1:0] byte_flag;
reg [3:0] read_bit;
% {, T2 ?$ c! {1 Mreg[11:0] temp;//12位温度数据
reg TMP_bit;

always@(posedge clk1MHz)
$ n; c) O: I- ^  t4 \: pbegin
case(state)
IDLE:
begin
* W. R! z" \6 C8 o7 I2 r3 m" tDQ<=1'bz;//空闲状态释放数据总线,由外接上拉电阻将DQ数据线置高
counter<=0;
write_byte_cnt<=4'b0000;
byte_flag<=2'b00;
read_bit<=4'b0;
8 L& w  I' U$ f. ?" nstate<=DO_RESET;
end
3 G! g  j6 \1 S" Y" vDO_RESET://主机拉低数据总线持续至少480us，然后释放总线
# g) L2 \* p. t6 G% E7 A: ]begin
- T2 o; H2 A; h3 n2 tif(counter<=480)
: U$ C4 P6 F" Y: ^) rbegin
DQ<=1'b0;//拉低数据线480us
5 a$ r% t! |, Xcounter<=counter+1'b1;
6 j5 }8 `7 r$ Xend
else if(counter>480 && counter<=780)
% C' j4 q- b  {begin
4 y, o. X  x; q  k; F0 aDQ<=1'bz;//释放数据总线60us+240us=300us
counter<=counter+1'b1;
if(DQ)//检测从机是否发送Presence Pulse(持续60us~240us低电平)
( Q( s& i, I* i1 b3 z( k3 |# vbegin
# @# u3 [: F* I  Hstate<=CMD_CC;
9 k" `5 }! C( W( [counter<=0;
end
5 S, e, S. ~5 E* E0 {1 J& ?6 Melse
begin
* m; o, G0 C5 Q3 y6 R8 z+ D4 D7 cstate<=IDLE;
end
- k" m2 }8 r" }end
' p8 t# y# F$ Bend
CMD_CC:
, B7 C6 E' q: S9 [; Y) o1 Ebegin
  X" `% u+ C5 v4 [4 n" uwrite_byte<=8'hCC;
state<=WRITE_BYTE;
end
WRITE_BYTE://写指令字节,由低位向高位依次写入从机
" N% p4 q# U8 C3 u+ E$ H! M' |begin
: c; W( ]8 t/ N; T( N7 Wcase(write_byte_cnt)
4'b0000:
begin
state<=write_byte[0]?Write_High:Write_Low;
write_byte_cnt<=write_byte_cnt+1'b1;
7 P$ G$ q, N6 zend
% |5 G0 i! D- O4'b0001:
. l$ e/ q5 ?( ]; D8 S3 Ubegin
state<=write_byte[1]?Write_High:Write_Low;
( y; |3 {) P' G6 y2 S  Twrite_byte_cnt<=write_byte_cnt+1'b1;
end
4'b0010:
$ z! R7 |4 l5 Q7 ~# J) \begin
0 @/ b; S0 x5 |, p; D4 `, ystate<=write_byte[2]?Write_High:Write_Low;
( L, k: J2 _& i- E& C2 ~& f# Iwrite_byte_cnt<=write_byte_cnt+1'b1;
end
4'b0011:
, S! {, L% V7 b/ |* Lbegin
state<=write_byte[3]?Write_High:Write_Low;
1 t/ ~2 M) c* h  y5 t! M2 Awrite_byte_cnt<=write_byte_cnt+1'b1;
# ]$ I3 K" L+ Y+ A# q+ \: U! b$ ]end
: P7 N' @8 G9 E* X4'b0100:
4 B7 x& w1 B: X5 c; `% J8 \begin
2 S2 _  F# U# hstate<=write_byte[4]?Write_High:Write_Low;
write_byte_cnt<=write_byte_cnt+1'b1;
end
4'b0101:
begin
state<=write_byte[5]?Write_High:Write_Low;
write_byte_cnt<=write_byte_cnt+1'b1;
& x$ ^% p$ W$ qend
4'b0110:
begin
state<=write_byte[6]?Write_High:Write_Low;
write_byte_cnt<=write_byte_cnt+1'b1;
end
3 b8 Z# M( O& X2 m4'b0111:
' t: e+ J1 ^/ }) h4 rbegin
state<=write_byte[7]?Write_High:Write_Low;
/ ^( t4 Z) z$ @$ F3 ^2 {write_byte_cnt<=write_byte_cnt+1'b1;
end
4'b1000://8bit字节写完后在此处进行状态转换
0 p4 t- @+ u0 D  T/ ?( pbegin
write_byte_cnt<=4'b0000;
case(byte_flag)
$ [* p9 U( j; e3 J% B2'b00:
begin
state<=CMD_44;
byte_flag<=2'b01;
/ a4 |, K. }; X( [" S, z) W9 rend
+ ^# y& D- h+ V8 w1 G2'b01:
. u6 k* U; w; f! P0 zbegin
9 @2 N+ u4 k7 b$ N# _0 _5 Z1 rstate<=DO_RESET;
6 Q( R5 c" j) G7 c+ U- r( r0 J3 |byte_flag<=2'b10;
) A) H+ K' r' }( D, Mend
3 h% x6 o* i; y* g& T6 o9 E8 E2'b10:
begin
4 R; `& k- B/ B. J0 v0 X+ h$ Dstate<=CMD_BE;
byte_flag<=2'b11;
- N) r; N/ c* {, r" i- z2 fend
2'b11:
4 S6 r! Z! ?6 Q& S& d8 O! ]begin
' |3 ^; {) ^$ h/ u2 ?2 `state<=GET_TMP;
4 y5 l$ v( T) f$ j7 Jbyte_flag<=2'b00;
! X0 O0 X( m) n& k- |$ h% N- J8 Yend
endcase
end
default:write_byte_cnt<=4'b0000;
endcase
end
Write_High://写‘1’时序:主机拉低数据线1~27us,然后释放数据总线30~数千us.
7 C6 W- A/ j* i0 _+ k4 Tbegin
if(counter<=8)//拉低数据线15us(至少1us)
begin
DQ<=1'b0;
counter<=counter+1'b1;
& ]1 r5 L$ ?8 a/ o$ y, [end
else if(counter>8 && counter begin
DQ counter end
( A/ J- Y) X- n8 jelse
begin
counter state end
end
7 y/ ~" p1 i/ k- w# L. B: c( oWrite_Low://写‘0’时序:主机拉低数据线30~227us,然后释放数据总线1us~数千us.
begin
0 G0 J- ~1 S2 O( uif(counter begin
; k2 O: l/ N" a5 T# z8 `( P# Q; P& VDQ counter end
# @- v# i, z( m6 n/ _% lelse if(counter>78 && counter begin
0 l8 i5 t' o& c8 S$ I7 wDQ counter end
6 x# G8 Y( d9 u) Eelse
, e( M. |: z7 U, d0 Ibegin
* h" M: X4 e: D9 _* u* Tcounter state end
end
. {( _& n, K& y) s( L- SCMD_44:
begin
write_byte state end
2 q; @# Z- x$ |/ @8 CWAIT_750ms:
! W; J9 q) I1 W  Y$ mbegin
if(counter>750000)//实际上只等待几us甚至不等待也可以
/ j6 d; M2 t7 g( ~+ l7 Ibegin
state<=DO_RESET;
counter<=0;
* U9 V$ A, h0 F+ Q2 Jend
else
counter<=counter+1'b1;
end
CMD_BE:
2 Y0 G2 V* D# mbegin
3 g! x  Q8 k  K9 K; R, Pwrite_byte<=8'hBE;
; ~! g  x/ L! x9 @state<=WRITE_BYTE;
end
GET_TMP:
* Q& I& |1 H( d! U% R4 w6 |  a# }begin
case(read_bit)
$ L; j' D+ G9 y4'h0:
7 P4 @* K/ s! ]8 V  t5 J7 ubegin
state<=READ_BIT;
read_bit<=read_bit+1'b1;
# u3 h- S+ @% Dend
4'h1:
begin
- k9 I, A% @% mstate<=READ_BIT;
read_bit<=read_bit+1'b1;
. i; [' a# M1 W! Htemp[0]<=TMP_bit;
8 D3 X  i. c" C% l2 gend
4'h2:
begin
state<=READ_BIT;
7 f! B# E* z7 u7 qread_bit<=read_bit+1'b1;
% N0 P) c4 G5 h( P; X( Q* o+ \temp[1]<=TMP_bit;
end
4'h3:
begin
2 r" b+ Y9 x- V. C- `; w  mstate<=READ_BIT;
: ]  K/ t# R: T; ~; c# ^read_bit<=read_bit+1'b1;
3 Z" N+ p; n" Z: k! X+ U6 W# atemp[2]<=TMP_bit;
+ y; u, u) o- m% q+ f/ ^! vend
4'h4:
7 k7 Y. H) e: n- W" H$ hbegin
! v  z8 E6 P7 rstate<=READ_BIT;
read_bit<=read_bit+1'b1;
temp[3]<=TMP_bit;
end
4'h5:
& {& F  z5 G2 `9 N0 wbegin
state<=READ_BIT;
  z* h+ g% K+ E" Z8 k7 p3 Uread_bit<=read_bit+1'b1;
temp[4]<=TMP_bit;
4 P! Q) [9 A0 r% g( zend
" @3 O: b7 K! G; ?4'h6:
: d4 Y; Y- O. \: H+ [7 Ibegin
state<=READ_BIT;
read_bit<=read_bit+1'b1;
temp[5]<=TMP_bit;
end
4'h7:
begin
state<=READ_BIT;
, ~0 I8 N* [' ?, t6 }, w5 ~read_bit<=read_bit+1'b1;
temp[6]<=TMP_bit;
end
" D; p9 B  w8 F! u4'h8:
begin
7 M, b3 O5 s5 ]. F0 Istate<=READ_BIT;
0 l2 n. T3 \0 n. l' Vread_bit<=read_bit+1'b1;
temp[7]<=TMP_bit;
end
$ ~, R1 R% w" w- P' ]4'h9:
begin
state<=READ_BIT;
read_bit<=read_bit+1'b1;
$ m0 ]6 U5 C1 q0 j9 a! [temp[8]<=TMP_bit;
5 ~3 P! i3 y! ^7 Y( H4 G7 |& Zend
- e7 q4 p+ m6 B8 i3 J# |4'hA:
begin
9 A# _& K9 y/ A7 t6 s0 qstate<=READ_BIT;
read_bit<=read_bit+1'b1;
  r2 O# H4 {+ V; E  w2 P& z% ptemp[9]<=TMP_bit;
& y1 ~& O5 O' X+ D8 p. u# v* Lend
( E/ _; U' S. W3 r4'hB:
" j$ T$ L, ]4 ?6 J8 J/ N2 Sbegin
state<=READ_BIT;
0 Q$ `9 K3 a3 Q8 D) [" q9 i' Vread_bit<=read_bit+1'b1;
, ?& X/ S& n7 d7 L* x: etemp[10]<=TMP_bit;
end
4'hC:
! A0 O& B( [( z) I1 n; w, Ubegin
state<=WAIT_4MS;
. Y" l8 ~. U( {6 G! {  Kread_bit<=4'h0;
6 N8 p: H2 O0 N( p& x; Dtemp[11]<=TMP_bit;
end
default:read_bit<=4'h0;
endcase
end
) ?. U4 k6 W9 X. L" v6 J0 ^3 E5 vREAD_BIT://读时序:主机拉低数据总线约2~4us,然后释放数据总线2~4us,再读取DQ数据线上的值
begin
& k6 E% \+ l# F- g/ S4 c5 j4 G) X; sif(counter>=0 && counter<=3)
begin
DQ<=1'b0;//主机拉低数据总线约5us
counter<=counter+1'b1;
end
: o. O* u! k6 c- V( q" delse if(counter>=4 && counter<=7)//最迟必须在29us处释放数据线
begin
DQ<=1'bz;//释放数据总线5us
counter<=counter+1'b1;
end
else if(counter==8)
begin

counter<=counter+1'b1;
6 @- e. J* T/ {; \: h: N; m9 vTMP_bit<=DQ;
end
else if(counter>=9 && counter begin
counter end
else
( Q) A3 D" }. X- v5 Cbegin
state counter end
: V1 D) S7 {' send
5 E+ ^2 Z! V5 }WAIT_4MS:
# B# O& h* x; @begin
if(counter>4000)
begin
state<=IDLE;
counter<=0;
end
6 w! m# |) i) J# N; p: [else
begin
counter<=counter+1'b1;
  h& k9 @, C2 F" H# Uend
) A+ e+ l8 l* V9 v3 [end
default:state<=IDLE;
. R9 t3 i# t1 p0 R7 {% ?* Q) @endcase

end
" E3 H* L# D( R4 aendmodule

7 }) n5 X/ M9 _, F# l

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hzh123

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