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本帖最后由 i4dm99 于 2018-10-24 10:05 编辑
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" n0 a. I9 |# i4 S2 x感谢分享,能共享一下都更新了哪些内容吗
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$ {+ }* i: R) g2 ]Fixed CCRs: SPB 17.2 HF048- p# V( D8 T }- [4 n9 s5 F
10-13-2018
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CCRID Product ProductLevel2 Title
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1 I4 U5 n5 W% h1913039 ADW ADWSERVER EDM Library Server exits with error message on starting library server service
. r1 E% p/ @% A1 ?1 C/ L0 q& q1709155 ADW COMPONENT_BRO Search query does not search for all the parts in the library" d$ m- @* x# \
1827231 ADW COMPONENT_BRO Clicking the 'a' key in Part Manager launched from DE-HDL crashes DE-HDL
) E8 `0 k. r- F! p, N1903818 ADW COMPONENT_BRO Parts that have comment_body do not display version7 E, V% |. E! M2 N
1917961 ADW COMPONENT_BRO Component Browser PPL column values are truncated when selecting the top '*' filter. W) {9 u7 C! ^
1938172 ADW COMPONENT_BRO Symbol version with COMMENT_BODY set to TRUE cannot be instantiated
$ J0 A1 @5 y6 _- e7 k* ~1914103 ADW CONF conf creates incorrect path in fetch_dump.ini when MLR is enabled.
e: a) v# Z- a1911422 ADW DBADMIN RuleP101 - PACK_TYPE check against schematic model not working
5 O* |, J; l: r& S1926691 ADW DBEDITOR Adding a new classification and immediately trying to delete it results in errors
' [3 u0 k/ p6 f- V4 ?& H9 y1926694 ADW DBEDITOR Renaming a classification and then renaming it back to the original results in error6 O* P# ^7 d' ]% g) t
1934870 ADW DBEDITOR Adding a new classification and immediately trying to delete it results in errors+ Z. c1 |/ Y& y
1872387 ADW DSN_MIGRATION Design Migration does not cache all used parts into flatlib/part_table.ptf
/ l4 Q E) T1 g$ |$ ?1254292 ADW FLOW_MGR Flow Manager Open Last Project should open last project closed
5 a- M- P& k2 C1281817 ADW FLOW_MGR '-proj' switch in 'pcbdw_fm' does not work; launches Flow Manager without loading any project
3 p6 ^2 w) G; n G# Y3 g# \1727286 ADW FLOW_MGR Product options for PCB SI and Power Integrity are incorrect in the flow and tool launchers$ `/ y% |' K% a
1875498 ADW FLOW_MGR EDM fails to open or becomes unresponsive.
/ [6 r" b. `8 p1879386 ADW FLOW_MGR Unable to access COS with the default Firefox version in the 17.2 installation- o0 C- y- Q0 |0 t& C; H
1922541 ADW FLOW_MGR Warning message for unavailability of Java version appears on opening a project on Linux U. J" n" C, ]4 s8 |
1945451 ADW FLOW_MGR Checklist does not work with two-byte characters
6 ]' Q! `5 L# D1956213 ADW FLOW_MGR Not able to invoke Flow Manager on the remote system' C( A; H: ~/ m
1892285 ADW LIBDISTRIBUTI Symbol not consistently available in 16.6 ADW Library
0 G+ n5 N& e6 f- e8 R2 Z6 m/ h. T, d1 ?0 h$ K1961731 ADW LIBIMPORT libimport fails to create tar for two Capture models
0 M; R* [- ~! t6 \- x8 G1836620 ADW LRM Library Revision Manager crashes on clicking Help
) @, H" S' v# E1961845 ADW PART_BROWSER Error regarding environment variable
z- c* \5 C/ Q+ K6 N/ i1890782 ADW TDA Launching TDO dashboard connected to PLM returns a license error
/ q8 K5 s. h% d! ~ {# v z; Q1980914 ADW TDA Cannot start Design Entry HDL and Component Browser in a TDO design8 j- V7 j2 s% v) }# z" N+ j
1833750 ALLEGRO_EDITOR 3D_CANVAS Soldermask Text is not shown in 3D Canvas
! N1 x% B$ a2 w' H3 U; h( E1891230 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas Viewer not bending PCB with proper radius
9 Y4 ] |& w) \( d4 y6 |" A1913338 ALLEGRO_EDITOR 3D_CANVAS STEP models missing from exported .stp file
" t8 T$ u2 s8 B* o1927507 ALLEGRO_EDITOR 3D_CANVAS Get Error: All bend operations are disabled due to licensing and/or DLL installation issues on invoking 3D Canvas( C. a2 `/ d9 u
1931508 ALLEGRO_EDITOR 3D_CANVAS Place Bound Bottom is displayed on Top, when dra is opened in 3D Canvas; H0 L# v6 R g5 _9 h) x
1943060 ALLEGRO_EDITOR 3D_CANVAS Placebound bottom is not showing correctly.2 {: x, D+ R2 u; c2 d2 y
1950099 ALLEGRO_EDITOR 3D_CANVAS Place Bound Bottom is displayed on Top, when dra is opened in 3D Canvas$ n: b: C2 W \
1988307 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation5 B" r% D$ {, m n0 g6 U1 N
1923585 ALLEGRO_EDITOR ARTWORK Additional unwanted subclasses appear in film control when a new film definition is added( F7 U+ ]5 e) D! C0 m0 a
1944079 ALLEGRO_EDITOR COLOR Export of Board Parameters (Net Colors) does not contain entries for nets with spaces Y$ F5 S* d* C. o
1856320 ALLEGRO_EDITOR DATABASE Donut pad fails to connect with cross-hatched shape in full contact thermal mode, despite hatch overlap of donut.; ]% m8 V7 _9 j# \! X& l( x, ?- [
1912313 ALLEGRO_EDITOR DATABASE Database corrupted during background process* n1 u# d6 H/ y
1913344 ALLEGRO_EDITOR DATABASE When changing accuracy of design, the thermal relief for donut pad's outer pad connects to inner pad1 d8 V2 Z1 M$ |: M- y
1914470 ALLEGRO_EDITOR DATABASE Release 17.2-2016: export libraries command does not inherit posi/nega information
4 _* G& E3 p4 {# I1932086 ALLEGRO_EDITOR DATABASE Unable to resolve DBDoctor error
# w9 E2 b9 W9 h& {7 ~8 j1963932 ALLEGRO_EDITOR DATABASE DB Doctor is not recognizing placed parts and showing them as unplaced. \# \$ P* s$ a( Y7 N( p; T: B
1987735 ALLEGRO_EDITOR DATABASE Interior sub-lamination backdrill holes are displayed with Top Soldermask pads where backdrill does not exist
7 P& }) g. D z. j4 t, W5 S1 ?: i; k1977622 ALLEGRO_EDITOR DFM Not able to add value '5' or multiples of 5 in in DFF constraints for maximum stacked via count
) W) L S/ t& z* C% m1892809 ALLEGRO_EDITOR DRC_CONSTR NODRC_ETCH_OUTSIDE_KEEPIN property is not working on TEXT
# X o) t$ c4 J) R# x |: N9 X, T5 b D1894765 ALLEGRO_EDITOR DRC_CONSTR DRC for no_drc_component_board_overlap is not created if the place bound is outside Place Keepin
/ c( @. q7 D% A" W. l2 |1896627 ALLEGRO_EDITOR DRC_CONSTR Moving components takes long time while doing placement
, z5 {0 o; ~4 `6 i1 W$ E7 E1914591 ALLEGRO_EDITOR DRC_CONSTR Spacing constraints for Mechanical to Hole shows resolved constraints different from the actual air-gap/space
% s: b- J6 N$ _# C5 L- l7 x1956468 ALLEGRO_EDITOR DRC_CONSTR DRC getting generated while moving the uvia and getting removed after updating DRC./ I( a; j2 G, s! p3 T8 A% o) `
1884149 ALLEGRO_EDITOR EDIT_ETCH Arced Routing of differential pair creates unexpected arc radii6 \ a1 c; v3 o7 s
1891985 ALLEGRO_EDITOR EDIT_ETCH Etch edit does not follow the constraints) Z$ G8 J' Q# D. B) l* _- l( H
1860056 ALLEGRO_EDITOR GRAPHICS PCB Editor crashes on right-click after choosing the Move command7 i# K0 [; S! c& v, |$ D% b# w
1860723 ALLEGRO_EDITOR GRAPHICS APD crashes on right-click when using the Move command2 A4 h) u( I( w+ B% w' i6 I# J
1870058 ALLEGRO_EDITOR GRAPHICS PCB Editor crashes when using Place Manual -H command+ @$ Q; ~+ E' G% N3 }
1930282 ALLEGRO_EDITOR GRAPHICS PCB Editor crashes on executing axlVisibleDesign(nil) from allegro.ilinit
7 v3 E/ ?; O3 r" A) V1882813 ALLEGRO_EDITOR INTERACTIV Unable to set the end point with 'snap pick to' when adding an arc
6 E0 ^, I" Y7 x; j$ @1884725 ALLEGRO_EDITOR INTERACTIV Edit and Move vertex operation not working as desired
4 m7 L/ o; j! r0 Z4 m1902359 ALLEGRO_EDITOR INTERACTIV Connector boundary remains ON for a layer if visibility toggles in Shape Edit application mode
& Y( |1 H4 A% x$ s( @! j* f1909004 ALLEGRO_EDITOR INTERACTIV Parameter description showing wrong for Padless Holes under Design Parameter Editor1 T$ ~1 i' _/ t2 K
1912055 ALLEGRO_EDITOR INTERACTIV PCB Editor crashes on Delete By Query - AutoSilkscreen - Find By Query& Q" J: o" I B. G- B# q1 j
1924503 ALLEGRO_EDITOR INTERACTIV Editing shape causes PCB Editor to crash
2 _- r o3 t8 p, T7 N2 u4 J1929614 ALLEGRO_EDITOR INTERACTIV Unable to Place Via Array when Staggered ring is selected in Global Ring Parameters." `/ M8 F* ~8 [, a7 j6 N: i
1938523 ALLEGRO_EDITOR INTERACTIV Change Shape Type message is same for dynamic and static shapes; H( H% S; @8 N; f8 ?7 a% e
1940827 ALLEGRO_EDITOR INTERACTIV Irrelevant/incorrect warning message when doing Edit- Change on Clines0 b0 Q* y5 |7 g
1872653 ALLEGRO_EDITOR INTERFACES DXF export shows embedded layers in the layer configuration file3 A1 }; O Y$ h9 M# }
1873971 ALLEGRO_EDITOR INTERFACES IDX proposal comments are not shown when importing the IDX file into Allegro; u( }6 _2 Y% v
1892172 ALLEGRO_EDITOR INTERFACES STEP Package Mapping form needs to be larger
0 z! I; z3 Q5 q& S: T) M1893311 ALLEGRO_EDITOR INTERFACES A line became two lines after import dxf
) \5 C4 u% n# W1 r m" o6 m+ o# D1937816 ALLEGRO_EDITOR INTERFACES Unit as % in Property Definition not supported by SubDrawing. d* r5 l9 I9 g7 V( j5 Z
1973084 ALLEGRO_EDITOR INTERFACES Physical library not placed if design and IDF database not matched while running
$ ^4 z5 O, ?8 a$ n3 v* s1987526 ALLEGRO_EDITOR INTERFACES IDX import Fails to recognize SURFACE FINISHES Class2 \' f) g7 J2 n0 _- N
1872856 ALLEGRO_EDITOR IN_DESIGN_ANA Message displayed when creating directed groups needs to be improved
6 O+ a' V; ~( M5 e1900832 ALLEGRO_EDITOR IN_DESIGN_ANA RTP: Return Path DRC does not check circle void correctly& T4 D" w" h z4 R9 \
1935641 ALLEGRO_EDITOR IN_DESIGN_ANA Return path DRC crashes PCB Editor+ \) L0 d& E p. k
1649465 ALLEGRO_EDITOR MANUFACT Manufacturing options are not visible in OrCAD PCB Designer legacy menu
5 x& C& t$ W; J) ~1873417 ALLEGRO_EDITOR MANUFACT Autosilk fails to add line information. Only part of the line is getting copied to the autosilk layer.
* c2 K$ w+ T* J8 ? X* t1911596 ALLEGRO_EDITOR MANUFACT Documentation Editor drill chart shows two different rows for the same slot.
( S! ?% Y9 h1 X. a- i$ c1937721 ALLEGRO_EDITOR MANUFACT Drill figure character scaled up in GERBER
2 K" ?; I5 [3 [" i1957768 ALLEGRO_EDITOR MANUFACT Import IPC2581 on cross-section does not import line width and impedance
! |" p! g& f3 C/ ^1969363 ALLEGRO_EDITOR MANUFACT Pressfit connector backdrill depth is considering MNC Layer. F: \4 g9 m; O
1891102 ALLEGRO_EDITOR MULTI_USER Rejected by server error messages when using Symphony Team Design5 v# T% E% I! U1 }
1928082 ALLEGRO_EDITOR MULTI_USER Unknown SubClass BOUNDARY/MULTI_USER_LOCK automatically added when defining Artwork Output.% g6 m/ K# q4 N% L+ X' k8 }
1976705 ALLEGRO_EDITOR MULTI_USER Symphony client disconnects from server without any notification - despite ping mechanism
|/ f9 a: M) L3 S1972554 ALLEGRO_EDITOR NC Mill symbol moved from Nclegend-slots-1-2 to Nclegend-1-2 subclass if nc_param.txt not present1 a A( G" _3 J" P* |) e2 [
1914412 ALLEGRO_EDITOR OTHER Autosilk lines do not clear padstacks that are not rectangular
$ K# P2 L5 f' A j( B3 L2 m1921933 ALLEGRO_EDITOR PAD_EDITOR column clearance cannot reset to 0 in padstack editor
. O# w6 O7 \8 n5 r+ S8 ]1922234 ALLEGRO_EDITOR PAD_EDITOR DBDoctor reports 'illegal value for pad' and does not fix when zero corner radius for Rounded Rectangle is defined
9 d S3 t0 i- i# F% \2 m3 p1932183 ALLEGRO_EDITOR PAD_EDITOR Drill Symbol information not exported in Padstack XML if Drill Figure in none
. j& K6 _" w, j' r7 r1934880 ALLEGRO_EDITOR PAD_EDITOR Shapes with offsets not displaying properly in Padstack Editor views; l) ~ {8 @7 y5 {- J4 E
1813270 ALLEGRO_EDITOR PLACEMENT When a place replicate module is updated, the vias used in thermal pad are removed
' r- M" [4 q; a0 P! K1840275 ALLEGRO_EDITOR PLACEMENT Placing component with the Mirror option causing display problems
; i3 `, ~( f4 C6 q' }! E: v1854099 ALLEGRO_EDITOR PLACEMENT Align components to zero spacing causing mirrored components to overlap4 ?8 }, r1 k' Y% m+ U: Z
1854696 ALLEGRO_EDITOR PLACEMENT Pins shown incorrectly when the Alt Symbol and Mirror commands used consecutively! T- ~; F9 W8 e; L
1862863 ALLEGRO_EDITOR PLACEMENT Too many messages in the command window when symbol does not support mirroring
/ ~, \9 j) ~/ B% r8 W7 f1909857 ALLEGRO_EDITOR PLACEMENT Using Mirror with Alt Symbol placement displays incorrect graphics
?' w' G3 ]* X1 k* w1 m; m1917128 ALLEGRO_EDITOR PLACEMENT Place - Autoplace - Room when all the components of the room are placed on board causing crash
2 v% |7 g+ d8 S& l; T4 J. r1925144 ALLEGRO_EDITOR PLACEMENT PCB Editor stops responding on using the Autoplace - Room command8 n+ U1 @- h8 Z
1961509 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes on choosing Place - Autoplace -Room8 e/ j% w, @9 u9 J' ]8 e; X" r
1930669 ALLEGRO_EDITOR REPORTS Net 'VSS' not included in the Etch Length By Pin Pair Report
+ L }! Z% a" D% C1 o1982934 ALLEGRO_EDITOR SCRIPTS PCB Editor stops responding if Generate button is used to create script from journal file& |1 A: w# K: t
1337346 ALLEGRO_EDITOR SHAPE Shape Check is generating problem point errors that seem unnecessary9 A" ]. e* j+ }8 M: \$ {( m' M
1396692 ALLEGRO_EDITOR SHAPE Zcopy with expansion not following board outline
_2 `) s4 ^, d7 [8 D+ }7 b% A( T1902001 ALLEGRO_EDITOR SHAPE Shape behaving differently across hotfixes. d- o9 Z, x0 y
1921287 ALLEGRO_EDITOR SHAPE 3D canvas is showing some stray objects
4 P: ]1 w0 ?" w5 d/ u1 _0 o) f! T1936482 ALLEGRO_EDITOR SHAPE Option for Fillet to not obey NO_SHAPE_CONNECT Property
/ `2 g/ u# i% F/ {3 z( r1943899 ALLEGRO_EDITOR SHAPE Only one Shape to Route Keep In DRC in release 17.2-2016 compared to two in release 16.6
4 s* P' `% \: j5 j/ L# n1944041 ALLEGRO_EDITOR SHAPE shape_rki_autoclip makes shape voiding incorrect
3 f" E$ u9 I3 p9 ^0 }% n, B1947675 ALLEGRO_EDITOR SHAPE Shape void error when dv_squarecorners is enabled' \8 t- _9 S/ |9 {) B& s( d
1949250 ALLEGRO_EDITOR SHAPE Shapes are filled even after raising and lowering priority
& T8 {, a! x5 j; u* M2 \$ W5 t1984526 ALLEGRO_EDITOR SHAPE Same net shape voided is inconsistent with respect to vias E- I+ \8 ~( R! J$ X' Q
1984955 ALLEGRO_EDITOR SHAPE Dynamic shape creating same net spacing drcs.7 ?& L+ h. G; Y" t) Z4 \9 j$ p8 s
1839147 ALLEGRO_EDITOR SKILL axlDBGetLength() reports that the segments of a filled rectangle shape are invalid database ID arguments
* u4 j+ o9 O* A1882776 ALLEGRO_EDITOR SKILL SKILL documentation for axlIsBetween() is wrong
& ]3 S9 g6 ?. j1882882 ALLEGRO_EDITOR SKILL Example for axlMathConstants needs correction in Allegro SKILL Reference
4 {$ {& P6 z% R2 z; a4 W: }1902712 ALLEGRO_EDITOR SKILL axlAltSymbolReplace moves symbol to the top of design while replacing
& J ^9 [' j9 D9 i! S2 Y m1906329 ALLEGRO_EDITOR SYMBOL Mechanical Pin to Conductor property set on a pin in a symbol does not pass to the board
0 n& h8 x# g3 r" I4 k! g1911343 ALLEGRO_EDITOR UI_FORMS Global Visibility not turning all layers off. n }- Z3 v6 W& X, J" W
1985584 ALLEGRO_EDITOR UI_FORMS Import logic changes the Current Working Directory
! q1 i, A# c) ] N2 l1987829 ALLEGRO_EDITOR UI_FORMS Import logic changes the current working directory5 ^/ L4 e* B2 s1 y# C( p
1992722 ALLEGRO_EDITOR UI_FORMS After netlist import process, the board file is changing its current path
# A7 [5 l# ^0 F' w, u S7 g1697506 ALLEGRO_EDITOR UI_GENERAL Stroke Editor working in OrCAD PCB Editor of release 16.6 does not work in release 17.2-2016
5 l% O6 l( \8 L& {1702631 ALLEGRO_EDITOR UI_GENERAL Etch Length by Net report does not list correct net name for nets in a bus
/ J' F" z6 \+ [( @" Q1703105 ALLEGRO_EDITOR UI_GENERAL Bus net names are incorrect in reports when using the allegro_html_qt variable/ e2 J2 a% O7 m7 A4 n
1770786 ALLEGRO_EDITOR UI_GENERAL Stroke Editor working in OrCAD PCB Editor of release 16.6 does not work in release 17.2-2016% l) p# `( J5 w7 u6 q0 e3 l
1784938 ALLEGRO_EDITOR UI_GENERAL Etch Length by Net report does not show net names with angle brackets in release 17.2-2016
* t% S. e. Q' O4 K1822557 ALLEGRO_EDITOR UI_GENERAL axlUIWCloseAll is not closing text window in release 17.2-20167 k0 p( I! u4 ?; V: ] Z& @7 V
1836400 ALLEGRO_EDITOR UI_GENERAL Net names are truncated in HTML reports
7 i, f$ w8 p+ U9 M# W6 e1869879 ALLEGRO_EDITOR UI_GENERAL Links not working in the Net loop report. g; O2 o; X$ J2 x. C$ R" L }) ^# P) \
1895878 ALLEGRO_EDITOR UI_GENERAL axlUIWClose()/axlUIWCloseAll() functions do not work when allegro_html_qt setting is enabled.+ J% c7 P4 T$ C! h
1912282 ALLEGRO_EDITOR UI_GENERAL PCB Editor exits with error message on editing objects
, Q- {' |' g; n9 L9 M/ `" `' R A2 d1913962 ALLEGRO_EDITOR UI_GENERAL PCB Editor toolbars change on choosing View - UI Settings - Save Settings and then restarting
) S) J8 t! V# D) D1933172 APD UI_GENERAL Cannot paste text into the command prompt without clicking when 'enable_command_window_history' is set8 K+ A" \! v5 d e" ?
1843712 CAPTURE NETGROUPS Signals shown only for first segment of NetGroup+ e6 \! O! q: A5 M& L
1917768 CAPTURE NEW_SYM_EDITO Missing package pin overview in Symbol editor3 K8 g9 d/ @$ a: O) @
1920088 CAPTURE NEW_SYM_EDITO Package view missing in the new Symbol Editor& d& w( o" `! i3 J! _ T* {
1922196 CAPTURE NEW_SYM_EDITO Snap to grid issue in Symbol editor
- {' U0 a0 r% t4 }' M: U3 Z: _, l+ @; `2 W1927268 CAPTURE NEW_SYM_EDITO View Package is grayed out in release 17.2-2016, hotfix 038 and later versions3 X, o2 c2 }, B
1928012 CAPTURE NEW_SYM_EDITO In new Symbol Editor, View - Package is grayed out3 U$ X$ l/ ]6 [: U+ \
1930865 CAPTURE NEW_SYM_EDITO View Package missing in hotfix 038
d4 \, x3 f( B' X7 k- Q% k1938507 CAPTURE NEW_SYM_EDITO Issues with new Symbol Editor: Justification and spreadsheet usability: c+ k4 t2 u" |& ?
1940869 CAPTURE NEW_SYM_EDITO Missing pins in 'Edit Pins of All Section' table view for 4k resolution but not in 2k resolution
, D5 k+ G: e; a; N- |1940888 CAPTURE NEW_SYM_EDITO Copying pins from a part and pasting on different parts not working properly.& g5 o8 k. A5 t8 X5 a
1942994 CAPTURE NEW_SYM_EDITO Cut / Paste of object in New Part / Symbol editor always pastes on grid
3 _5 c) o. |1 w5 I1944396 CAPTURE NEW_SYM_EDITO JavaScript error while copying from 'Edit Pins of All Sections'
" u6 G9 f$ N0 g2 y1950224 CAPTURE NEW_SYM_EDITO Cyrillic alphabets are not displayed properly on Schematic.
) F$ ?0 O% F9 |+ a( f* E1951369 CAPTURE NEW_SYM_EDITO Cancel closes Symbol Editor" V# L( G$ ~, n( t' p+ @- H) O
1966785 CAPTURE NEW_SYM_EDITO Edit Part is grayed out/ i* p+ t: X0 M5 C2 A$ C( ^
1973135 CAPTURE NEW_SYM_EDITO Issue with new Symbol Editor: cannot copy-paste pins% S9 q% K& E" `6 |
1973344 CAPTURE NEW_SYM_EDITO JavaScript error on opening part from design
: B3 F+ D! f+ T: I; g3 I1974122 CAPTURE NEW_SYM_EDITO Cannot copy-paste all pin list on the new Symbol Editor2 E. ^! k2 m9 _) d. }1 Q
1983593 CAPTURE NEW_SYM_EDITO Script error on copying and pasting to property sheet3 g, u' M+ F; f5 u0 I' r
1929692 CAPTURE OPTIONS PACK_SHORT issues with Pin Numbers that contain letters/alphabets8 r2 j* {" o1 a) Q. c) Y
1876939 CAPTURE OTHER Incorrect Capture renaming error (ORCAP-1310)* ]! G! N3 }* @, q7 U! L' b
1916090 CAPTURE OTHER Incorrect error message when 'save as' fails due to long directory path
! B) w; x$ ]' p: o$ H6 u1921927 CAPTURE OTHER Two functions are mapped to Shift + R in OrCAD Capture in hotfix 038
+ N; b" A; G; A& l# g, u z1946453 CAPTURE OTHER Shift+R shortcut is assigned to two functions.
9 T6 e' L8 R5 b3 ~ X( b4 D1965456 CAPTURE OTHER Shortcut Shift + R is not opening the Independent Sources dialog box' S3 L j) _+ k1 d0 ?$ m- a% f
1968757 CAPTURE OTHER Close CIP is grayed when right-clicking on the tab in Capture.
" b$ @! b* a Z0 R5 ?1938437 CAPTURE PART_EDITOR OrCAD Capture new Symbol Editor Pin Type missing in table& x+ d6 V) S4 r2 C* P* |% H" N
1906757 CAPTURE SCHEMATICS Intersheet reference is overlapping with the offpage connector name
8 j5 a A9 \. B" a' ?6 W/ X; `1867016 CAPTURE SCHEMATIC_EDI Part placeholders not being positioned when moved
8 N. `; \- L, ?+ ]+ I3 v4 c1932837 CAPTURE SCHEMATIC_EDI Parameters graphics are not correctly positioned
; _" C( X6 @' x0 g7 ] g6 G1949518 CAPTURE SCHEMATIC_EDI Getting error when comparing designs
9 u: J& G7 ~" U b: a P; Y1967545 CAPTURE SCHEMATIC_EDI Only section A of heterogeneous part being placed and not sections B, C, or D, `( e+ A! ?" a9 f5 P5 B, b7 n
1933919 CIS DBC_CFG_WIZAR New CIS Configuration .dbc file created in release 17.2-2016 shows release 16.3
) l8 A. { Q* n6 B/ x# |: Y0 j1 w1932550 CIS RELATIONAL_DB VIEW NAME in Relational Database configuration is not working as expected.% E/ V3 A7 s B# A- ^
1832524 CONCEPT_HDL CHECKPLUS Default checkplus rules show body height of 0 (sym_2 of the attached cell). This causes the cell to fail verification./ J3 R @: w/ l7 _
1912023 CONCEPT_HDL CHECKPLUS signalWidth predicate does not recognize SIG[1..0] as bus.2 C+ G, P2 r0 ^/ b( A+ l
1966120 CONCEPT_HDL COPY_PROJECT Copying release 17.2-2016 project results in message stating the project is of an older version4 I3 u5 [3 W7 w; e
1879425 CONCEPT_HDL CORE Adding signals with the right-click menu is not following the defined color scheme/ o0 Y" o) u; N/ i! O
1890542 CONCEPT_HDL CORE Getting ERROR(SPCOCN-1911) when running export physical with backannotation
8 M5 z9 T5 {9 O) H! [1907684 CONCEPT_HDL CORE Moving symbol makes canvas unresponsive for a long time
7 X# S9 ^8 E" S+ U( ]' i1920711 CONCEPT_HDL CORE Pin names changes when mirroring the swapped section.# c0 t7 R: @# M4 j# Y& j# K L
1931421 CONCEPT_HDL CORE On Linux, 'cpmaccess -read' returns incorrect value0 [ Y! W2 F% U
1931782 CONCEPT_HDL CORE Setting DONT_FORCE_ORIGIN_ONGRID to ON does not work for sig_name
! s9 R6 U( @0 o) x# j) Z S3 q1932433 CONCEPT_HDL CORE _movetogrid causes signal disconnection
& V! ^; n$ k7 p6 z1946993 CONCEPT_HDL CORE DE-HDL Part Manager fails to update parts on schematic if new KEY properties exist in PTF but not in schematic
) U, |# ?3 g% P# i3 h1947029 CONCEPT_HDL CORE Design Entry HDL Font Support not working for signal rename
8 @- q: y& Q! l6 i v7 M1962865 CONCEPT_HDL CORE Schematic symbol creation with '-' as pin name not packaging1 F4 O1 v$ H/ W; ^9 K- k
1966805 CONCEPT_HDL CORE Issues with packaging design containing cells named with a leading underscore
" l7 k- F2 A4 Q% M; U8 e1967760 CONCEPT_HDL CORE DE-HDL crashes on moving Net Group/Port in release 17.2-2016, hotfix 044
2 o: d7 b% L9 R9 S9 x; Q P1968282 CONCEPT_HDL CORE DE-HDL Part Manager fails to update parts on schematic when new KEY properties exist in PTF and not in schematic" l% O# j5 s9 w* h
1972815 CONCEPT_HDL CORE Part Manager not updating missing key attributes from the ptf file by using 'Update instances' option0 A" b L1 }5 M/ k1 v$ b' K& ~9 d8 I8 M
1887790 CONCEPT_HDL CREFER CRefer links not working in selected cpm file
, d1 e: j; w" ^. a' M l1898535 CONCEPT_HDL INTERFACE_DES Global Navigation window does not reflect removal of a net on page2 that is part of a netgroup on page1
% x% W% B- t0 X& v# p& U1888048 CONCEPT_HDL PDF Japanese characters are not output correctly to PDF on Linux.) D9 j2 ^9 d$ f! ~8 h& C& G
1937505 CONCEPT_HDL PDF Missing intersection dot in schematic PDF8 a* a: r6 @+ G/ U6 ^7 A
1942486 CONSTRAINT_MGR CONCEPT_HDL CM crashes when you save after importing a TCF file- m- e7 C5 H+ `
1983743 CONSTRAINT_MGR CONCEPT_HDL Region Class-Class members are being duplicated in CM in the current session/ L; V8 \# Z4 W0 G6 Q) c9 r
1906573 CONSTRAINT_MGR ECS_APPLY Database corrupt and DBDoctor reports illegal database pointer error
' T Y4 \4 m0 Z3 W: k' p8 w1913805 CONSTRAINT_MGR OTHER Setting environmental variable CM_PARTIAL_DCF in release 17.2-2016 causing crash
' V$ N3 E5 o3 {( p/ F+ T p& m1914813 CONSTRAINT_MGR OTHER C++ Runtime error and non-recoverable crash in class-class worksheet
6 j: L4 |- {7 u. g7 @# D0 z1920142 CONSTRAINT_MGR OTHER Xnet names are not consistent in the design
% X8 ^9 f- P; S( l, H. _5 e0 N1898549 CONSTRAINT_MGR SCHEM_FTB Importing netlist causing crash in release 17.2-2016, hotfix 0364 f1 S6 m1 D! [" T7 h. |
1814851 CONSTRAINT_MGR UI_FORMS Field solver /DRC check running forever5 W6 Y" U4 ~# s+ }' _& X
1889862 CONSTRAINT_MGR UI_FORMS PCB Editor hangs while assigning net voltages in CM
4 s/ W4 G K$ C7 u2 s& R1965470 CONSTRAINT_MGR UI_FORMS Constraint Manager GUI Issue in release 17.2-2016, hotfix 039: Font size small and rows/columns in shrink mode, h5 y3 @) T2 {- y$ m5 ~" _) i4 P/ C
1945406 ECW ADMINISTRATIO Tree view was not refreshed soon after changing the site permission.
O) s1 c+ w% G' k! \5 t. R1826848 ECW METRICS SPDWECW-551 and SPDWECW-553 should be warnings, not errors
2 F% G8 b4 ]6 W1933373 ECW PROJECT_MANAG ecwbatch does not accept password and does not ignore invalid users% D% A% o, K8 c+ t- M, e
1921502 F2B PACKAGERXL Errors on running Export Physical:SPCOPK-1138 and SPCOPK-11493 j& n7 v, y" }! \+ E
1929846 F2B PACKAGERXL PackagerXL is still creating the pstcmbc.dat file on a release 16.6 design uprevved to release 17.2-2016 a# d M; [: R0 u, V8 J
1953780 F2B PACKAGERXL Updated subdesign package information not updated on the top-level design in the reuse flow
8 Y' A1 D$ X' h6 Q1971738 F2B PACKAGERXL Deleting blank space from pstxnet.dat file crashing DE-HDL. J+ i, e; f9 E$ e2 A) M/ c0 t
1891002 INSTALLATION DOWNLOAD_MGR Issue with Download Manager (Change Preferences Option does not Work)
! V% ^+ i& Y6 @1972890 ORBITIO OTHER OrbitIO-APR failed to run if PCB design included
2 ^. B8 g. A1 }1954262 PCB_LIBRARIAN CORE Footprint model check in fails with verification checks failed error
& b5 T3 f7 \- k! A- w1943656 PCB_LIBRARIAN GRAPHICAL_EDI Symbol Editor is blank if .ascii file is newer than .css file6 i8 t3 E+ [, ]0 M9 b( h' ^4 u
1897887 PCB_LIBRARIAN SYMBOL_EDITOR New Symbol Editor: Inconsistent symbol results when adding vector pins in Part Developer0 a3 c9 I' ?/ l6 x- q
1898003 PCB_LIBRARIAN SYMBOL_EDITOR Issue with Page Border Symbol4 N" X, I4 W6 a( W" ?
1842007 PSPICE LIBRARIES Change required in swit_reg.lib
/ A( t( ^, z+ S6 _) e$ G1906922 PSPICE LIBRARIES Mismatch in mapping of IC pins in model and PSpice template for analog device AD8138
4 v7 h/ B4 o) c7 ?7 U1 c; i1947586 PSPICE LIBRARIES Update the model AD8138/AD in ANLG_DEV.OLB/ f1 d; E. x: a A$ J/ J& N3 v
1748470 PSPICE MATLAB PSpice displays an error when sending current in co-simulation+ z( h9 M% W5 B, M7 U8 _: a
1802455 PSPICE MATLAB Incorrect current direction for pins in SLPS flow6 R, g: s% x7 Y( V
1852811 PSPICE MATLAB ORPSIM-2604 being reported in SLPS simulation
' o! `; {# B% O( y2 a1858716 PSPICE MATLAB Co-Simulation fails if 'RC' is used as reference of resistor4 [" D6 c7 O: Y- i! F
1921641 PSPICE MODELEDITOR Model Editor in Client Server installation slow to invoke
3 f" c" u, x. E5 r' U+ c1 H8 V1922160 PSPICE MODELING_APPS New Capture Associate Symbol GUI not reading libraries: ^( B9 {( t/ r" G4 t# ^
1843698 PSPICE PROBE PSpice icons appear very small on a specific computer
% j' r9 W+ P/ |0 y C+ z1773841 PSPICE SIMULATOR orSimSetup64 crashes when running the simulation for attached design* a: t' S* T; A) F/ z: D
1816316 PSPICE SIMULATOR Simulation stuck; however, the status bar is correctly updated during Pseudo Transient Analysis
2 D& Y$ Z; D% [/ b6 _ \0 y1887119 SCM IMPORTS Cannot selectively update changes in VDD
+ a7 `1 t4 [: ^1889362 SCM IMPORTS Cannot selectively update changes in Visual Design Differences
, q% O/ M# v' G+ C1958545 SCM SETUP Auto assign models does not work in SCM same way as in DE-HDL
7 \2 K+ v) }8 E' B( F1988841 SIG_EXPLORER INTERACTIV SigXplorer stops responding or crashes in hotfix 047 when a design is saved; u' M2 |6 O7 X) H2 |+ e2 r
1988943 SIG_EXPLORER INTERACTIV SigXplorer crashes on selecting Update Constraint Manager
7 P) r2 J% H0 a5 y5 B" Q1991375 SIG_EXPLORER INTERACTIV SigXplorer crashes when clicking Save
+ I, M0 ^1 C6 ]9 }" Z4 u6 W1993749 SIG_EXPLORER INTERACTIV SigXplorer crashes on saving topology- }# e" H4 c! W
1969975 SIG_INTEGRITY GUI Model Browser edits model above the one that is selected
C( g2 K: ]% t' w1953184 SIP_LAYOUT IMPORT_DATA Sub Drawing not saving dashed lines" h* h3 j" T) w1 ?' A
1913864 SIP_LAYOUT ORBITIO_IF SiP Layout design import results in wrong die rotation
/ A2 q5 Z, g/ I7 P3 }' M1880237 SIP_LAYOUT PADSTACK_EDIT Background Window comes to the forefront when closing the Padstack editor" a( j1 Y/ I: Y' h$ t0 @9 v
1972560 SIP_LAYOUT STREAM_IF GDS Export fidelity issue: inverted arcs
( U0 o+ c4 m0 w1920317 SIP_LAYOUT THIEVING Thieving pattern does not allow for OOPS operation
: x4 O @' x9 n. B. M }% A1909075 SYSTEMSI DOC SystemSI PBA channel and circuit simulations do not respond if bit pattern is 1s or 0s7 Z- {: f6 Q" X: p
1916101 SYSTEMSI DOC Lack of stimulus in file causes Serial Link Analysis to become unresponsive
- [% [; U% |# s6 F1919562 SYSTEMSI ENG_PBA SystemSI generates wrong timing bathtub curves in channel simulations for write and read
. C% G a% z- k9 t0 I, m6 o1964064 SYSTEMSI GUI_PBA Able to sweep AMI parameters in SSI-PBA
2 K5 ^9 {- k2 U6 J( V1971266 SYSTEMSI GUI_PBA MCP header shows only 49 ckt nodes instead of 52 for s52p S-parameter file
; P) q" I: {( Y& k' U2 U; S1885625 SYSTEMSI GUI_SLA Manage AMI + DLL from Setup Analysis Window0 Z5 A# e) |( i; K( _$ H. E
1924382 SYSTEMSI GUI_SLA Data Rate field in SystemSI Stimulus property form is confusing for PAM4 operation
& ]5 C* y! x# b4 x% ^- j6 R1982341 SYSTEM_CAPTURE CANVAS_EDIT Signal rename does not maintain new signal name value
& n7 P" O% a8 d7 b# X8 M/ V1976857 SYSTEM_CAPTURE CONSTRAINT_MA System Capture-CM Match Group Creation is not updating correctly
1 F9 b- n" h* v# _. \% d1929606 SYSTEM_CAPTURE DESIGN_CORRUP Opening design causes System Capture to crash, p! R. ^0 m8 m H
1914697 SYSTEM_CAPTURE DRC Overlapping component DRC does not work: e8 f# q% D; x0 F" s: }( g/ Z6 ~
1973467 SYSTEM_CAPTURE IMPORT_PCB System Capture Import Physical shows many component and physical differences on a design that is synced up
5 A6 e/ r4 B# c$ _; J6 K2 T/ D1962603 SYSTEM_CAPTURE NAVLINKS Ability to not underline hyperlinks for Navigation Link values: q# `* b8 r7 R/ M# W* f
1967639 SYSTEM_CAPTURE PART_MANAGER Part Manager does not open in System Capture for part property value changes even after setting the cpm directive. d9 F6 G* T8 `& H$ }
1964388 SYSTEM_CAPTURE SMART_PDF Some shapes are not visible in the smart PDF schematics, j% _" x" I9 \6 |, W
1976832 SYSTEM_CAPTURE TDO Rolling Back local lower-block requires check-out of higher-level packaged & variant views
: |$ V0 L! @( Z1976844 SYSTEM_CAPTURE TDO CM - TDO check-out dependencies are broken) x3 P8 h8 y: }$ g/ c) Q
1976859 SYSTEM_CAPTURE TDO Variant Editor in System Capture -TDO allows to delete a variant without checking out variants view3 t- N' C6 a+ S) X7 \" \
1839816 TDA CORE All the design objects are locked in the EDM dashboard after a DSFrame error/ w; M+ _7 p# d E9 H' \7 P
1889898 TDA CORE Cannot check in the top level of the project in TDO# G* x) }* x; m9 L6 }
1892411 TDA CORE Unable to undo the block checkout if something fails
3 ?+ O( ~8 N/ O4 ^/ U1877757 TDA DEHDL Refresh Hierarchy does not show latest TDO lock/unlock status in DE-HDL: m6 K3 [* x( g
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