关于在capture cis 生成网表后导入PADS LAYOUT 的报错。请不吝赐教。

wanghf

我在生成网表后，导入pads layout， 结果报告如下错误：
Can't find part Type item < XTAL_HC49SMT >
) D' P$ z0 ]* v8 nY1               XTAL_HC49SMT
Can't find part Type item < XTAL_HC49SMT >
Y2               XTAL_HC49SMT
" s4 p7 w; @9 a+ rCan't find part Type item < XTAL_HC49SMT >
) C7 P# G$ ~( q! d) F4 `Y3               XTAL_HC49SMT
# p6 X0 o; d% n1 w( Q+ A; F*Part name not found U13
6 b6 I/ n$ q6 B% {# n' e+ x0 XU13.1 R9.1 C45.2 R13.2 R14.1
1 B; G+ I/ W9 Z% j. t" |*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal N1356420
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal XT2_PHY
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal USB_D+2
' c/ }% \: b5 d( @7 [* B8 M) X*Part name not found Y1
Y1.2 U6.1 C28.1 J3.1 J4.1 J5.1
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal OSC1
9 F$ x' n7 i+ J0 _*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal CRS_PHY
% _& ]1 D+ W- I# R*Part name not found Y2
U5.34 Y2.2 C41.2
*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal RTCK1
' M2 w  L  L, B; V, |3 {# i# h*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal VDD_PHY
; w* P1 l2 ]2 x6 H2 e*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal TXD1_PHY
; k% r; U+ ~: A, i*Bad *CONNECTION* ascii data format, nets must contain more than one pin. Signal USB_OTG_ID
/ h& r. A3 }3 D  |  w+ z! A8 }除了上述报错元件不能导入，可以导入其它元件。我的部分PCB封装在自己建的pads库里，还用了些常用的自带库。请问
这些错是什么原因造成的？我看了一天了也没头绪。
, i- {+ D; n, `% S多谢各位看完。
我会把整个设计放在附件里。
再谢。

风淡云悠

这种问题发了N种贴了，你找下以前有人发过。。有解决方法：是你的晶振封装名和ORCAD里不对

wanghf

非要和ORCAD一样吗？我用pads画PCB.

wanghf

我已经把封装改好了。