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装完还是显示052 " ]& i% Y* {& R$ L( r! a5 n" g
Fixed CCRs: SPB 17.2 HF053* S% a: Y5 \8 s, [1 B. y( ~4 C
03-01-2019$ ] p" \+ M0 Y! S; h; `
========================================================================================================================================================
5 B1 F. w; i' o2 nCCRID Product ProductLevel2 Title
& i+ d0 ~5 C! p8 N- l6 B$ C========================================================================================================================================================
& T, Z* ~. `3 `2 q& {2 |9 L* I2035766 ADW DSN_MIGRATION EDM release 17.2-2016: design migration UI is cut off on right6 V- Y5 `/ O9 p) {
2044872 ADW PART_BROWSER Component Browser: Only one PTF file read for multiple PTF files under Part Table all referenced in master.tag) r8 ^* `; ?! E2 J: V0 u
2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name
. x& }( D3 f! O2 |8 C+ T2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design
& \* ^ D. r" ]3 D0 C' g6 _2052046 ADW TDO-SHAREPOIN Joining projects is downloading 0-byte files due to SSL error, _# z( ? ~' b
2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object4 i5 ^0 `) A) g' E
2047512 ALLEGRO_EDITOR 3D_CANVAS Mechanical components do not move when bending in 3D Viewer
3 d: l, V* G! l6 f0 z8 r2 _2048086 ALLEGRO_EDITOR 3D_CANVAS Wirebonds are not linked to diepad when component is embedded body down; D6 \ C% t F/ S8 l8 l) _
2051277 ALLEGRO_EDITOR 3D_CANVAS 3D View Vias are Offset from Board in Z direction
' R5 x8 ~# ?$ O7 t2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation
8 z1 a) F5 A4 v) r9 l2056547 ALLEGRO_EDITOR 3D_CANVAS 3D model not shown for component with STEP file assigned
" W3 P# e, i! \" y( z2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded
$ G9 \# L* A% r; y2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone
0 o9 {4 A, w. p1826533 ALLEGRO_EDITOR DATABASE Dyn_Thermal_Con_Type not behaving as defined in Symbol Editor after placing on PCB file.
$ U1 ^2 z& ^9 j( d1 e1857282 ALLEGRO_EDITOR DATABASE PCB Editor slow when Manhattan and Path length tooltip enabled in datatip customization) {8 S1 v3 W) B/ M
2052767 ALLEGRO_EDITOR DATABASE Allegro PCB Editor crashes on editing padstack
' H% ]% Y. J4 G1825692 ALLEGRO_EDITOR DRAFTING Dimension line text moved by Update Symbols& x: \6 r0 T# f) M* M" @
1874814 ALLEGRO_EDITOR DRAFTING 'Connect Lines' does not merge overlapping lines7 Y: P$ M, j3 q
1874935 ALLEGRO_EDITOR DRAFTING Angular dimension text has extra spaces added before the degree symbol.
" L g, f) e$ j1882597 ALLEGRO_EDITOR DRAFTING 'Trim Segment' should allow trimming for all intersecting segment types- z1 ?( a" E+ @5 a/ ?# I
2052315 ALLEGRO_EDITOR DRC_CONSTR DRC (pad-shape) incorrect when both pad and drill are offset from pad origin.# w: M0 f- V/ l$ ~: h
2040603 ALLEGRO_EDITOR EDIT_SHAPE Shape is not updating correctly after the 'move' command
* W& n6 ~' P+ K% ^' l2050177 ALLEGRO_EDITOR INTERACTIV Letters need to remain aligned and uniform after performing Boolean ANDNOT operation
* m/ E5 D5 K, `: w+ R6 N9 x9 W2052586 ALLEGRO_EDITOR IPC IPC356 showing shorts and disconnects for chip-on-board design
5 e- ?; j5 `5 D# m& e" Y' V2044350 ALLEGRO_EDITOR MANUFACT Cross Section table showing multiple decimal digits for the Tolerance column- }( k' l' l8 l
2051150 ALLEGRO_EDITOR NC Counterbore/Countersink holes not being shown in the NC legend table.
" n" @! w$ R6 a. \1 g7 j2058199 ALLEGRO_EDITOR NC 'Manufacture - NC - Drill Legend' does not populate the CounterBore/CounterSink row values in the Drill Chart table
5 T( y1 B& y- D4 H( u7 m. p2 L2061809 ALLEGRO_EDITOR NC Counter bore NC Legend does not show any data/ V0 n. e- Z0 G6 b9 s
2063477 ALLEGRO_EDITOR NC Counter bore NC Legend does not show its value
; @9 C3 _. @% ` ^* }+ s2033849 ALLEGRO_EDITOR PLACEMENT PCB Editor stops responding when removing a plane that the Place Replicate command added
! A2 I; _2 ^' v) x0 ~( ]& h, v. F2037509 ALLEGRO_EDITOR PLACEMENT Move or Rotate or Mirror of a module/group makes PCB Editor to crash with no .SAV file created
: [! b& n8 l$ m9 `: L( X2047480 ALLEGRO_EDITOR SCHEM_FTB Importing netlist using Capture-CM flow in PCB Editor is crashing netrev' ^3 h$ I$ Y1 t- S( \1 ^
2046276 ALLEGRO_EDITOR SHAPE Add notch is not snapping to the grid point
( k) `; V9 e( o4 @8 y' ]2047572 ALLEGRO_EDITOR SHAPE Voiding elements on static shape do not void adjacent layer keep-outs and PCB Editor stops responding
1 T5 z: S- `1 p* A% C2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update) C: O* s6 r( m$ Q; X
2050120 ALLEGRO_EDITOR SHAPE Dynamic fill is flooding over other etch shapes within a symbol.
, _8 q/ ~7 y1 e$ J e. E2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present
2 H3 z+ u0 b4 o5 K2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in hotfix 048.
0 {. `0 x: t Z1 b2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash- j# I$ T3 R- b
1961689 ALLEGRO_EDITOR SYMBOL Pin Numbers are moved from center with Pin Rotation when adding pins to Footprint
3 b8 i9 l7 ?" Z+ j* z" F6 f2034949 ALLEGRO_EDITOR SYMBOL Angular dimension from DRA not created in PCB
' R m0 S2 ~& e) _2046242 ALLEGRO_EDITOR UI_GENERAL Searching User Preference Summary results in crash
9 i4 ^( l; |( k2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog box is behind canvas! }4 y+ K: |2 t; Y, H! W ?/ @" j- l
2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden
6 z) ~5 q! g& X* [1886781 ALLEGRO_VIEWER OTHER Opening Color192 in Allegro Free Viewer causes it to crash
8 b: ?7 Z) I# K4 _3 g4 l1699433 APD EDIT_ETCH Field solver runs when not expected& n+ u5 Z3 K& z* J% h7 o( B# e
1937159 APD EDIT_ETCH Routing clines takes long time! w' o9 A0 \4 M# J$ f& ]7 ^
2050863 APD SHAPE Taper voiding process is different in Within the region/Out of Region5 w* e5 t& |4 x- u% l: W
2047391 CAPTURE PART_EDITOR Pin type cannot be changed in hotfix 051" ?8 p. ^" @3 g5 R. P
2049161 CAP_EDIF IMPORT Fatal error 'cannot determine grid' when converting third-party design to Capture/ J- D& g4 s2 n `" e- a0 _" E
2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved
/ D. [# V, z3 }7 r# h7 i2047583 CONCEPT_HDL COPY_PROJECT Design Entry HDL crashing when trying to open page 52 of copied project" P& d! p$ j; j' G
2036239 CONCEPT_HDL CORE When cutting/pasting, multiple error pop-ups appear for the same notification! _ y, I' Q( \! V; A0 N: F& M
2037572 CONCEPT_HDL CORE Warning (SPCOCD-578): Soft VOLTAGE property found is misleading and should be auto resolved when closing CM9 C: f& M, H$ [
2037578 CONCEPT_HDL CORE VOLTAGE property gets deleted after copying it from a non-synchronized source
8 q V5 e- R6 ]) O3 \& p% Q2046958 CONCEPT_HDL CORE Moving block pins from symbol right to left places pin names outside the symbol* G& i, T+ M, Z' g, `' s
2032480 CONSTRAINT_MGR CONCEPT_HDL Incorrect matchgroups created when working with multiple level nested hierarchical blocks5 A+ W( g. f9 D8 S+ V, p% q5 i
2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor
2 u$ B7 K3 h2 s0 @# F( R3 n* g2046765 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout 'dump libraries' crashes when exporting library0 c' D+ y/ M0 g9 Z0 s, N
2067970 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout cannot dump libraries, viewlog is empty
; v# D* ~5 d* X1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error/ I* S: l, n4 s2 [, r
1968437 SYSTEM_CAPTURE ASSIGN_SIGNAL Net name pasted in lower-case though UPPERCASE INPUT is enabled- r& \0 Q; M& n/ R
1983063 SYSTEM_CAPTURE AUTOSHAPES Auto Shapes are being shown as part of components& r' {$ @& f' Y) o) J
1968463 SYSTEM_CAPTURE CANVAS_EDIT System Capture should not allow illegal characters to be entered for net names
* j7 k0 X" ?2 v7 B* a2 x2006593 SYSTEM_CAPTURE CANVAS_EDIT Asterisk in a search string is not treated as a wildcard character2 }& ~( M' k7 j" I$ S
1721863 SYSTEM_CAPTURE CONNECTIVITY_ Net Names move to random locations when the components are moved around the canvas
9 Z4 R; |% E0 [& [9 R1960130 SYSTEM_CAPTURE CONNECTIVITY_ Disconnected nets when using the mirror option" Z* X0 z; x- Z6 y v4 P; {& t
1985029 SYSTEM_CAPTURE EDIT_OPERATIO Net aliases do not drag with circuit, they appear to move after the circuit is dropped
: ~2 }8 D0 K. ^; i9 T; F( C1895142 SYSTEM_CAPTURE EXPORT_PCB System Capture reports incorrect unsaved changes when closed after running export physical* ~; s8 {. Z! }9 U. \
1628596 SYSTEM_CAPTURE FIND_REPLACE Alias issue in Find: Results do not show the resolved physical net names5 a ^6 u+ f; I2 R; s
1988297 SYSTEM_CAPTURE FIND_REPLACE Edit > Find and Replace does not replace a net with an existing net on the canvas
1 }( h/ Y0 E( ~+ I) W) f( E n1843885 SYSTEM_CAPTURE FORMAT_OBJECT Renaming a net causes it to lose custom color assignment" s) w5 @& s [ B0 y& Y) Z
1969308 SYSTEM_CAPTURE FORMAT_OBJECT System Capture: Clicking arrows to increase/decrease font size does not work correctly when clicked fast
5 X, \1 m: |( u: }( `% M1990060 SYSTEM_CAPTURE FORMAT_OBJECT Bold, italics, and underline formats not visually shown on all selected objects concurrently6 Y$ U2 Z7 s' Y' b7 [' d
1993208 SYSTEM_CAPTURE FORMAT_OBJECT Setting font prior to placing text does not work, pop-up does not work, and bucket results in scrolling page8 T( v; V' u# X; b6 A1 S- _
1981775 SYSTEM_CAPTURE IMPORT_PCB Import Physical takes a long time on some designs to launch the UI0 ] g* m! K; K0 [# H$ w; f' }
1982320 SYSTEM_CAPTURE IMPORT_PCB In the B2F flow none of the *view files are created+ j# }( R' Y5 W* t8 N6 ?" i2 H9 r
2010996 SYSTEM_CAPTURE INSERT_PICTUR Image in title block is at a wrong location in design: correctly placed in library
* \3 O4 D& K) l% p$ V% u( ^& S) {1967614 SYSTEM_CAPTURE MISCELLANEOUS Dragging a circuit with net aliases does not move the net aliases with it
* |6 T: ^2 \3 B% _* B1980999 SYSTEM_CAPTURE NEW_PROJECT System Capture stops working with message regarding Part Manager initialization for a design based on DE-HDL
0 v+ d! k4 L1 T8 z) [( r, \1973437 SYSTEM_CAPTURE OPEN_CLOSE_PR Opening a design crashes System Capture) A i9 ^& \1 q$ @( ~7 u( V
1986566 SYSTEM_CAPTURE OPEN_CLOSE_PR System Captures stops responding on opening project, cleaning project displays project already open message
/ ]! H/ u0 u3 N" Y+ y1993093 SYSTEM_CAPTURE OPEN_CLOSE_PR Add option to override the lock file similar to Allegro PCB Editor5 C7 N" b6 x, B" O" W
2042360 SYSTEM_CAPTURE OPEN_CLOSE_PR System Capture will not open nor gives error message when previous lock file present inside the logic folder
1 a9 n0 \4 H, J; {* j$ M9 Y1992247 SYSTEM_CAPTURE PART_MANAGER Part Manager displays message for undo and redo stack even after specifying not to show message
3 d0 B- I" {1 A' {2048000 SYSTEM_CAPTURE PERFORMANCE Performance issue when instantiating and moving a component% P4 S8 {1 h2 o/ {. U( a* J: n* ]
1892120 SYSTEM_CAPTURE PROPERTY_EDIT Some parts missing reference designators and some have two properties, RefDes and REFDES
! p( I6 G8 ]. k6 h7 t2 O/ E1970009 SYSTEM_CAPTURE PROPERTY_EDIT System Capture: Right-clicking RefDes with conflict in 'Edit Properties' shows the Hyperlink option1 k7 k7 [3 _0 {/ B+ h! t# H
2042707 SYSTEM_CAPTURE VARIANT_MANAG variant.lst file under 'physical' folder not updated when closing Variant Editor
7 G5 F+ j3 J1 s2 r: X* ^. u0 O5 {* T
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发表于 2019-4-6 21:51
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