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装完还是显示052
+ Z9 w% J* o3 y" k7 wFixed CCRs: SPB 17.2 HF053( K' d/ m, \4 c& b
03-01-20192 W0 ~$ t( Q* j: y" ~ C/ N8 v
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CCRID Product ProductLevel2 Title5 T, i8 r3 D: t1 X7 O
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! W3 C# y, ^* F. k d9 [. m) p2035766 ADW DSN_MIGRATION EDM release 17.2-2016: design migration UI is cut off on right# B6 c" z' D/ _; U* p% r7 A
2044872 ADW PART_BROWSER Component Browser: Only one PTF file read for multiple PTF files under Part Table all referenced in master.tag
9 B8 P1 N D& L! \2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name
5 h9 i T. I `& y1 J2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design2 }' I& T0 F! {0 I5 l
2052046 ADW TDO-SHAREPOIN Joining projects is downloading 0-byte files due to SSL error9 J; N4 q2 m+ X! F9 X, c& `4 E) z
2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object
$ r. m8 l5 R# d/ S2047512 ALLEGRO_EDITOR 3D_CANVAS Mechanical components do not move when bending in 3D Viewer) |" G6 ^7 I" F! Z; k6 {
2048086 ALLEGRO_EDITOR 3D_CANVAS Wirebonds are not linked to diepad when component is embedded body down, Y, q4 }" h% d6 s& R
2051277 ALLEGRO_EDITOR 3D_CANVAS 3D View Vias are Offset from Board in Z direction
f( l! Y5 Q; z* ~2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation% O. I$ i, J& K" X5 E! B$ d
2056547 ALLEGRO_EDITOR 3D_CANVAS 3D model not shown for component with STEP file assigned
) Y7 J5 w# e+ H8 n8 t9 ?2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded: q; t: h R+ X+ E
2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone& Q( n8 F( K/ o2 o* X" w2 `7 B
1826533 ALLEGRO_EDITOR DATABASE Dyn_Thermal_Con_Type not behaving as defined in Symbol Editor after placing on PCB file. G5 o8 P! ]5 O8 b4 g2 i
1857282 ALLEGRO_EDITOR DATABASE PCB Editor slow when Manhattan and Path length tooltip enabled in datatip customization
* U- _) p) v0 L( H6 [6 N0 W; J2052767 ALLEGRO_EDITOR DATABASE Allegro PCB Editor crashes on editing padstack
% @7 e) e0 \* c% ^. ?, C& U1825692 ALLEGRO_EDITOR DRAFTING Dimension line text moved by Update Symbols
+ p2 r3 l) F# w5 c1874814 ALLEGRO_EDITOR DRAFTING 'Connect Lines' does not merge overlapping lines
0 T/ Q Q7 H$ S# T' Z) J1 M1874935 ALLEGRO_EDITOR DRAFTING Angular dimension text has extra spaces added before the degree symbol.
" X% M `" X/ h H4 V1882597 ALLEGRO_EDITOR DRAFTING 'Trim Segment' should allow trimming for all intersecting segment types
; I% K7 ?. H4 F+ B! k2052315 ALLEGRO_EDITOR DRC_CONSTR DRC (pad-shape) incorrect when both pad and drill are offset from pad origin./ M5 m- ]7 r5 b, T/ `) F
2040603 ALLEGRO_EDITOR EDIT_SHAPE Shape is not updating correctly after the 'move' command
|' H& Z* P3 F% E. D! f/ A2050177 ALLEGRO_EDITOR INTERACTIV Letters need to remain aligned and uniform after performing Boolean ANDNOT operation5 z; c3 Z) g- h& d7 K( E6 u @
2052586 ALLEGRO_EDITOR IPC IPC356 showing shorts and disconnects for chip-on-board design
0 z* W* o. }. w; S* ~2044350 ALLEGRO_EDITOR MANUFACT Cross Section table showing multiple decimal digits for the Tolerance column8 G7 d+ f8 r; |9 z" H
2051150 ALLEGRO_EDITOR NC Counterbore/Countersink holes not being shown in the NC legend table. [, v; [: l* n, f) Z7 C7 ]' E2 L1 B
2058199 ALLEGRO_EDITOR NC 'Manufacture - NC - Drill Legend' does not populate the CounterBore/CounterSink row values in the Drill Chart table
& m$ i* `, F( n. z2061809 ALLEGRO_EDITOR NC Counter bore NC Legend does not show any data
5 W( \. X9 [& Y( y& l& S2063477 ALLEGRO_EDITOR NC Counter bore NC Legend does not show its value6 U' B; _" Q( _! r; t5 Y# \
2033849 ALLEGRO_EDITOR PLACEMENT PCB Editor stops responding when removing a plane that the Place Replicate command added
4 G$ m( q" ?! c! s+ |; a* o) F/ F$ H2037509 ALLEGRO_EDITOR PLACEMENT Move or Rotate or Mirror of a module/group makes PCB Editor to crash with no .SAV file created
. T2 q/ u9 J: U$ i2047480 ALLEGRO_EDITOR SCHEM_FTB Importing netlist using Capture-CM flow in PCB Editor is crashing netrev
, N/ a) _8 L' X, ?# G2046276 ALLEGRO_EDITOR SHAPE Add notch is not snapping to the grid point
8 f# z2 d' H$ Q8 N- X9 ^2047572 ALLEGRO_EDITOR SHAPE Voiding elements on static shape do not void adjacent layer keep-outs and PCB Editor stops responding2 B8 y% u: T0 ~: a- w
2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update8 T6 c/ u0 d y& l2 R: ~: }
2050120 ALLEGRO_EDITOR SHAPE Dynamic fill is flooding over other etch shapes within a symbol.$ t1 C7 w4 Y! P5 r" |- ~, g
2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present2 g' t9 e! E7 [
2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in hotfix 048.
! M0 G) P/ d/ F$ M, a2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash& w7 Q4 ?. q6 d$ h) l3 p- q
1961689 ALLEGRO_EDITOR SYMBOL Pin Numbers are moved from center with Pin Rotation when adding pins to Footprint
8 V% u) s6 L0 x- R+ w0 y. P* ^( i2034949 ALLEGRO_EDITOR SYMBOL Angular dimension from DRA not created in PCB
" S6 n U* K% V$ f# h/ X3 ?2046242 ALLEGRO_EDITOR UI_GENERAL Searching User Preference Summary results in crash* n. J* a- Q n
2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog box is behind canvas5 a5 D* g0 B$ @% e
2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden
9 _. E( g1 H' N* k# M* l8 K1 N" H1886781 ALLEGRO_VIEWER OTHER Opening Color192 in Allegro Free Viewer causes it to crash& y3 y3 j( f" U
1699433 APD EDIT_ETCH Field solver runs when not expected- B1 m, t, r' |0 R, s' l) y" W
1937159 APD EDIT_ETCH Routing clines takes long time
. P; w* N+ w' R% Z4 Z! v2050863 APD SHAPE Taper voiding process is different in Within the region/Out of Region
- l8 X* r _/ W& ~2047391 CAPTURE PART_EDITOR Pin type cannot be changed in hotfix 051
8 |+ J8 w3 L3 L" t# b! ~2049161 CAP_EDIF IMPORT Fatal error 'cannot determine grid' when converting third-party design to Capture" s8 g* I" d+ u8 G2 c7 f
2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved, F( O4 K$ P9 Z6 M( N5 B
2047583 CONCEPT_HDL COPY_PROJECT Design Entry HDL crashing when trying to open page 52 of copied project0 z+ H+ ~+ z2 b* c) p, h' o) T
2036239 CONCEPT_HDL CORE When cutting/pasting, multiple error pop-ups appear for the same notification
, W e8 E3 N3 n- Z5 ?6 U$ {+ R2037572 CONCEPT_HDL CORE Warning (SPCOCD-578): Soft VOLTAGE property found is misleading and should be auto resolved when closing CM
; c2 w- Y5 H# j# B4 y2037578 CONCEPT_HDL CORE VOLTAGE property gets deleted after copying it from a non-synchronized source
! h5 [* u! Y" _$ `8 F0 y. H, {# K+ O2046958 CONCEPT_HDL CORE Moving block pins from symbol right to left places pin names outside the symbol2 ^+ _1 Y3 J7 f s) d7 f0 N
2032480 CONSTRAINT_MGR CONCEPT_HDL Incorrect matchgroups created when working with multiple level nested hierarchical blocks
+ A/ w7 \0 O+ C( Z3 a8 w2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor; H2 ~. M; W. R- _4 t+ Q3 y
2046765 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout 'dump libraries' crashes when exporting library1 \3 I7 i, I! v O: ?+ q( C
2067970 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout cannot dump libraries, viewlog is empty
5 Z( q7 I" L0 n5 R3 v8 e: b1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error8 |6 o3 k% h4 Q: d$ K) H) ]
1968437 SYSTEM_CAPTURE ASSIGN_SIGNAL Net name pasted in lower-case though UPPERCASE INPUT is enabled
* z0 N0 t+ a. h `: |1983063 SYSTEM_CAPTURE AUTOSHAPES Auto Shapes are being shown as part of components C d' W8 U3 [0 {1 K
1968463 SYSTEM_CAPTURE CANVAS_EDIT System Capture should not allow illegal characters to be entered for net names" r& M* H) Q+ A8 L) a
2006593 SYSTEM_CAPTURE CANVAS_EDIT Asterisk in a search string is not treated as a wildcard character
. `3 C# W: ^9 J1721863 SYSTEM_CAPTURE CONNECTIVITY_ Net Names move to random locations when the components are moved around the canvas1 @" T: s7 P1 p& f- Z- ]4 v
1960130 SYSTEM_CAPTURE CONNECTIVITY_ Disconnected nets when using the mirror option
3 d e5 T, L6 U& V( ?1985029 SYSTEM_CAPTURE EDIT_OPERATIO Net aliases do not drag with circuit, they appear to move after the circuit is dropped; |" W7 l3 @! a. a/ m! @" v+ F# I
1895142 SYSTEM_CAPTURE EXPORT_PCB System Capture reports incorrect unsaved changes when closed after running export physical& o4 K2 B) Y1 q3 u0 b! @: f7 b
1628596 SYSTEM_CAPTURE FIND_REPLACE Alias issue in Find: Results do not show the resolved physical net names
: l- o/ d$ e: }3 \2 ?1988297 SYSTEM_CAPTURE FIND_REPLACE Edit > Find and Replace does not replace a net with an existing net on the canvas0 f1 `. E* M$ V$ ?8 q
1843885 SYSTEM_CAPTURE FORMAT_OBJECT Renaming a net causes it to lose custom color assignment
9 J% k/ P+ g# e) \1969308 SYSTEM_CAPTURE FORMAT_OBJECT System Capture: Clicking arrows to increase/decrease font size does not work correctly when clicked fast
/ O% l1 O8 K/ \. T, A- G& F1990060 SYSTEM_CAPTURE FORMAT_OBJECT Bold, italics, and underline formats not visually shown on all selected objects concurrently4 o* A/ n: L) `' H( A
1993208 SYSTEM_CAPTURE FORMAT_OBJECT Setting font prior to placing text does not work, pop-up does not work, and bucket results in scrolling page
: V2 v4 _: G5 \. [0 \% Q" }# [1981775 SYSTEM_CAPTURE IMPORT_PCB Import Physical takes a long time on some designs to launch the UI
$ D4 E& a) T3 N- s7 h$ t5 B! z: Y1982320 SYSTEM_CAPTURE IMPORT_PCB In the B2F flow none of the *view files are created' C7 {! H( W2 {( o( s3 N. r. @
2010996 SYSTEM_CAPTURE INSERT_PICTUR Image in title block is at a wrong location in design: correctly placed in library4 r) D! G! g$ \9 d: z
1967614 SYSTEM_CAPTURE MISCELLANEOUS Dragging a circuit with net aliases does not move the net aliases with it% n3 a* i* k2 l; F% f
1980999 SYSTEM_CAPTURE NEW_PROJECT System Capture stops working with message regarding Part Manager initialization for a design based on DE-HDL5 Y& \: d# G% `" o) G' O$ j
1973437 SYSTEM_CAPTURE OPEN_CLOSE_PR Opening a design crashes System Capture
3 Z0 m e- S$ s8 [; k1986566 SYSTEM_CAPTURE OPEN_CLOSE_PR System Captures stops responding on opening project, cleaning project displays project already open message7 x0 i* D- _* r E0 X5 U6 j+ p
1993093 SYSTEM_CAPTURE OPEN_CLOSE_PR Add option to override the lock file similar to Allegro PCB Editor
4 q4 {( s/ Q* z! d0 R2042360 SYSTEM_CAPTURE OPEN_CLOSE_PR System Capture will not open nor gives error message when previous lock file present inside the logic folder! o) Q$ d" m& z9 b* o
1992247 SYSTEM_CAPTURE PART_MANAGER Part Manager displays message for undo and redo stack even after specifying not to show message4 f9 _3 v, |4 b2 _# h3 X4 f n2 M
2048000 SYSTEM_CAPTURE PERFORMANCE Performance issue when instantiating and moving a component
6 O* j7 g. Q8 ?% O, I1892120 SYSTEM_CAPTURE PROPERTY_EDIT Some parts missing reference designators and some have two properties, RefDes and REFDES
$ l e1 U- B5 p1970009 SYSTEM_CAPTURE PROPERTY_EDIT System Capture: Right-clicking RefDes with conflict in 'Edit Properties' shows the Hyperlink option& j* F6 |. V; M4 k
2042707 SYSTEM_CAPTURE VARIANT_MANAG variant.lst file under 'physical' folder not updated when closing Variant Editor7 c: M2 E9 n* ]* m) X* I
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发表于 2019-4-8 19:46
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