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装完还是显示052
2 A& M) m5 y* uFixed CCRs: SPB 17.2 HF053
" Y! ?' b) K! S: X% _! `* U03-01-2019
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CCRID Product ProductLevel2 Title
8 L5 P& ]5 \) v========================================================================================================================================================+ _' v$ u, e" D( V6 t$ V/ s
2035766 ADW DSN_MIGRATION EDM release 17.2-2016: design migration UI is cut off on right
! g2 V- ^! _% V$ n( _1 W2044872 ADW PART_BROWSER Component Browser: Only one PTF file read for multiple PTF files under Part Table all referenced in master.tag
% g. L' m8 E# F2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name
F+ L: L$ Z) `; b; b2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design
' {, p* ?1 E- Z, j. e8 y4 |2052046 ADW TDO-SHAREPOIN Joining projects is downloading 0-byte files due to SSL error; g; b! B* I- X$ `0 V( }
2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object) i+ A( H& V8 B6 l+ K3 G
2047512 ALLEGRO_EDITOR 3D_CANVAS Mechanical components do not move when bending in 3D Viewer
, i% j" J$ p! k0 B$ o- M( M2048086 ALLEGRO_EDITOR 3D_CANVAS Wirebonds are not linked to diepad when component is embedded body down
( d) g" i5 k. \. x3 q2051277 ALLEGRO_EDITOR 3D_CANVAS 3D View Vias are Offset from Board in Z direction! N% d* f2 f6 ]3 z' o, {# p
2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation5 Z/ G% x0 {) C- _4 ^0 K
2056547 ALLEGRO_EDITOR 3D_CANVAS 3D model not shown for component with STEP file assigned4 r1 D& u; p" s, y7 d
2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded
. |* ?$ `' `7 d: m9 X2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone7 W3 t' R& S2 ?( L8 b( m
1826533 ALLEGRO_EDITOR DATABASE Dyn_Thermal_Con_Type not behaving as defined in Symbol Editor after placing on PCB file.
8 {; X- W: k2 q/ t: z+ _" I1857282 ALLEGRO_EDITOR DATABASE PCB Editor slow when Manhattan and Path length tooltip enabled in datatip customization7 U8 s0 U; o0 A* b
2052767 ALLEGRO_EDITOR DATABASE Allegro PCB Editor crashes on editing padstack
) c% k2 c0 [' M2 l t+ {* O1825692 ALLEGRO_EDITOR DRAFTING Dimension line text moved by Update Symbols) ?2 c4 {7 } j: }0 d4 ~+ _& T
1874814 ALLEGRO_EDITOR DRAFTING 'Connect Lines' does not merge overlapping lines
' j) k( _& ~3 J9 ~1874935 ALLEGRO_EDITOR DRAFTING Angular dimension text has extra spaces added before the degree symbol.
" P+ i6 P8 `/ Y7 A7 i1882597 ALLEGRO_EDITOR DRAFTING 'Trim Segment' should allow trimming for all intersecting segment types- J! E# t1 Z2 Z1 A$ L i1 q
2052315 ALLEGRO_EDITOR DRC_CONSTR DRC (pad-shape) incorrect when both pad and drill are offset from pad origin.! ~7 P' a' x0 z, q2 G. q
2040603 ALLEGRO_EDITOR EDIT_SHAPE Shape is not updating correctly after the 'move' command
. J" A( M- K; Y& `3 i) O* n0 L% u2050177 ALLEGRO_EDITOR INTERACTIV Letters need to remain aligned and uniform after performing Boolean ANDNOT operation
2 `/ D& l: w- \; o" M: \4 _7 c4 h2052586 ALLEGRO_EDITOR IPC IPC356 showing shorts and disconnects for chip-on-board design
- B, f3 Z5 Z: |9 G2044350 ALLEGRO_EDITOR MANUFACT Cross Section table showing multiple decimal digits for the Tolerance column
+ H! u" x6 s* u5 u" p2051150 ALLEGRO_EDITOR NC Counterbore/Countersink holes not being shown in the NC legend table.
8 d! p8 {* |6 H* b2058199 ALLEGRO_EDITOR NC 'Manufacture - NC - Drill Legend' does not populate the CounterBore/CounterSink row values in the Drill Chart table
$ A* g! ^+ W( S# m% T# W7 A: N2061809 ALLEGRO_EDITOR NC Counter bore NC Legend does not show any data
/ S @5 P- C: O) m# t: d+ Q% [6 G& w4 O2063477 ALLEGRO_EDITOR NC Counter bore NC Legend does not show its value
2 C @ M! M( u$ ~! q% f2033849 ALLEGRO_EDITOR PLACEMENT PCB Editor stops responding when removing a plane that the Place Replicate command added
5 \5 U+ n* R4 z. P5 w2 ?2037509 ALLEGRO_EDITOR PLACEMENT Move or Rotate or Mirror of a module/group makes PCB Editor to crash with no .SAV file created) z6 ^) w) p. F' u4 d! `! A
2047480 ALLEGRO_EDITOR SCHEM_FTB Importing netlist using Capture-CM flow in PCB Editor is crashing netrev0 L" W, m* U1 ~% h% Y
2046276 ALLEGRO_EDITOR SHAPE Add notch is not snapping to the grid point
2 e$ C; D: I$ J2047572 ALLEGRO_EDITOR SHAPE Voiding elements on static shape do not void adjacent layer keep-outs and PCB Editor stops responding$ ~1 Y- L* q1 V$ O! S
2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update" Q6 ^- q+ W- B Q: M k' M, g5 q
2050120 ALLEGRO_EDITOR SHAPE Dynamic fill is flooding over other etch shapes within a symbol.
, G f" E9 Y. o$ T9 F: ?- b2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present" `3 Q! \# I$ M9 D' {2 Z9 S8 g
2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in hotfix 048.
4 P# |4 w9 |9 x! ^1 J: }2 I2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash# H) B9 l- R; f/ ]7 L
1961689 ALLEGRO_EDITOR SYMBOL Pin Numbers are moved from center with Pin Rotation when adding pins to Footprint0 v2 @" w: K! p- Q G1 {
2034949 ALLEGRO_EDITOR SYMBOL Angular dimension from DRA not created in PCB
) c0 P( u* B, Y% t! ~1 r0 P/ S2046242 ALLEGRO_EDITOR UI_GENERAL Searching User Preference Summary results in crash1 H' G9 f5 E& L: N* m/ h
2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog box is behind canvas
* J6 E6 Y: g6 C) S# G. i6 T2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden1 z5 q" ?8 L s1 C# X* j
1886781 ALLEGRO_VIEWER OTHER Opening Color192 in Allegro Free Viewer causes it to crash! }% e+ j4 n* x6 w
1699433 APD EDIT_ETCH Field solver runs when not expected
2 a7 R* `( B# t$ q/ ~. r1937159 APD EDIT_ETCH Routing clines takes long time4 f$ f- U3 R+ T7 z' S
2050863 APD SHAPE Taper voiding process is different in Within the region/Out of Region
2 V I0 B! p& ?0 V2047391 CAPTURE PART_EDITOR Pin type cannot be changed in hotfix 051
# y: M% j2 K! v1 l0 h+ q `2049161 CAP_EDIF IMPORT Fatal error 'cannot determine grid' when converting third-party design to Capture
6 m2 B% g u3 O5 P- O1 Y2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved
5 G4 y) y0 x8 l9 c! g, k5 \2047583 CONCEPT_HDL COPY_PROJECT Design Entry HDL crashing when trying to open page 52 of copied project: u+ L# H& x. j `) \
2036239 CONCEPT_HDL CORE When cutting/pasting, multiple error pop-ups appear for the same notification9 l9 W8 I& x6 }8 H( k
2037572 CONCEPT_HDL CORE Warning (SPCOCD-578): Soft VOLTAGE property found is misleading and should be auto resolved when closing CM' ]( ?& _; Z4 E* a- k
2037578 CONCEPT_HDL CORE VOLTAGE property gets deleted after copying it from a non-synchronized source
* v$ p+ j. V1 J; G7 t* X% ^9 q ^/ C! x2046958 CONCEPT_HDL CORE Moving block pins from symbol right to left places pin names outside the symbol- p) ~; j6 H( ?# ]- O R6 o$ a
2032480 CONSTRAINT_MGR CONCEPT_HDL Incorrect matchgroups created when working with multiple level nested hierarchical blocks
8 X: k5 W5 k( [2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor
" s0 O5 k* b6 ?1 @5 O" k( w2046765 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout 'dump libraries' crashes when exporting library
9 m8 h+ d, l1 b3 h# [2067970 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout cannot dump libraries, viewlog is empty
2 V7 Q- h& r Z+ r& D% p1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error2 Z5 G! E, w' |& k
1968437 SYSTEM_CAPTURE ASSIGN_SIGNAL Net name pasted in lower-case though UPPERCASE INPUT is enabled
- p o: a# q2 E. x1983063 SYSTEM_CAPTURE AUTOSHAPES Auto Shapes are being shown as part of components9 e2 s1 F' `2 P/ X
1968463 SYSTEM_CAPTURE CANVAS_EDIT System Capture should not allow illegal characters to be entered for net names
" h+ [& q% [0 c& d# |8 t/ V9 q) \( ?2006593 SYSTEM_CAPTURE CANVAS_EDIT Asterisk in a search string is not treated as a wildcard character
2 b5 Z% O+ s. ]5 Q3 Q- V1721863 SYSTEM_CAPTURE CONNECTIVITY_ Net Names move to random locations when the components are moved around the canvas
z7 d) b8 C x- W9 f' o: P1 s' e1960130 SYSTEM_CAPTURE CONNECTIVITY_ Disconnected nets when using the mirror option
- W6 N; B6 D% _/ P: q3 H2 t1985029 SYSTEM_CAPTURE EDIT_OPERATIO Net aliases do not drag with circuit, they appear to move after the circuit is dropped
" I( f* i: s# u- c, O# q1 J' {1 @1895142 SYSTEM_CAPTURE EXPORT_PCB System Capture reports incorrect unsaved changes when closed after running export physical4 l6 |2 @! j7 u/ t* n# C4 J
1628596 SYSTEM_CAPTURE FIND_REPLACE Alias issue in Find: Results do not show the resolved physical net names
0 L+ A& j/ N5 c+ Y: I9 \: w1988297 SYSTEM_CAPTURE FIND_REPLACE Edit > Find and Replace does not replace a net with an existing net on the canvas
' D# k% q6 N" I- q& H Y- N1843885 SYSTEM_CAPTURE FORMAT_OBJECT Renaming a net causes it to lose custom color assignment
! J, H2 Z H9 m% ]! K# ^2 [1969308 SYSTEM_CAPTURE FORMAT_OBJECT System Capture: Clicking arrows to increase/decrease font size does not work correctly when clicked fast
3 ]$ T8 @0 u1 M* l5 p3 k1990060 SYSTEM_CAPTURE FORMAT_OBJECT Bold, italics, and underline formats not visually shown on all selected objects concurrently
& m3 K8 Z: k8 x P1 `) g( ~1993208 SYSTEM_CAPTURE FORMAT_OBJECT Setting font prior to placing text does not work, pop-up does not work, and bucket results in scrolling page
2 h( l% w2 {) O+ M1 x1981775 SYSTEM_CAPTURE IMPORT_PCB Import Physical takes a long time on some designs to launch the UI
7 g) N. f' g4 R& P6 F1 W4 l1982320 SYSTEM_CAPTURE IMPORT_PCB In the B2F flow none of the *view files are created$ g! V, M2 d8 Q; g7 t2 i1 |8 S [
2010996 SYSTEM_CAPTURE INSERT_PICTUR Image in title block is at a wrong location in design: correctly placed in library& k0 }% R9 }: S" d
1967614 SYSTEM_CAPTURE MISCELLANEOUS Dragging a circuit with net aliases does not move the net aliases with it* b% q, `3 Q5 F$ W" ^7 U' G+ w
1980999 SYSTEM_CAPTURE NEW_PROJECT System Capture stops working with message regarding Part Manager initialization for a design based on DE-HDL$ ]: X/ k" }: S; M2 Q: z
1973437 SYSTEM_CAPTURE OPEN_CLOSE_PR Opening a design crashes System Capture
' U& l! {3 i2 N9 V$ P% G1986566 SYSTEM_CAPTURE OPEN_CLOSE_PR System Captures stops responding on opening project, cleaning project displays project already open message
1 {2 S- M9 g6 I1 W1993093 SYSTEM_CAPTURE OPEN_CLOSE_PR Add option to override the lock file similar to Allegro PCB Editor2 R# [& Q' W" u2 m7 E1 `& i8 J
2042360 SYSTEM_CAPTURE OPEN_CLOSE_PR System Capture will not open nor gives error message when previous lock file present inside the logic folder0 Z1 f( M4 f! o- X- I
1992247 SYSTEM_CAPTURE PART_MANAGER Part Manager displays message for undo and redo stack even after specifying not to show message
& i9 k) m9 Y5 { p+ M2048000 SYSTEM_CAPTURE PERFORMANCE Performance issue when instantiating and moving a component
; d% b# d* A7 T1892120 SYSTEM_CAPTURE PROPERTY_EDIT Some parts missing reference designators and some have two properties, RefDes and REFDES
- B; K5 ]: M% R8 T4 }2 {1970009 SYSTEM_CAPTURE PROPERTY_EDIT System Capture: Right-clicking RefDes with conflict in 'Edit Properties' shows the Hyperlink option
1 [1 ]! Q! V2 _0 T- S' ]: H: y( ^2042707 SYSTEM_CAPTURE VARIANT_MANAG variant.lst file under 'physical' folder not updated when closing Variant Editor
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发表于 2019-4-6 21:51
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