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装完还是显示052 - J1 G" t8 s- U, J
Fixed CCRs: SPB 17.2 HF053 B2 `" `( B, S- q1 i6 e% ]
03-01-20197 l, X7 a5 V+ n6 @- Y
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CCRID Product ProductLevel2 Title
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2035766 ADW DSN_MIGRATION EDM release 17.2-2016: design migration UI is cut off on right0 X! ~, |! O0 L1 r/ f3 S
2044872 ADW PART_BROWSER Component Browser: Only one PTF file read for multiple PTF files under Part Table all referenced in master.tag
) R1 w, w& @5 m' f2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name: _, X+ v- b0 s# n, L3 @+ w; A- k
2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design% o5 p Y; p& X6 M# _( v
2052046 ADW TDO-SHAREPOIN Joining projects is downloading 0-byte files due to SSL error+ K6 I( f6 o7 f+ a' a4 P7 G
2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object) q# k% r1 A* Q5 {& t% P
2047512 ALLEGRO_EDITOR 3D_CANVAS Mechanical components do not move when bending in 3D Viewer% y1 T: {1 F+ |3 L
2048086 ALLEGRO_EDITOR 3D_CANVAS Wirebonds are not linked to diepad when component is embedded body down
% Y e8 i. F' d4 e" S$ o2051277 ALLEGRO_EDITOR 3D_CANVAS 3D View Vias are Offset from Board in Z direction' ?2 t. p- H: ]( p$ d0 j3 l( F
2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation% c# ^) ^; B0 x4 C$ ]/ B2 G
2056547 ALLEGRO_EDITOR 3D_CANVAS 3D model not shown for component with STEP file assigned; b [9 s( \6 E0 ~3 C
2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded: Y/ C- }7 u/ _* {5 [: h1 d: s) I- _
2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone* L- A5 j3 z8 A( e# X3 y; l
1826533 ALLEGRO_EDITOR DATABASE Dyn_Thermal_Con_Type not behaving as defined in Symbol Editor after placing on PCB file.; s$ P x1 B& c8 m6 [% r( d" f
1857282 ALLEGRO_EDITOR DATABASE PCB Editor slow when Manhattan and Path length tooltip enabled in datatip customization
( K' {4 w, A- f6 v2052767 ALLEGRO_EDITOR DATABASE Allegro PCB Editor crashes on editing padstack4 J v. E7 u7 F$ B
1825692 ALLEGRO_EDITOR DRAFTING Dimension line text moved by Update Symbols$ Q" q/ c0 i! t1 t& r& v9 P
1874814 ALLEGRO_EDITOR DRAFTING 'Connect Lines' does not merge overlapping lines" U( `6 v- Q/ `* W
1874935 ALLEGRO_EDITOR DRAFTING Angular dimension text has extra spaces added before the degree symbol.4 \" C; E4 F# R" S
1882597 ALLEGRO_EDITOR DRAFTING 'Trim Segment' should allow trimming for all intersecting segment types
% ~$ F) `3 U% q# n$ h/ T& N# _+ W2052315 ALLEGRO_EDITOR DRC_CONSTR DRC (pad-shape) incorrect when both pad and drill are offset from pad origin.( o5 S0 w# M; r) O/ @1 I' O1 [
2040603 ALLEGRO_EDITOR EDIT_SHAPE Shape is not updating correctly after the 'move' command: [+ |* Q, l6 M8 e9 o
2050177 ALLEGRO_EDITOR INTERACTIV Letters need to remain aligned and uniform after performing Boolean ANDNOT operation
" O, h. W2 N+ |7 Z' H3 E2 ]0 m2052586 ALLEGRO_EDITOR IPC IPC356 showing shorts and disconnects for chip-on-board design
. L# B/ i. I- Q* k* W+ h. p2044350 ALLEGRO_EDITOR MANUFACT Cross Section table showing multiple decimal digits for the Tolerance column
S$ W8 f$ Q9 l# I5 C5 V/ o2051150 ALLEGRO_EDITOR NC Counterbore/Countersink holes not being shown in the NC legend table.) l* i6 z( c, F1 C2 M, g
2058199 ALLEGRO_EDITOR NC 'Manufacture - NC - Drill Legend' does not populate the CounterBore/CounterSink row values in the Drill Chart table, p7 |; m- s. I3 x' x
2061809 ALLEGRO_EDITOR NC Counter bore NC Legend does not show any data
( ]* Z( q8 c/ ^8 v9 M$ [4 v2063477 ALLEGRO_EDITOR NC Counter bore NC Legend does not show its value
3 g2 b$ K) z2 q. ]2033849 ALLEGRO_EDITOR PLACEMENT PCB Editor stops responding when removing a plane that the Place Replicate command added
% q1 ^* Y5 v0 e4 E1 x1 \1 A2037509 ALLEGRO_EDITOR PLACEMENT Move or Rotate or Mirror of a module/group makes PCB Editor to crash with no .SAV file created7 D; u# `3 R) R# `
2047480 ALLEGRO_EDITOR SCHEM_FTB Importing netlist using Capture-CM flow in PCB Editor is crashing netrev
1 X E) e: V1 d1 o2046276 ALLEGRO_EDITOR SHAPE Add notch is not snapping to the grid point
( i5 p5 w( _( t& b) e5 _) i. \2047572 ALLEGRO_EDITOR SHAPE Voiding elements on static shape do not void adjacent layer keep-outs and PCB Editor stops responding
, D6 J8 i* D5 B. }2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update* n7 X4 v+ v7 h$ y' S
2050120 ALLEGRO_EDITOR SHAPE Dynamic fill is flooding over other etch shapes within a symbol.) b: w3 l7 L0 U8 y. ~& `$ h
2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present/ w4 h6 N+ ~1 x$ V
2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in hotfix 048.* g9 `1 T1 Q) c! e! c+ e4 Y) Q
2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash
! V( C. `" Y6 I1961689 ALLEGRO_EDITOR SYMBOL Pin Numbers are moved from center with Pin Rotation when adding pins to Footprint
7 ^7 t, @% L m3 \6 f2034949 ALLEGRO_EDITOR SYMBOL Angular dimension from DRA not created in PCB
6 y9 p! |9 t- p, r2046242 ALLEGRO_EDITOR UI_GENERAL Searching User Preference Summary results in crash
; l" r- U) C+ B6 E) A" R2 p2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog box is behind canvas$ k4 f- B0 g$ A: x) e
2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden, E P; f; I& i6 Y
1886781 ALLEGRO_VIEWER OTHER Opening Color192 in Allegro Free Viewer causes it to crash$ m$ ?% T- }' e, q- ]& t3 D
1699433 APD EDIT_ETCH Field solver runs when not expected
# K9 Q1 f* ?5 N8 @$ `1937159 APD EDIT_ETCH Routing clines takes long time+ G" o- w% N, G9 F9 A% q
2050863 APD SHAPE Taper voiding process is different in Within the region/Out of Region
& C/ z) p- z) r T, a$ z2047391 CAPTURE PART_EDITOR Pin type cannot be changed in hotfix 051
: W2 |' X" L" Y- l' K2049161 CAP_EDIF IMPORT Fatal error 'cannot determine grid' when converting third-party design to Capture) d! k- F% D6 L
2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved
6 h7 y( o2 c4 P2047583 CONCEPT_HDL COPY_PROJECT Design Entry HDL crashing when trying to open page 52 of copied project/ H; B6 k2 x p3 S( r" t% k: B
2036239 CONCEPT_HDL CORE When cutting/pasting, multiple error pop-ups appear for the same notification' y9 N1 P0 \0 d/ y7 [5 }
2037572 CONCEPT_HDL CORE Warning (SPCOCD-578): Soft VOLTAGE property found is misleading and should be auto resolved when closing CM
! u! I2 A0 r: g) K5 u2037578 CONCEPT_HDL CORE VOLTAGE property gets deleted after copying it from a non-synchronized source
$ Y& T" ^- v5 O5 @" A+ D1 a2046958 CONCEPT_HDL CORE Moving block pins from symbol right to left places pin names outside the symbol
9 ]3 W5 f: o! P Q& ~* o9 d/ U4 A2032480 CONSTRAINT_MGR CONCEPT_HDL Incorrect matchgroups created when working with multiple level nested hierarchical blocks
0 `" C) Q3 d5 _" l3 X/ o; Q2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor- S0 d( H; x- y
2046765 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout 'dump libraries' crashes when exporting library
- s/ g' w2 r% P# s/ d& y {& ^2067970 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout cannot dump libraries, viewlog is empty% v% T8 |! X: d3 b8 N
1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error+ c3 c6 ]. W$ e" [8 ]
1968437 SYSTEM_CAPTURE ASSIGN_SIGNAL Net name pasted in lower-case though UPPERCASE INPUT is enabled
( K" M: ]% t) d0 ?6 P* K" H$ P# _1983063 SYSTEM_CAPTURE AUTOSHAPES Auto Shapes are being shown as part of components3 h/ u# q6 S6 _# \7 X( Y
1968463 SYSTEM_CAPTURE CANVAS_EDIT System Capture should not allow illegal characters to be entered for net names, b3 \& q# G) H( q# G1 f6 o
2006593 SYSTEM_CAPTURE CANVAS_EDIT Asterisk in a search string is not treated as a wildcard character
0 A$ M& u! V9 ^$ N$ I& H1721863 SYSTEM_CAPTURE CONNECTIVITY_ Net Names move to random locations when the components are moved around the canvas
# P' l) a! O( }% Y4 z V1960130 SYSTEM_CAPTURE CONNECTIVITY_ Disconnected nets when using the mirror option
! p* g- [" h3 {3 K8 C8 _# ]1 s1985029 SYSTEM_CAPTURE EDIT_OPERATIO Net aliases do not drag with circuit, they appear to move after the circuit is dropped
: O& M8 T- Z, ^) h! @1895142 SYSTEM_CAPTURE EXPORT_PCB System Capture reports incorrect unsaved changes when closed after running export physical
2 Y. k B7 \0 ]2 q0 `1628596 SYSTEM_CAPTURE FIND_REPLACE Alias issue in Find: Results do not show the resolved physical net names
+ H+ l( @" O1 N4 N1988297 SYSTEM_CAPTURE FIND_REPLACE Edit > Find and Replace does not replace a net with an existing net on the canvas( w* G6 ~$ V) [: y0 t, D
1843885 SYSTEM_CAPTURE FORMAT_OBJECT Renaming a net causes it to lose custom color assignment2 P7 B! y3 p# | C' D/ A
1969308 SYSTEM_CAPTURE FORMAT_OBJECT System Capture: Clicking arrows to increase/decrease font size does not work correctly when clicked fast( V0 l u- W& T, K7 T( v
1990060 SYSTEM_CAPTURE FORMAT_OBJECT Bold, italics, and underline formats not visually shown on all selected objects concurrently
' e+ T9 x+ [. w Y% H1993208 SYSTEM_CAPTURE FORMAT_OBJECT Setting font prior to placing text does not work, pop-up does not work, and bucket results in scrolling page
/ o' ?6 A4 V1 [1 A* J% }9 x$ h7 W1981775 SYSTEM_CAPTURE IMPORT_PCB Import Physical takes a long time on some designs to launch the UI
( ]- ~& @6 J( U1982320 SYSTEM_CAPTURE IMPORT_PCB In the B2F flow none of the *view files are created
* S/ L0 ~8 o, w0 |1 M$ H3 f* y2010996 SYSTEM_CAPTURE INSERT_PICTUR Image in title block is at a wrong location in design: correctly placed in library
1 Q6 s3 T& T) E* X* Y3 t" k1967614 SYSTEM_CAPTURE MISCELLANEOUS Dragging a circuit with net aliases does not move the net aliases with it% t, E2 Y3 p( [$ y
1980999 SYSTEM_CAPTURE NEW_PROJECT System Capture stops working with message regarding Part Manager initialization for a design based on DE-HDL
0 [( P4 f: z1 V4 U: r+ U# Q1973437 SYSTEM_CAPTURE OPEN_CLOSE_PR Opening a design crashes System Capture. j9 F6 z' J+ N1 T3 n7 U6 z/ k
1986566 SYSTEM_CAPTURE OPEN_CLOSE_PR System Captures stops responding on opening project, cleaning project displays project already open message3 w2 P1 K5 B& p
1993093 SYSTEM_CAPTURE OPEN_CLOSE_PR Add option to override the lock file similar to Allegro PCB Editor/ ^) j1 h) R! s
2042360 SYSTEM_CAPTURE OPEN_CLOSE_PR System Capture will not open nor gives error message when previous lock file present inside the logic folder
$ ~5 b2 x1 B7 y1992247 SYSTEM_CAPTURE PART_MANAGER Part Manager displays message for undo and redo stack even after specifying not to show message
6 f" Q! w+ W+ W6 C y3 }( q3 ^2048000 SYSTEM_CAPTURE PERFORMANCE Performance issue when instantiating and moving a component' p: b- A! x0 e5 |; i# o4 \: B) [9 A
1892120 SYSTEM_CAPTURE PROPERTY_EDIT Some parts missing reference designators and some have two properties, RefDes and REFDES7 l, H- d/ j- [4 e, q3 I6 A
1970009 SYSTEM_CAPTURE PROPERTY_EDIT System Capture: Right-clicking RefDes with conflict in 'Edit Properties' shows the Hyperlink option
/ a& M2 V. Q2 T2 i2042707 SYSTEM_CAPTURE VARIANT_MANAG variant.lst file under 'physical' folder not updated when closing Variant Editor
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发表于 2019-4-6 21:51
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