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装完还是显示052 : K4 v. o: J; ` I
Fixed CCRs: SPB 17.2 HF053- ? {( n- |8 `( [
03-01-2019% p! x% a4 d, d/ g
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CCRID Product ProductLevel2 Title
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2035766 ADW DSN_MIGRATION EDM release 17.2-2016: design migration UI is cut off on right- O5 I5 W5 F; O5 P! k
2044872 ADW PART_BROWSER Component Browser: Only one PTF file read for multiple PTF files under Part Table all referenced in master.tag, }- z" v( n7 z' m: Y/ R8 g: r2 t
2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name; Z1 u9 b* R' Q6 ?# x4 n
2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design3 G. {6 k( T9 h8 f) R
2052046 ADW TDO-SHAREPOIN Joining projects is downloading 0-byte files due to SSL error/ S8 G7 h1 ~, n, r; x
2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object
5 W* t1 c2 G8 \% W2 }. u+ m2 u6 g2047512 ALLEGRO_EDITOR 3D_CANVAS Mechanical components do not move when bending in 3D Viewer6 ?& g2 f, o! t4 S: R
2048086 ALLEGRO_EDITOR 3D_CANVAS Wirebonds are not linked to diepad when component is embedded body down( W9 A8 F6 }" Z- G" V( C9 _7 k" J+ ^
2051277 ALLEGRO_EDITOR 3D_CANVAS 3D View Vias are Offset from Board in Z direction
- p/ _! v; F* |# L" G& N2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation U: h8 [& X# U$ G
2056547 ALLEGRO_EDITOR 3D_CANVAS 3D model not shown for component with STEP file assigned1 {. n/ y$ Y7 q# ]
2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded7 P& I0 f- f2 |) q, p8 I/ S# T
2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone+ J/ h# m3 T+ ]! N0 d. o4 ~! V
1826533 ALLEGRO_EDITOR DATABASE Dyn_Thermal_Con_Type not behaving as defined in Symbol Editor after placing on PCB file.
5 O% [1 q% ]/ M, L! M1857282 ALLEGRO_EDITOR DATABASE PCB Editor slow when Manhattan and Path length tooltip enabled in datatip customization8 Z5 g; J2 p) v2 U$ [- W, ~/ t
2052767 ALLEGRO_EDITOR DATABASE Allegro PCB Editor crashes on editing padstack! Z2 a$ j# j: M9 z; d7 u
1825692 ALLEGRO_EDITOR DRAFTING Dimension line text moved by Update Symbols
& a3 g5 E/ d8 R) }7 j1874814 ALLEGRO_EDITOR DRAFTING 'Connect Lines' does not merge overlapping lines" P3 g* I d+ G# b
1874935 ALLEGRO_EDITOR DRAFTING Angular dimension text has extra spaces added before the degree symbol.
$ n4 y7 R; q; @5 r _" M( {/ C- w1882597 ALLEGRO_EDITOR DRAFTING 'Trim Segment' should allow trimming for all intersecting segment types
, K6 x {/ ^ m3 [2052315 ALLEGRO_EDITOR DRC_CONSTR DRC (pad-shape) incorrect when both pad and drill are offset from pad origin.
3 }$ h+ v/ O+ J& A. j& `! q# i$ r2040603 ALLEGRO_EDITOR EDIT_SHAPE Shape is not updating correctly after the 'move' command
2 S! s( f: P/ h2 b2 e: t( {3 ]0 j; {2050177 ALLEGRO_EDITOR INTERACTIV Letters need to remain aligned and uniform after performing Boolean ANDNOT operation
6 f2 I/ T- D! O2052586 ALLEGRO_EDITOR IPC IPC356 showing shorts and disconnects for chip-on-board design; m, i1 A& t' i0 K2 D3 a3 r
2044350 ALLEGRO_EDITOR MANUFACT Cross Section table showing multiple decimal digits for the Tolerance column
3 @/ g) t0 F9 o$ n6 W4 B2051150 ALLEGRO_EDITOR NC Counterbore/Countersink holes not being shown in the NC legend table.
2 Q4 W) r2 y$ P# u2058199 ALLEGRO_EDITOR NC 'Manufacture - NC - Drill Legend' does not populate the CounterBore/CounterSink row values in the Drill Chart table
5 s& E$ S! G5 c5 n9 w2 X2061809 ALLEGRO_EDITOR NC Counter bore NC Legend does not show any data
' L- {8 R: L# A0 n6 B: |0 M5 M2063477 ALLEGRO_EDITOR NC Counter bore NC Legend does not show its value
/ ~6 k: ?9 h% W7 y. F+ H: A! }6 Z2 k; Q2033849 ALLEGRO_EDITOR PLACEMENT PCB Editor stops responding when removing a plane that the Place Replicate command added
2 ^! c2 x. u$ [* k1 I" o2037509 ALLEGRO_EDITOR PLACEMENT Move or Rotate or Mirror of a module/group makes PCB Editor to crash with no .SAV file created
# ~( P! y& e; K r2047480 ALLEGRO_EDITOR SCHEM_FTB Importing netlist using Capture-CM flow in PCB Editor is crashing netrev4 P+ M( Q( G9 ^8 _
2046276 ALLEGRO_EDITOR SHAPE Add notch is not snapping to the grid point
' A2 I$ J4 Y Y4 W. H8 D9 E2047572 ALLEGRO_EDITOR SHAPE Voiding elements on static shape do not void adjacent layer keep-outs and PCB Editor stops responding
) v6 |1 M& E( o1 I) }% r2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update1 _2 N& [# O! P" e& n
2050120 ALLEGRO_EDITOR SHAPE Dynamic fill is flooding over other etch shapes within a symbol.# @: ?5 W, k( s; O* C! P
2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present
& e3 I, _) f7 \* c2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in hotfix 048." E2 e" [" l1 U5 Q/ N; U1 }
2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash# P: a9 R* t1 ~ y. [4 R
1961689 ALLEGRO_EDITOR SYMBOL Pin Numbers are moved from center with Pin Rotation when adding pins to Footprint! y# J' I. ]( P
2034949 ALLEGRO_EDITOR SYMBOL Angular dimension from DRA not created in PCB8 A( e4 o" k- y) y* n
2046242 ALLEGRO_EDITOR UI_GENERAL Searching User Preference Summary results in crash
+ R7 @ a8 n: S" d2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog box is behind canvas
( j' N8 F. L/ e- x& b" F9 Q4 b2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden9 P" X5 `2 p, p/ h
1886781 ALLEGRO_VIEWER OTHER Opening Color192 in Allegro Free Viewer causes it to crash; _$ V7 R. ^# b5 p" M
1699433 APD EDIT_ETCH Field solver runs when not expected0 U& N0 h4 b" G
1937159 APD EDIT_ETCH Routing clines takes long time$ D. j( g: U$ k$ e9 e% q/ S
2050863 APD SHAPE Taper voiding process is different in Within the region/Out of Region; A( j2 U7 h8 v
2047391 CAPTURE PART_EDITOR Pin type cannot be changed in hotfix 051
( y" A. R5 `2 i0 A# f- K l2049161 CAP_EDIF IMPORT Fatal error 'cannot determine grid' when converting third-party design to Capture6 ?) Q) J& m, m# S3 {7 R" u8 h+ M
2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved
( D' o. a! N# U/ n2047583 CONCEPT_HDL COPY_PROJECT Design Entry HDL crashing when trying to open page 52 of copied project b" ]/ w u0 {0 D* e
2036239 CONCEPT_HDL CORE When cutting/pasting, multiple error pop-ups appear for the same notification
* t- A! E5 r0 s7 J9 A2037572 CONCEPT_HDL CORE Warning (SPCOCD-578): Soft VOLTAGE property found is misleading and should be auto resolved when closing CM5 ~6 o! c& y( E' g4 e7 G
2037578 CONCEPT_HDL CORE VOLTAGE property gets deleted after copying it from a non-synchronized source) z5 ]" Q( [) x$ I: V a
2046958 CONCEPT_HDL CORE Moving block pins from symbol right to left places pin names outside the symbol" a: W5 r9 Q! V3 I2 n. f
2032480 CONSTRAINT_MGR CONCEPT_HDL Incorrect matchgroups created when working with multiple level nested hierarchical blocks+ f7 M; h) Q& `6 N$ q
2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor. g1 L; x5 `8 ^9 E3 y8 {1 c; q/ A( o
2046765 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout 'dump libraries' crashes when exporting library
5 c/ n5 x+ X/ |$ o- K! F2067970 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout cannot dump libraries, viewlog is empty
" B: Y& _, \# b7 }1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error
! ^3 R/ v9 ?6 Y/ V5 p1968437 SYSTEM_CAPTURE ASSIGN_SIGNAL Net name pasted in lower-case though UPPERCASE INPUT is enabled+ }$ N& n6 I& j/ z
1983063 SYSTEM_CAPTURE AUTOSHAPES Auto Shapes are being shown as part of components
/ M `2 [& O5 I1968463 SYSTEM_CAPTURE CANVAS_EDIT System Capture should not allow illegal characters to be entered for net names' o' C3 B6 G% t0 ^$ y
2006593 SYSTEM_CAPTURE CANVAS_EDIT Asterisk in a search string is not treated as a wildcard character/ Y9 E$ U! A3 E! K2 w' K
1721863 SYSTEM_CAPTURE CONNECTIVITY_ Net Names move to random locations when the components are moved around the canvas
h3 R" {6 J- T- |/ h" ?- k1960130 SYSTEM_CAPTURE CONNECTIVITY_ Disconnected nets when using the mirror option
) X; V9 Y! |8 t4 a) S1985029 SYSTEM_CAPTURE EDIT_OPERATIO Net aliases do not drag with circuit, they appear to move after the circuit is dropped
( K6 J( l7 `. d5 L3 @3 Y1895142 SYSTEM_CAPTURE EXPORT_PCB System Capture reports incorrect unsaved changes when closed after running export physical% g2 P1 A" e0 M* ~- P5 B
1628596 SYSTEM_CAPTURE FIND_REPLACE Alias issue in Find: Results do not show the resolved physical net names
+ T- {. |; a7 w" x4 P1988297 SYSTEM_CAPTURE FIND_REPLACE Edit > Find and Replace does not replace a net with an existing net on the canvas
) B6 R: G, d! n5 _0 T1843885 SYSTEM_CAPTURE FORMAT_OBJECT Renaming a net causes it to lose custom color assignment
+ a! b4 t$ I- Z+ r1969308 SYSTEM_CAPTURE FORMAT_OBJECT System Capture: Clicking arrows to increase/decrease font size does not work correctly when clicked fast0 Q# d0 Q. S7 p$ ~
1990060 SYSTEM_CAPTURE FORMAT_OBJECT Bold, italics, and underline formats not visually shown on all selected objects concurrently& }, M1 b0 [; n2 w
1993208 SYSTEM_CAPTURE FORMAT_OBJECT Setting font prior to placing text does not work, pop-up does not work, and bucket results in scrolling page2 o; w1 m P+ b' n3 R
1981775 SYSTEM_CAPTURE IMPORT_PCB Import Physical takes a long time on some designs to launch the UI. D" Z2 r2 C5 @' s/ W9 G) q
1982320 SYSTEM_CAPTURE IMPORT_PCB In the B2F flow none of the *view files are created9 g, ]" {, K; u; g" [8 C2 h
2010996 SYSTEM_CAPTURE INSERT_PICTUR Image in title block is at a wrong location in design: correctly placed in library) v0 P& |4 U/ v" p& a
1967614 SYSTEM_CAPTURE MISCELLANEOUS Dragging a circuit with net aliases does not move the net aliases with it N+ m7 v0 s/ ]6 |+ q; @
1980999 SYSTEM_CAPTURE NEW_PROJECT System Capture stops working with message regarding Part Manager initialization for a design based on DE-HDL
; g% ?- ]5 v& K7 b7 E: L$ V, d1973437 SYSTEM_CAPTURE OPEN_CLOSE_PR Opening a design crashes System Capture" w ^$ J2 ?1 j8 x4 O3 A+ d
1986566 SYSTEM_CAPTURE OPEN_CLOSE_PR System Captures stops responding on opening project, cleaning project displays project already open message
, \- j- h, \$ ?! E" I2 r1993093 SYSTEM_CAPTURE OPEN_CLOSE_PR Add option to override the lock file similar to Allegro PCB Editor1 @8 k, ?0 a5 f: [) ]
2042360 SYSTEM_CAPTURE OPEN_CLOSE_PR System Capture will not open nor gives error message when previous lock file present inside the logic folder
% J, G5 b2 K% e: l# O1992247 SYSTEM_CAPTURE PART_MANAGER Part Manager displays message for undo and redo stack even after specifying not to show message& m' d9 w3 a- ~) @
2048000 SYSTEM_CAPTURE PERFORMANCE Performance issue when instantiating and moving a component
; ~$ w) O+ J, O1892120 SYSTEM_CAPTURE PROPERTY_EDIT Some parts missing reference designators and some have two properties, RefDes and REFDES ~- w$ v% A, L7 ~/ _
1970009 SYSTEM_CAPTURE PROPERTY_EDIT System Capture: Right-clicking RefDes with conflict in 'Edit Properties' shows the Hyperlink option P) h5 W( f- [1 s, r5 t
2042707 SYSTEM_CAPTURE VARIANT_MANAG variant.lst file under 'physical' folder not updated when closing Variant Editor
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发表于 2019-4-6 21:51
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