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装完还是显示052 5 w( j2 z' [# l: ?
Fixed CCRs: SPB 17.2 HF053% e2 L. B% K. N% W/ [3 V
03-01-20196 I0 r* E- l3 {. e9 L
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& e) E# H( \. |$ U+ \8 uCCRID Product ProductLevel2 Title0 `- u- A" j0 L& N* V3 g
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2035766 ADW DSN_MIGRATION EDM release 17.2-2016: design migration UI is cut off on right( w' S$ g3 H1 q' ~, x4 a# ?7 T V
2044872 ADW PART_BROWSER Component Browser: Only one PTF file read for multiple PTF files under Part Table all referenced in master.tag
! ^# y. r. P. r' Q2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name
: P. m, M1 I. z9 `* I0 `2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design9 n& }# \" q% X8 X
2052046 ADW TDO-SHAREPOIN Joining projects is downloading 0-byte files due to SSL error
9 Y3 o+ H/ |! |- a2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object
9 R" P. O9 E+ G2047512 ALLEGRO_EDITOR 3D_CANVAS Mechanical components do not move when bending in 3D Viewer4 z( y2 e$ ^5 d) s" V
2048086 ALLEGRO_EDITOR 3D_CANVAS Wirebonds are not linked to diepad when component is embedded body down5 x% r' i$ I% y$ w# p8 T
2051277 ALLEGRO_EDITOR 3D_CANVAS 3D View Vias are Offset from Board in Z direction
/ l* e1 R, ]; ]; b5 H% ~/ c2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation" g/ E4 P! M( ^! I
2056547 ALLEGRO_EDITOR 3D_CANVAS 3D model not shown for component with STEP file assigned
+ c3 H+ L, I' U k2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded$ f0 g2 n8 W% o- V4 M g6 X
2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone
8 v6 ^* H) S. T/ Y8 {1826533 ALLEGRO_EDITOR DATABASE Dyn_Thermal_Con_Type not behaving as defined in Symbol Editor after placing on PCB file.
& o: j3 E; \2 [5 A* p+ D' g1857282 ALLEGRO_EDITOR DATABASE PCB Editor slow when Manhattan and Path length tooltip enabled in datatip customization! H! M K- {) {3 n9 k
2052767 ALLEGRO_EDITOR DATABASE Allegro PCB Editor crashes on editing padstack
4 G& C4 F! _. V1 j2 ?1825692 ALLEGRO_EDITOR DRAFTING Dimension line text moved by Update Symbols W4 `" f. P- z& @- [$ {0 a: y
1874814 ALLEGRO_EDITOR DRAFTING 'Connect Lines' does not merge overlapping lines* o% r+ j; ~$ V8 |
1874935 ALLEGRO_EDITOR DRAFTING Angular dimension text has extra spaces added before the degree symbol.
1 h# K) q2 l9 r/ d( I9 s1882597 ALLEGRO_EDITOR DRAFTING 'Trim Segment' should allow trimming for all intersecting segment types
, d) V- N5 @& `5 I2052315 ALLEGRO_EDITOR DRC_CONSTR DRC (pad-shape) incorrect when both pad and drill are offset from pad origin.2 ^9 F/ S8 G" X5 E" @
2040603 ALLEGRO_EDITOR EDIT_SHAPE Shape is not updating correctly after the 'move' command
9 E3 c7 T' I& K; y3 [/ i0 w2050177 ALLEGRO_EDITOR INTERACTIV Letters need to remain aligned and uniform after performing Boolean ANDNOT operation# u- I+ `5 [7 ?2 t: i- H
2052586 ALLEGRO_EDITOR IPC IPC356 showing shorts and disconnects for chip-on-board design
: E: `! C1 G" a' @2044350 ALLEGRO_EDITOR MANUFACT Cross Section table showing multiple decimal digits for the Tolerance column
5 v F$ z/ x" d* w2051150 ALLEGRO_EDITOR NC Counterbore/Countersink holes not being shown in the NC legend table.: s' ~. z$ D! g8 K/ }* G, e
2058199 ALLEGRO_EDITOR NC 'Manufacture - NC - Drill Legend' does not populate the CounterBore/CounterSink row values in the Drill Chart table
. B4 V: B; D- F! P6 U2061809 ALLEGRO_EDITOR NC Counter bore NC Legend does not show any data8 B: g4 p5 Y$ T/ S/ M, g
2063477 ALLEGRO_EDITOR NC Counter bore NC Legend does not show its value- v s; ?8 d* I/ d* S5 M
2033849 ALLEGRO_EDITOR PLACEMENT PCB Editor stops responding when removing a plane that the Place Replicate command added; `( Y T0 K4 F; N! y* j" r
2037509 ALLEGRO_EDITOR PLACEMENT Move or Rotate or Mirror of a module/group makes PCB Editor to crash with no .SAV file created+ y3 d+ @7 e) w) [2 g. Z
2047480 ALLEGRO_EDITOR SCHEM_FTB Importing netlist using Capture-CM flow in PCB Editor is crashing netrev* W# l8 V& V/ t4 ~; \1 X" j
2046276 ALLEGRO_EDITOR SHAPE Add notch is not snapping to the grid point
4 z S0 S ]! D3 `, h v2047572 ALLEGRO_EDITOR SHAPE Voiding elements on static shape do not void adjacent layer keep-outs and PCB Editor stops responding5 [, K! s" k3 ]) O
2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update
& ]. |- f `, b, E: U2050120 ALLEGRO_EDITOR SHAPE Dynamic fill is flooding over other etch shapes within a symbol.
5 | C- t+ G( D2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present
* \* S4 `0 N L; v' M3 O% @2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in hotfix 048.. R, N* y6 g1 d J
2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash8 m, [) o5 [/ I9 E4 {
1961689 ALLEGRO_EDITOR SYMBOL Pin Numbers are moved from center with Pin Rotation when adding pins to Footprint! Y; ~( D. w; j( S
2034949 ALLEGRO_EDITOR SYMBOL Angular dimension from DRA not created in PCB1 P6 p& |! K, H1 \5 B
2046242 ALLEGRO_EDITOR UI_GENERAL Searching User Preference Summary results in crash
3 B2 X c: Q% R5 U" B# b' a K+ X2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog box is behind canvas% |' m) y& V( ^' u* G8 }
2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden8 a: ]$ | Q0 q E
1886781 ALLEGRO_VIEWER OTHER Opening Color192 in Allegro Free Viewer causes it to crash# g M$ d6 F7 `! p+ H- O* c
1699433 APD EDIT_ETCH Field solver runs when not expected5 }' h& I" m- a4 j6 Y, S
1937159 APD EDIT_ETCH Routing clines takes long time+ K# y% `0 z4 V" z1 B1 E) E, P
2050863 APD SHAPE Taper voiding process is different in Within the region/Out of Region
& M, t: `4 Z4 K% r! b2 q5 x$ l2047391 CAPTURE PART_EDITOR Pin type cannot be changed in hotfix 0516 Y7 h/ g( B5 _6 B
2049161 CAP_EDIF IMPORT Fatal error 'cannot determine grid' when converting third-party design to Capture
, f; o3 E) e% }: p. b1 O) Q2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved
5 D+ h: b; [* ~4 c, q! N8 y2047583 CONCEPT_HDL COPY_PROJECT Design Entry HDL crashing when trying to open page 52 of copied project
6 P, O. x. Z# b$ f2036239 CONCEPT_HDL CORE When cutting/pasting, multiple error pop-ups appear for the same notification
. y) c' t7 g; v ^/ b) v D2037572 CONCEPT_HDL CORE Warning (SPCOCD-578): Soft VOLTAGE property found is misleading and should be auto resolved when closing CM
) u8 r) E! J$ `/ `6 @! Y( z4 G2037578 CONCEPT_HDL CORE VOLTAGE property gets deleted after copying it from a non-synchronized source: e, u2 z @/ m& }
2046958 CONCEPT_HDL CORE Moving block pins from symbol right to left places pin names outside the symbol
' o( G, W- P# i; A* B$ S' G2032480 CONSTRAINT_MGR CONCEPT_HDL Incorrect matchgroups created when working with multiple level nested hierarchical blocks
) D. p) H+ G. K1 L/ c2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor
, ` p- f' X/ {' B2046765 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout 'dump libraries' crashes when exporting library- {$ Q- G. C5 c3 a N
2067970 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout cannot dump libraries, viewlog is empty6 \3 \2 n. I F$ D3 p0 \8 i3 ~
1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error
: g! K- v T' g$ V6 q6 b7 W1968437 SYSTEM_CAPTURE ASSIGN_SIGNAL Net name pasted in lower-case though UPPERCASE INPUT is enabled
1 Q1 P% m5 u3 F7 d8 `2 d1983063 SYSTEM_CAPTURE AUTOSHAPES Auto Shapes are being shown as part of components
: S, f2 ?. E( P& u" p& Y$ G# ^ R$ V/ b1968463 SYSTEM_CAPTURE CANVAS_EDIT System Capture should not allow illegal characters to be entered for net names
2 ~0 k& B0 m, f" N2006593 SYSTEM_CAPTURE CANVAS_EDIT Asterisk in a search string is not treated as a wildcard character/ }0 y/ r( ^" _. w3 q
1721863 SYSTEM_CAPTURE CONNECTIVITY_ Net Names move to random locations when the components are moved around the canvas
) @5 Y6 D& J7 W& P5 E4 R- w1960130 SYSTEM_CAPTURE CONNECTIVITY_ Disconnected nets when using the mirror option# M5 _, g/ i, C4 b
1985029 SYSTEM_CAPTURE EDIT_OPERATIO Net aliases do not drag with circuit, they appear to move after the circuit is dropped
9 C* C5 \: r' q. `1895142 SYSTEM_CAPTURE EXPORT_PCB System Capture reports incorrect unsaved changes when closed after running export physical5 B. E) D8 g; ~
1628596 SYSTEM_CAPTURE FIND_REPLACE Alias issue in Find: Results do not show the resolved physical net names5 [! S( g8 F: O$ t5 h' h, @1 Q
1988297 SYSTEM_CAPTURE FIND_REPLACE Edit > Find and Replace does not replace a net with an existing net on the canvas
/ _5 s ]: _6 S, J1843885 SYSTEM_CAPTURE FORMAT_OBJECT Renaming a net causes it to lose custom color assignment
* ]) D! V% T5 _7 `& ^& [# Z% ^1969308 SYSTEM_CAPTURE FORMAT_OBJECT System Capture: Clicking arrows to increase/decrease font size does not work correctly when clicked fast2 `0 \+ B4 m3 j4 p
1990060 SYSTEM_CAPTURE FORMAT_OBJECT Bold, italics, and underline formats not visually shown on all selected objects concurrently
5 ]4 [" x9 z6 w. I( B/ F1993208 SYSTEM_CAPTURE FORMAT_OBJECT Setting font prior to placing text does not work, pop-up does not work, and bucket results in scrolling page5 j, Z3 A" @: G6 W8 n6 a; R$ A
1981775 SYSTEM_CAPTURE IMPORT_PCB Import Physical takes a long time on some designs to launch the UI
6 i( u3 O3 t) Z1982320 SYSTEM_CAPTURE IMPORT_PCB In the B2F flow none of the *view files are created8 M3 U9 b! G2 A2 ?$ L- J; Z
2010996 SYSTEM_CAPTURE INSERT_PICTUR Image in title block is at a wrong location in design: correctly placed in library) p# ~, l3 C, }9 |% m- V: U; ] |
1967614 SYSTEM_CAPTURE MISCELLANEOUS Dragging a circuit with net aliases does not move the net aliases with it' Y8 H) \! z5 I8 A* ?) {6 O% O
1980999 SYSTEM_CAPTURE NEW_PROJECT System Capture stops working with message regarding Part Manager initialization for a design based on DE-HDL: f) L$ t4 B6 W1 p2 S
1973437 SYSTEM_CAPTURE OPEN_CLOSE_PR Opening a design crashes System Capture
" J! ^1 L& x0 n3 b' V1986566 SYSTEM_CAPTURE OPEN_CLOSE_PR System Captures stops responding on opening project, cleaning project displays project already open message# x; Y" o h8 N8 [
1993093 SYSTEM_CAPTURE OPEN_CLOSE_PR Add option to override the lock file similar to Allegro PCB Editor0 j5 a; P, u/ x) o, R7 E$ G
2042360 SYSTEM_CAPTURE OPEN_CLOSE_PR System Capture will not open nor gives error message when previous lock file present inside the logic folder. ~6 L0 ~/ m0 h: k9 H' a
1992247 SYSTEM_CAPTURE PART_MANAGER Part Manager displays message for undo and redo stack even after specifying not to show message
- O, u& d& ^2 A+ c# f' B1 j2048000 SYSTEM_CAPTURE PERFORMANCE Performance issue when instantiating and moving a component
. ]+ f. R" B6 Q+ Y1892120 SYSTEM_CAPTURE PROPERTY_EDIT Some parts missing reference designators and some have two properties, RefDes and REFDES
0 U5 n' ^: d( d; \3 F$ x1970009 SYSTEM_CAPTURE PROPERTY_EDIT System Capture: Right-clicking RefDes with conflict in 'Edit Properties' shows the Hyperlink option
6 [; F8 e% o6 `2 C" W0 v' O3 W2042707 SYSTEM_CAPTURE VARIANT_MANAG variant.lst file under 'physical' folder not updated when closing Variant Editor
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