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本帖最后由 dsws 于 2014-4-28 12:56 编辑
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链接: http://pan.baidu.com/s/1dD9XLPB 密码: ujuq
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% t" q {2 Z1 e9 B g4 j gDATE: 04-25-2014 HOTFIX VERSION: 027% F) [( S( x; D |
===================================================================================================================================2 \5 p [7 w0 H o) ^- H
CCRID PRODUCT PRODUCTLEVEL2 TITLE
8 Q% m' z" T7 E/ A4 A5 h* S4 v' j- N===================================================================================================================================# S0 ^3 C6 |3 L- _$ Z
308701 CONSTRAINT_MGR OTHER Needs to delete user defined schedule in CM
- F' j. x1 q6 [ M" D( O: `481674 allegro_EDITOR pads_IN No board file saved from PADS_in5 Q0 [/ [5 M' Y4 u2 x3 C! [
982929 ALLEGRO_EDITOR EDIT_ETCH can't route on NC pin and other that are not pin.3 J" Z @. w1 M- V+ U+ n9 w+ H4 B& ?
1012783 FSP OTHER Need Undo Command in FSP9 c# H& T7 D9 t
1017381 ALLEGRO_EDITOR DRC_CONSTR Need Dynamic Phase to be able to measure back to the Drive Pins.
" N7 @ n! x% z% _* h1072673 PCB_LIBRARIAN GRAPHICAL_EDITOR Copy paste goes offgrid if mouse is moved
8 I7 F3 t6 x4 ~* ]& {1073231 concept_HDL CORE Copy-paste of signal names goes off-grid in Windows mode.
7 O- ~. R, M2 z0 B1105371 CONCEPT_HDL INTERFACE_DESIGN Strange behavior when shorting two Net groups7 |" G. R; ]: g' l& ?# Q
1116498 CIS LINK_DATABASE_PA link database with modified part results in Capture crash
% b/ x; a- x7 M# E. |1118632 ALLEGRO_EDITOR GRAPHICS Text display refresh issue while in Edit > text command W( }, z% v: r& Z" P# Q* |; P
1155821 SIG_INTEGRITY LIBRARY Xnet are not recalculated correctly when model is changed on the Series switch part defined as discrete with Espice mode8 S; o3 }+ `2 [" y
1157372 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase for Diff Pairs not reporting back to Driver pin if pin escapes present
3 J7 [$ `5 L3 w+ F1171951 ALLEGRO_EDITOR CREATE_SYM Jumper has a limited of count when it add to list. t- b2 O3 D1 n5 D6 X
1180871 CAPTURE LIBRARY_EDITOR Copied parts don't retain pin name and pin number settings8 J& h2 U8 ^3 k5 u
1185575 SIP_LAYOUT DIE_STACK_EDITOR Updating symbols causes the graphics for the Assy layer to change from Bottom to Top.7 a$ T7 L) d, ^' M" U
1185772 PCB_LIBRARIAN CORE VALID_PACK_TYPE warning when cell was opened in PDV. [1 ?; c3 h6 F) J
1192377 CAPTURE SCHEMATIC_EDITOR Pin name/number position is incorrect on schematic if it is changed for a rotated part.8 S7 I8 u& i6 F v
1202654 ALLEGRO_EDITOR GRAPHICS Zoom using mouse wheel shall maintain the center co-ordinates- I3 u6 X4 Y" J
1208031 ALLEGRO_EDITOR INTERACTIV Snap to Pin for via during Copy command do not snap to connect point everytime# C2 c1 }7 L" ]# Z
1208478 Pspice PROBE Attached project gives overflow error with marching ON.$ \4 D8 M# M- c* s9 X8 I- h
1210015 CONCEPT_HDL CORE The value of $PN should be not turned on spin or rotate symbol3 x) d* {: D1 [$ U4 C* |' E7 T- u
1210425 CONCEPT_HDL CORE When moving a circuit tool reports that connectivity has changed
$ @( ^9 _9 F, i, _2 t1215858 ALLEGRO_EDITOR SHAPE Force update does not void cline with the shape; _! n( \* x2 T8 j Y
1215906 ALLEGRO_EDITOR SHAPE Dynamic shape fill smooth failed when copying to other layers- j! D2 z: w# c& [" @: U
1216358 CONCEPT_HDL CORE Can we improve our export BOM function to check if user did export physical function before exporting BOM?
0 A$ d& M$ g3 a0 [1217364 CONCEPT_HDL OTHER Netlist reports fail because error: GScald failed.% v+ C4 c/ S6 i* ^+ J4 _& q
1217529 CONCEPT_HDL CORE ADW checks do not catch single quotes in PTF values" Z$ c) O4 `1 d' i7 ?
1217556 F2B PACKAGERXL signal name change not sent to Allegro after packaging
7 b' Y; e- @. z$ f1219283 ALLEGRO_EDITOR DRC_CONSTR Show constraint is inconsistent when displaying region information
" V; i$ A1 j7 y& f5 h7 h1220078 F2B PACKAGERXL Export Physical crashes when ALL the part pins are added
+ |4 ]# ?8 I& H4 J6 I! S1220393 CONSTRAINT_MGR CONCEPT_HDL HDL import physical from board file will annotate CM data back to HDL which includes cross-section thickness.$ X+ W+ S- W: g7 ^ i, V' b
1220540 ALLEGRO_EDITOR GRAPHICS Need an option to see the pads inside the internal plane shapes
, Y9 _0 p3 _- ~3 w2 X- r" i! P( B" Y1220936 CONCEPT_HDL CORE About crash by vpadd/vpdelete command on Linux5 |8 M, g$ W2 X7 S7 Z: `
1221059 ALLEGRO_EDITOR DRC_CONSTR Get a "Shape to Thru Via Spacing" DRC error only the first time when the shape is manually voided.
$ w" f R0 L" h3 v, t6 L2 w2 |% B1221182 ADW TDA Team Design with SAMBA
k/ W6 W4 j9 U; W* s: R3 K1222442 CONSTRAINT_MGR UI_FORMS Duplicate pin pairs appear in DiffPair
: `9 ?% i- G; E- {, C2 N1223175 CONCEPT_HDL CONSTRAINT_MGR Schematic crashes when opened
3 Y4 Z3 u7 x4 E$ {- m+ F1 H" t7 v1223533 ALLEGRO_EDITOR GRAPHICS Why the through pins for STEP models are shown at an offset when viewed in 3D inside Package Symbol?
* @; u6 U) H' y: p" x1223680 CONSTRAINT_MGR ECS_APPLY Improve ECSet mapping by allowing user to address ambiguity of Parts* v2 C" E/ }7 ]% }0 |
1224156 SIG_INTEGRITY SIGWAVE Exporting spreadsheet with filter Subitems in SigWave exports all waveforms
; @* R2 X0 T. O" L* c F4 e0 P1224417 ALLEGRO_EDITOR PLOTTING Hidden font pattern is not showing correct in 16.5 version also 16.6 version.6 B5 \: ]$ N. M w9 i5 M0 Q
1224704 F2B DESIGNVARI There is no lock for the variant.dat file - multiple users can open the editor# ~1 [% j% @- C! f
1224968 ALLEGRO_EDITOR INTERACTIV Delete >(RMB click) Cut> Snap Pick to>off grid loction does not work for lines.) y& f. n: t% i5 [# G
1224982 CONCEPT_HDL PDF commandline publishpdf does not work when there are spaces in the path
* N0 A+ z6 c" s) Z( y6 ]+ T; G1225114 CAPTURE GENERAL H-pins added after netgroup pin get color as of netgroup pin
1 g, C4 m1 A9 P1225494 CAPTURE DRC Different DRC results for Entire design and selection# ?1 J2 Y7 H2 S5 d* N2 @+ ~
1226153 ALLEGRO_EDITOR INTERFACES Export STEP should include PART_NUMBER property
$ \- [& a" J3 U1 h E1226235 ALLEGRO_EDITOR EDIT_ETCH Enhancement to include Pin_delay of descrete forming Xnet
" e# ]8 |7 C: T2 A3 J8 _ h) m8 z1226372 CAPTURE GENERATE_PART ENH: Functionality to add pin spacing in New Part From Spreadsheet' r( x) Q( ~- O4 V, p5 V, r
1226477 CONCEPT_HDL CORE DE HDL縮 `Allowed Global Shorts? function is inconvenient for Global Signal1 v" f1 d( `4 h& o/ Y- Q8 O% r
1226813 SIP_LAYOUT LEFDEF_IF ERROR SPMHLD-120 when importing a DEF file. Request to increase the number of characters/line in a .cml file) _+ }6 d9 M; l/ J8 H' |' i
1227453 ALLEGRO_EDITOR SHAPE Addition of Fillet generate Pin to Shape Spacing DRC errors and DBDOCTOR errors+ ^- J' D7 O4 t5 N
1227461 ALLEGRO_EDITOR SHAPE Sliding a cline for certain net changes the thermal relief connects for pins connected to another net from 4 to 5,6,7,8
" Y2 w; @% E6 |1227469 CIS DBC_CFG_WIZARD Oracle Views not visible on Step2 of CIS Configuration; Y9 \, r1 N. `% \" P$ e2 z, |' H: t1 e
1227780 CAPTURE ANNOTATE Inconsistent behaviour when annotating heterogeneous part5 T5 o: k! R, Y9 P2 ~: e
1227831 CONCEPT_HDL CORE Pin text and H-block name in upper case
6 l8 A9 U" T( r* S6 e1227954 CONCEPT_HDL OTHER supress check for global signals when wires are unconnected to pins0 t w: m! ]/ G: e: N( c
1228190 ALLEGRO_EDITOR OTHER Unable to close the 'usage' window during license selection
$ R8 b# o; p5 _( q4 _1 O1228899 CONSTRAINT_MGR INTERACTIV Export/Import constraints in "overwrite" mode from same design shows different results when imported second time.
$ U) \& O/ E2 j1228934 ALLEGRO_EDITOR EDIT_ETCH The "View Active Layer" option like the Board Station should be provided for dynamic layer visibility.6 M( u: y1 ]. R2 Y* X# w4 |
1229316 ALLEGRO_EDITOR EDIT_ETCH When routing with Hug only enabled we were able to route through other routes(sometimes Hug).
; T7 f/ x S1 @. {1229545 CONSTRAINT_MGR OTHER Allegro indicate bundle scheduled nets in CM
# b4 c' c: }' ]% f6 V# n5 x/ G# N/ J1230056 ALLEGRO_EDITOR GRAPHICS Bug: 3D View of Mechanical Symbol with the drill hole defined
+ [! d, d. j2 {2 T1230432 CONCEPT_HDL CORE No Description information in BOM
5 L( i* r/ y( o" Z1231148 F2B DESIGNVARI The variant.dat file is not updated with library PTF changes
q1 q9 t1 x8 Y/ F/ n/ d9 g1231625 F2B DESIGNSYNC VDD at command line needs to support sch2sch and test variable to write out report files V6 |$ ]. |1 q4 X6 R( g$ Y
1231697 CONCEPT_HDL CORE If any locked files exist force a pop-up dialog restricting certain commands. ?0 I. h/ S( @6 L3 G; v& q9 ~; i
1231767 CONCEPT_HDL OTHER Unable to find under the search options single bit vector nets: I1 R( Y% V/ m* S- i! T
1231961 ALLEGRO_EDITOR SHAPE Shapes not updating to smooth unless we use force update and as a result false DRC's appear in board.
# ]3 V# e9 e( t W% _$ }2 ~- [1232100 CONCEPT_HDL skill Unable to execute the SKILL commands in viewer mode/ R6 H% X, u( h: U6 g- j
1232336 CONSTRAINT_MGR CONCEPT_HDL cmFeedback takes 5hrs to complete during Import Physical
% [: H) w- b9 f% e9 R0 |/ w. v/ j1232710 F2B DESIGNVARI Dehdl crash while moving component in variant viewer mode% Y$ ~: O+ L2 l k- B( ]
1233894 F2B PACKAGERXL The page data is missing in the pst* and PCB files4 Q3 m" W1 I; L6 d
1235785 CONCEPT_HDL CREFER cref_from_list custom text is not subsitituted in complex hierarchy( v4 i' c% m S3 [; \
1235928 CAPTURE SCHEMATIC_EDITOR OleObject modifications not saved
( H- t5 W% n$ z$ ^- Z6 d- v, [& W1236065 CAPTURE PART_EDITOR Mirrored part after being edited get pin name locations incorrect
8 p5 H' x3 B4 e( h( X' S1 c1236071 ALLEGRO_EDITOR SHAPE Airgap for Octagonal Pads ignores DRC Value when Thermal set1 g4 K$ E, b6 u; ~) m$ x
1236072 CONCEPT_HDL CORE Page 122 cannot be saved as logical page 119 has different page mapping in connectivity data and schematic
6 d( ^+ _7 ~; d6 ]1236161 CONCEPT_HDL CORE Import Design shows the current project pages
- y+ p' Z. y, V( p0 v1236432 ALLEGRO_EDITOR PADS_IN pads_in doesnot translate via and shape in some instances.
7 }1 Q: |. i: |# m; h1 L- ]2 w1236557 CONCEPT_HDL PDF Running Publish PDF on command line in linux doesn't output progress until completion" P( |0 W- @! |' b
1236589 CONCEPT_HDL PDF Enhancement license failure error should appear in pdfpuplisher log file
) A3 t" U, L: H2 z8 u. j# [- m" R6 V1236644 ALLEGRO_EDITOR EDIT_ETCH create fanout deletes shape
3 V2 Q, U0 o: ]3 O4 t6 ^! m1236689 ALLEGRO_EDITOR GRAPHICS Graphics displays extraneous lines when panning or zooming
* J8 \7 K$ {% E- L: J( f1236781 F2B PACKAGERXL Export Physical produces empty files- r+ z7 e0 h X4 j, ^! U
1237331 PSPICE ENVIRONMENT pspice.exe <cir file name> - hangs when run& I- a) {) A: D/ I( @
1237400 CIS EXPLORER Capture hangs on 2 consecutive runs of `refresh symbol from lib? command
; n$ B) w8 @% b( r b& G) c1237437 CONCEPT_HDL CONSTRAINT_MGR CM Crash when saving after restore from definition8 Z1 R. b/ w+ Z0 M2 F& Y
1237862 CONSTRAINT_MGR OTHER A way to remove the RAVEL markers from the Constraint Manager.
z# x0 |) I5 Q* d5 L; ?7 H1238852 CAPTURE GENERAL signal list not updated for buses
& O u( U) \1 X3 X1238856 FSP DE-HDL_SCHEMATIC FSP schematic generation crashes' K- Z' q3 \6 F+ |' c9 j$ D0 y
1239079 ALLEGRO_EDITOR INTERACTIV The 16.6 Padstack > Replace function leaves old padstack.0 A+ H. i' f+ q# Y @. t
1239706 CONSTRAINT_MGR ANALYSIS The reflection result on a differential signal in the CM when Measurement location is DIE% Q% `/ b3 h0 X: ~6 H4 Z6 U
1239763 PSPICE PROBE Cannot modify text label if right y axis is active1 O0 s! p/ y% `% E
1240276 ALLEGRO_EDITOR GRAPHICS Printing to PDF from SigXp is giving unreadable images
, b! V3 r9 H# C; q' _' ]1240356 CAPTURE IMPORT/EXPORT Can縯 import SDT schematic to Capture.# O ~0 q0 Q; t% \5 o7 a7 g) ?
1240502 F2B PACKAGERXL Corrupt cfg_package does not stop PackagerXL from completing
6 c! i6 e* r3 k' D5 ~6 N: i1240607 ALLEGRO_EDITOR OTHER Footprint of screw hole got shift in DXF file, Z0 h/ ?% H; h; _7 d6 v
1240670 ALLEGRO_EDITOR PLACEMENT Select multiple parts and Rotate makes them immovable% _' o" K5 y9 p# w
1240773 CAPTURE DRC DRC check reports error for duplicate NetGroup Reference in complex hierarchy$ k* ~6 Y. c5 Q2 s% ?7 U
1240845 SIG_EXPLORER EXTRACTTOP Narrowband via models for Mirrored BB Vias not extracted in in the interconn.iml and this gives bad ringing in waveforms8 q# C% ]; ~) M! r9 j) {
1241634 ALLEGRO_EDITOR OTHER Netshort for pad-pad connect not working
. D( \! Y3 J( q) u+ z1241776 CONCEPT_HDL CORE In hierarchal design not all pages are getting printed.
: f. R. d' h; G4 F/ I2 |# W1241788 CONSTRAINT_MGR CONCEPT_HDL Issues with changing focus in Constraint manager using keys on keyboard
# x$ @2 Y( B$ g' A+ e6 s6 E1242683 ALLEGRO_EDITOR INTERACTIV Color View Save replaces file without warning
7 w0 I8 @2 z7 O: i1242818 ALLEGRO_EDITOR PLACEMENT Placement edit mirror option places component on wrong side3 I) e' @& U* s9 x' B
1242847 ALLEGRO_EDITOR GRAPHICS Need an option to suppress Via Holes in 3D Viewer2 @) P; T) @/ O/ r. \, z& ^
1242923 ADW COMPONENT_BROWSE UCB reports Missing From DB only after selecting the Row in the search results2 y2 _6 m6 |$ y8 W" m1 ]2 I3 x
1243609 CONCEPT_HDL CORE autoprop for occurrence properties4 x" w- l r9 F( s* c- f
1243682 F2B DESIGNVARI after undocking variant icon cannot be redocked back to GUI
1 I+ U+ V* x+ w6 J; b1243686 ALLEGRO_EDITOR GRAPHICS Invoking Edit->Text, the infinite cursor disappears until edit mode is changed.* b4 ~3 @. t. S" N' ?$ ~# X
1243715 CAPTURE PART_EDITOR Pin name positioning get changed after rotating or mirroring
/ }0 Z: Y6 d7 _# i1244945 CONCEPT_HDL PDF PDF Publisher does not include image when file is not located in the root folder
( E8 \1 G; v+ j7 Z" i9 E/ c1245568 CONCEPT_HDL CORE Dual unselect needed for wires attached to other net/source and property is not deselected when component is
/ ?, [' ]5 G# e. B9 L2 y! E1245819 F2B PACKAGERXL wrong injected properties information passed during packaging of the design5 |9 e9 p' T( z6 Q+ G: g P+ o
1245916 SCM CONCEPT_IMPORT Where does the folder location reside for DEHDL imported blocks?
, {+ B) g R e8 ]0 Y: S1246347 CONSTRAINT_MGR CONCEPT_HDL DEHDL crash if environment variable path has trailing backslash character8 U# ^# ]1 h# s- p Q9 N! f
1246896 ALLEGRO_EDITOR DFA DFA_UPDATE on Linux reports err message if the path has Upper case characters& \. }2 Z9 |- R9 _6 _
1247019 SIP_LAYOUT DIE_STACK_EDITOR SiP Layout - refresh/update symbols is mirroring the assembly drawing data on DIE that is placed ChipDown
$ Z. A0 `; v$ E3 d1247037 CAPTURE LIBRARY_EDITOR Copy & Paste of library parts resets pin name and number
s' @* s( K! }$ h; `. R1247089 CONCEPT_HDL CORE Group Align or Distribute > Left/Center/Right crashes DEHDL9 k2 K& R+ }: e6 y3 W \( O' e7 d
1247163 CONCEPT_HDL PDF Physical Net Names in PDF not maintained
/ B, x3 s6 x" _1 n1247462 CONCEPT_HDL CORE Text issue while moving with bounding box6 J2 [1 H0 u* j$ f
1247464 ALLEGRO_EDITOR UI_FORMS When using the define B/B via UI the end layer dropdown arrow is partially covered6 {4 ?0 [6 ^ Y# C8 I2 ]
1249063 CONCEPT_HDL CONSTRAINT_MGR CM and SigXP doesn縯 respect PACK_IGNORE at components
4 L$ J. I' \$ M* H }) ~! T1250270 CONCEPT_HDL CORE Part Manager Update places wrong parts- C; H- T- q: D, A4 J& V( Z
1251206 ALLEGRO_EDITOR ARTWORK Aperture command cannot create appropriate aperture automatically from design.: y u; p+ @" b% m
1251356 ALLEGRO_EDITOR INTERFACES Some STEP models are missing in 3D view of footprint, although all components have STEP model mapped in footprint8 n( p+ e0 d; U! R8 P: y- W
1251845 ALLEGRO_EDITOR EXTRACT Crosshatch arcs do not extract correctly
+ t' i- d# X* i. ^; m* l1252143 APD OTHER When using the beta "shape to cline" command the tool is removing the shape instead of converting it.
% u, n/ {/ u% y; D0 X( E1252737 SIP_LAYOUT OTHER SiP Layout - Option to create shapes from Pins for WLP wafer level packaging technologies3 m; ^* t" m+ L# `' L5 i5 }
1253424 SCM SCHGEN Export Schematics Crashes System Architect8 s! k1 e* c4 y3 M" i$ n7 P: \
1253508 ALLEGRO_EDITOR INTERFACES Bug - Export IPC2581 exports Crosshatch shapes as filled. W9 H& F( q% g5 u9 |
1253554 SIP_LAYOUT OTHER SiP Layout - Add Netlist Spreadsheet export to SiP layout to help with connectivity auditing
$ M2 O" k2 I0 I4 }3 u0 n1254578 SPIF OTHER Specctra crash with Error -1073741819 for Auto router
0 z1 Q& P* e3 Q' m8 u1254637 ALLEGRO_EDITOR DRC_TIMING_CHK adding nets to a net group causes constraint assignment error( R7 u" i8 n9 n' O. d
1254676 GRE IFP_INTERACTIVE Rake Lines disappear when Auto-Interactive Breakout is enabled.
$ F* I$ }2 P; ]8 @/ m( n3 X# N6 K1255067 SIG_INTEGRITY REPORTS Allegro hangs on Net Parasitc Report generation
- q1 i$ u0 v @ m& s1255267 ALLEGRO_EDITOR SKILL axlDBGetPropDictEntry does not return a list of all objects( i1 J, G1 u$ Z- k
1255383 SIP_LAYOUT IC_IO_EDITING cant move bumps or driver in app mode
$ @4 m# T. f5 ?' I; |1255703 ALLEGRO_EDITOR SKILL axlCNSSetPhysical and axlCNSGetPhysical return nil if a constraint set name is provided
$ E0 H0 d8 s9 L. [9 C) U1255759 ALLEGRO_EDITOR INTERFACES Change the silkscreen OUTLINE from layerFunction DOCUMENT to layerFunction BOARD_OUTLINE
+ }4 N* ]5 ^4 w4 P6 C1256457 CONCEPT_HDL CONSTRAINT_MGR Extracting a XNet from CM crashes the tool2 R: W6 T% H4 R" Y0 G4 r- U
1256597 GRE CORE Allegro GRE crashes while running Plan Spatial, on a particular design: [2 |! B* _6 K9 m$ Y& C
1256650 ASI_PI GUI PFE - Cannot generate model file error when using company decap library9 G$ }6 I( ?% K1 J2 J3 v( T+ ]3 u& ?. X
1256837 SIP_LAYOUT DIE_EDITOR Open and close of die editor takes too long
' i; S) r' A- S) M1257732 CONSTRAINT_MGR OTHER Bug - Export Analysis Results in CM makes Allegro crash/ c+ S) d& f' A# ?5 e/ Y( s n1 B# C2 A2 A
1257755 ALLEGRO_EDITOR OTHER Editing time in Display > Status seems to be logging wrong time
5 v b# H9 f3 ~* C1258029 APD WIREBOND The bondwire lost after import the wire information
3 X( K* D+ `; _6 d3 Z, u1258979 APD NC NC Drill: There is difference of number of drills.& P# e' [& X4 v6 Y' ]9 Q& Q* Q
1259484 SIP_LAYOUT OTHER SiP - calc min airgap calculate minimum airgap beta feature improvement, u: d0 U$ U4 J; u" g$ x
1259677 CONCEPT_HDL CORE hier_write -forcereset cause component prop change.
; S1 Z: f( n3 n) _( \# `, g- m1259913 ALLEGRO_EDITOR UI_FORMS Unable to save setting of "use secondary step models in 3D viewer"
! v% O. T* g* Z* r9 k: z3 ~5 Z4 Y" a1261758 ALLEGRO_EDITOR EDIT_ETCH Auto Interactive Delay tune (AiDT) is deleting clines
0 k1 F2 b) b) z5 v9 j% f: C1262543 ALLEGRO_EDITOR MANUFACT merge shape results in moved void
. [, K9 }* ~$ t5 i- H& j. @; E1264767 ALLEGRO_EDITOR DRC_TIMING_CHK XNET is choosing to resolve to a different name from 16.5 to 16.6 and is causing constraint loss' V: P3 y) O$ [4 L
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发表于 2014-4-26 15:14
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