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本帖最后由 dsws 于 2014-4-28 12:56 编辑
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链接: http://pan.baidu.com/s/1dD9XLPB 密码: ujuq7 @$ M8 x y; [1 D. ^+ N( x
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# ^: N6 ?) w3 H4 F9 Q9 ^; WDATE: 04-25-2014 HOTFIX VERSION: 027
' s; }) H5 ]. q* Z. F===================================================================================================================================3 }" B+ J; h( i+ X, S! b) W% ?
CCRID PRODUCT PRODUCTLEVEL2 TITLE/ L* L5 _# Y, b4 Y
===================================================================================================================================+ N7 j& W: J- R+ `4 X5 h3 E+ U$ T9 j
308701 CONSTRAINT_MGR OTHER Needs to delete user defined schedule in CM) p% y: R! E% G8 q- |4 w) g
481674 allegro_EDITOR pads_IN No board file saved from PADS_in5 d0 [8 a" l2 A. x
982929 ALLEGRO_EDITOR EDIT_ETCH can't route on NC pin and other that are not pin.0 F& F' c7 s5 l
1012783 FSP OTHER Need Undo Command in FSP
b, M4 k/ s. B% _1 P" \1017381 ALLEGRO_EDITOR DRC_CONSTR Need Dynamic Phase to be able to measure back to the Drive Pins.' A( g% B% \2 @' y# t# S
1072673 PCB_LIBRARIAN GRAPHICAL_EDITOR Copy paste goes offgrid if mouse is moved: p; r3 e% X; O! U# z$ B6 r
1073231 concept_HDL CORE Copy-paste of signal names goes off-grid in Windows mode.$ S d, U- \# Q( v9 J$ F
1105371 CONCEPT_HDL INTERFACE_DESIGN Strange behavior when shorting two Net groups
; h+ r i I1 V1116498 CIS LINK_DATABASE_PA link database with modified part results in Capture crash
8 z0 T# O ?, e- n3 q! F1118632 ALLEGRO_EDITOR GRAPHICS Text display refresh issue while in Edit > text command" `; G8 \- X+ A; t
1155821 SIG_INTEGRITY LIBRARY Xnet are not recalculated correctly when model is changed on the Series switch part defined as discrete with Espice mode; s3 a# B# L ~, X
1157372 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase for Diff Pairs not reporting back to Driver pin if pin escapes present4 G4 K9 r. d: k4 N# w. O
1171951 ALLEGRO_EDITOR CREATE_SYM Jumper has a limited of count when it add to list.
/ ?; N4 [ @. J' e3 l1180871 CAPTURE LIBRARY_EDITOR Copied parts don't retain pin name and pin number settings3 S6 y. T) z) K( W4 K
1185575 SIP_LAYOUT DIE_STACK_EDITOR Updating symbols causes the graphics for the Assy layer to change from Bottom to Top.
% U% v; j6 O# y2 U6 P1185772 PCB_LIBRARIAN CORE VALID_PACK_TYPE warning when cell was opened in PDV0 _$ L8 Z+ c6 U6 C1 A
1192377 CAPTURE SCHEMATIC_EDITOR Pin name/number position is incorrect on schematic if it is changed for a rotated part.
# E6 u" G/ k; b7 {5 | e! w1202654 ALLEGRO_EDITOR GRAPHICS Zoom using mouse wheel shall maintain the center co-ordinates6 r: b. L+ {2 a/ `6 [
1208031 ALLEGRO_EDITOR INTERACTIV Snap to Pin for via during Copy command do not snap to connect point everytime
3 T& P0 r, u* }6 P1208478 Pspice PROBE Attached project gives overflow error with marching ON.7 E s t U2 N ]2 y4 w8 ]
1210015 CONCEPT_HDL CORE The value of $PN should be not turned on spin or rotate symbol
/ d9 T5 [: T \- A- J5 Z1210425 CONCEPT_HDL CORE When moving a circuit tool reports that connectivity has changed9 o; j, r2 ]/ N6 l) Z) Y/ ?
1215858 ALLEGRO_EDITOR SHAPE Force update does not void cline with the shape% T( C$ e, E) l" L3 m g! p$ @8 `' W
1215906 ALLEGRO_EDITOR SHAPE Dynamic shape fill smooth failed when copying to other layers1 J: }( W% Y6 @! |9 A ?' F5 q
1216358 CONCEPT_HDL CORE Can we improve our export BOM function to check if user did export physical function before exporting BOM?2 P# n# b6 Q: ~. e, A
1217364 CONCEPT_HDL OTHER Netlist reports fail because error: GScald failed.; y* j* o/ S, y+ {6 ?; ~
1217529 CONCEPT_HDL CORE ADW checks do not catch single quotes in PTF values) f ^; |4 n2 ^( N; q8 |
1217556 F2B PACKAGERXL signal name change not sent to Allegro after packaging
$ D: `& p- l! a4 m! f# w1219283 ALLEGRO_EDITOR DRC_CONSTR Show constraint is inconsistent when displaying region information8 b* M. i N2 Q/ b- p3 \
1220078 F2B PACKAGERXL Export Physical crashes when ALL the part pins are added
" M E3 Z7 ^# b$ {" C) b1220393 CONSTRAINT_MGR CONCEPT_HDL HDL import physical from board file will annotate CM data back to HDL which includes cross-section thickness." W, q$ f3 ^! o* }/ I! d* d
1220540 ALLEGRO_EDITOR GRAPHICS Need an option to see the pads inside the internal plane shapes
5 R$ j+ P* T' R3 n7 o1220936 CONCEPT_HDL CORE About crash by vpadd/vpdelete command on Linux0 r2 w/ \& n4 `2 Y
1221059 ALLEGRO_EDITOR DRC_CONSTR Get a "Shape to Thru Via Spacing" DRC error only the first time when the shape is manually voided.3 o' p, a8 @% d# T) ]% M w
1221182 ADW TDA Team Design with SAMBA
7 ]% ]6 {1 K! m8 r0 {. x- R P1222442 CONSTRAINT_MGR UI_FORMS Duplicate pin pairs appear in DiffPair/ l* \0 K, z e9 o- n% I
1223175 CONCEPT_HDL CONSTRAINT_MGR Schematic crashes when opened% ?7 u7 Y8 V. M3 k4 u& p1 M
1223533 ALLEGRO_EDITOR GRAPHICS Why the through pins for STEP models are shown at an offset when viewed in 3D inside Package Symbol?
$ h. K. [, ?2 }- q% n6 Y: B' o1223680 CONSTRAINT_MGR ECS_APPLY Improve ECSet mapping by allowing user to address ambiguity of Parts* g) f& l2 J* p( {" V( M4 G+ f2 q
1224156 SIG_INTEGRITY SIGWAVE Exporting spreadsheet with filter Subitems in SigWave exports all waveforms
( J4 t- b& k! O8 P2 Z" x1224417 ALLEGRO_EDITOR PLOTTING Hidden font pattern is not showing correct in 16.5 version also 16.6 version.
9 [2 i6 X+ ?% y4 O1224704 F2B DESIGNVARI There is no lock for the variant.dat file - multiple users can open the editor" G& h/ C: W _; ]: S
1224968 ALLEGRO_EDITOR INTERACTIV Delete >(RMB click) Cut> Snap Pick to>off grid loction does not work for lines.# l5 J" O) \% n* l. S8 x
1224982 CONCEPT_HDL PDF commandline publishpdf does not work when there are spaces in the path
% I+ h2 R( F- P0 C$ w/ ^: Y1225114 CAPTURE GENERAL H-pins added after netgroup pin get color as of netgroup pin
. T3 v- s1 y7 i; p1225494 CAPTURE DRC Different DRC results for Entire design and selection$ K; G; \5 j# d
1226153 ALLEGRO_EDITOR INTERFACES Export STEP should include PART_NUMBER property
% x' [# j8 a. }3 x1 I, j/ ^8 l1226235 ALLEGRO_EDITOR EDIT_ETCH Enhancement to include Pin_delay of descrete forming Xnet j: }3 T( R( D4 E+ D
1226372 CAPTURE GENERATE_PART ENH: Functionality to add pin spacing in New Part From Spreadsheet
" S, ~% q/ {) c, _7 K5 |8 Z) d1226477 CONCEPT_HDL CORE DE HDL縮 `Allowed Global Shorts? function is inconvenient for Global Signal
: `+ K2 F, Y; ~3 k1226813 SIP_LAYOUT LEFDEF_IF ERROR SPMHLD-120 when importing a DEF file. Request to increase the number of characters/line in a .cml file7 r2 y0 v: b. n( r+ I9 a
1227453 ALLEGRO_EDITOR SHAPE Addition of Fillet generate Pin to Shape Spacing DRC errors and DBDOCTOR errors5 j7 z7 `- ?" w4 g
1227461 ALLEGRO_EDITOR SHAPE Sliding a cline for certain net changes the thermal relief connects for pins connected to another net from 4 to 5,6,7,8; h: e; e/ W9 e. J. U
1227469 CIS DBC_CFG_WIZARD Oracle Views not visible on Step2 of CIS Configuration/ f, W/ N! U* Z% \" Y/ y
1227780 CAPTURE ANNOTATE Inconsistent behaviour when annotating heterogeneous part0 c: F5 [1 [/ `
1227831 CONCEPT_HDL CORE Pin text and H-block name in upper case: m' A- f- D% N; E
1227954 CONCEPT_HDL OTHER supress check for global signals when wires are unconnected to pins
+ f% O0 P1 ]$ A/ u" Z1228190 ALLEGRO_EDITOR OTHER Unable to close the 'usage' window during license selection
4 \9 b5 I+ d, g" _7 g, q1228899 CONSTRAINT_MGR INTERACTIV Export/Import constraints in "overwrite" mode from same design shows different results when imported second time.
% r" c- S% |3 J" G7 j8 H# M! L1228934 ALLEGRO_EDITOR EDIT_ETCH The "View Active Layer" option like the Board Station should be provided for dynamic layer visibility.
3 n- |4 z2 A- y* [& Z, x' f' k5 Z2 O1229316 ALLEGRO_EDITOR EDIT_ETCH When routing with Hug only enabled we were able to route through other routes(sometimes Hug).
& a3 h6 Y5 O$ ~2 Y% w" e+ s1229545 CONSTRAINT_MGR OTHER Allegro indicate bundle scheduled nets in CM
, S: G- d7 u* N% E& a4 \2 ?" Z1230056 ALLEGRO_EDITOR GRAPHICS Bug: 3D View of Mechanical Symbol with the drill hole defined
/ ?, W1 i7 ?, d+ E7 x1230432 CONCEPT_HDL CORE No Description information in BOM$ \ \) m0 R6 o1 `# n& \
1231148 F2B DESIGNVARI The variant.dat file is not updated with library PTF changes8 M6 o! ^! y" ]: }- g) r
1231625 F2B DESIGNSYNC VDD at command line needs to support sch2sch and test variable to write out report files9 g; o7 Z5 c/ Z. i/ \
1231697 CONCEPT_HDL CORE If any locked files exist force a pop-up dialog restricting certain commands
6 f! ^: X* t0 q% H" `/ X: c K/ _1231767 CONCEPT_HDL OTHER Unable to find under the search options single bit vector nets
9 M5 A9 }! B2 L) }; x* G: m1231961 ALLEGRO_EDITOR SHAPE Shapes not updating to smooth unless we use force update and as a result false DRC's appear in board.
7 e8 B5 q4 f5 o4 V1232100 CONCEPT_HDL skill Unable to execute the SKILL commands in viewer mode! g; L- I* V6 h' e
1232336 CONSTRAINT_MGR CONCEPT_HDL cmFeedback takes 5hrs to complete during Import Physical; F3 q d* l3 H1 u. m; {0 \
1232710 F2B DESIGNVARI Dehdl crash while moving component in variant viewer mode. K0 }4 g& P0 T) y" l7 L
1233894 F2B PACKAGERXL The page data is missing in the pst* and PCB files
0 H9 `. @$ N: S/ t5 |- f1235785 CONCEPT_HDL CREFER cref_from_list custom text is not subsitituted in complex hierarchy7 H6 K( j7 F4 E2 w" R! _: g: [
1235928 CAPTURE SCHEMATIC_EDITOR OleObject modifications not saved
/ K. k+ K8 ]. v9 Q- a: W1236065 CAPTURE PART_EDITOR Mirrored part after being edited get pin name locations incorrect
9 O/ S5 D7 ?: ^9 z! H8 _2 f2 `1236071 ALLEGRO_EDITOR SHAPE Airgap for Octagonal Pads ignores DRC Value when Thermal set
# H' ]: e4 [; F; m0 _% {6 M- t* ]1236072 CONCEPT_HDL CORE Page 122 cannot be saved as logical page 119 has different page mapping in connectivity data and schematic. N/ m' d& a: ~9 X
1236161 CONCEPT_HDL CORE Import Design shows the current project pages/ k+ K0 |% z, e; u; A# {- f! i) y
1236432 ALLEGRO_EDITOR PADS_IN pads_in doesnot translate via and shape in some instances.+ A9 i7 e6 P, x9 v( c. R6 a" F! Y4 [# |
1236557 CONCEPT_HDL PDF Running Publish PDF on command line in linux doesn't output progress until completion
5 F# s0 O# a- a6 m% F2 @4 Q# r; U1236589 CONCEPT_HDL PDF Enhancement license failure error should appear in pdfpuplisher log file
o, T. I3 _9 D- e8 b3 I1236644 ALLEGRO_EDITOR EDIT_ETCH create fanout deletes shape6 o; h) f5 r% ^; C
1236689 ALLEGRO_EDITOR GRAPHICS Graphics displays extraneous lines when panning or zooming
* d- z# |7 e3 G6 R4 A: ?4 V0 n7 v1236781 F2B PACKAGERXL Export Physical produces empty files
/ i) S6 z7 q7 }! C$ I0 L4 R a1237331 PSPICE ENVIRONMENT pspice.exe <cir file name> - hangs when run) y+ s8 }+ N# D |/ U: o
1237400 CIS EXPLORER Capture hangs on 2 consecutive runs of `refresh symbol from lib? command
3 P( Y$ h+ I8 Z9 P1237437 CONCEPT_HDL CONSTRAINT_MGR CM Crash when saving after restore from definition& S6 _3 f/ p: O. z* n
1237862 CONSTRAINT_MGR OTHER A way to remove the RAVEL markers from the Constraint Manager.2 G3 z+ f5 d% m9 r
1238852 CAPTURE GENERAL signal list not updated for buses
8 Y. `% J# ^; m( A4 Q1 {1238856 FSP DE-HDL_SCHEMATIC FSP schematic generation crashes" K" L# y1 K! u% n3 l2 d
1239079 ALLEGRO_EDITOR INTERACTIV The 16.6 Padstack > Replace function leaves old padstack.
% V* l! `+ j5 I- ]# V; V1239706 CONSTRAINT_MGR ANALYSIS The reflection result on a differential signal in the CM when Measurement location is DIE3 e2 t- {+ B: C2 M
1239763 PSPICE PROBE Cannot modify text label if right y axis is active* ~2 n; {' ?' x7 r( p7 q
1240276 ALLEGRO_EDITOR GRAPHICS Printing to PDF from SigXp is giving unreadable images' c [( f0 c2 y# ~
1240356 CAPTURE IMPORT/EXPORT Can縯 import SDT schematic to Capture.
- {* l6 g8 a' I( j% }6 Z5 s# R5 `1240502 F2B PACKAGERXL Corrupt cfg_package does not stop PackagerXL from completing1 ]3 i' ~7 v& Y% a4 t
1240607 ALLEGRO_EDITOR OTHER Footprint of screw hole got shift in DXF file& j5 z( X6 K3 ^, i2 |7 _2 r( x
1240670 ALLEGRO_EDITOR PLACEMENT Select multiple parts and Rotate makes them immovable- h8 r+ i; x; ?6 |
1240773 CAPTURE DRC DRC check reports error for duplicate NetGroup Reference in complex hierarchy' Q8 q' x0 l8 D* |
1240845 SIG_EXPLORER EXTRACTTOP Narrowband via models for Mirrored BB Vias not extracted in in the interconn.iml and this gives bad ringing in waveforms6 N$ Q% Q' @! v S+ R
1241634 ALLEGRO_EDITOR OTHER Netshort for pad-pad connect not working" Q# f. Y6 q0 y F N' ^" k
1241776 CONCEPT_HDL CORE In hierarchal design not all pages are getting printed.
! _1 d& ~5 V d7 _+ ^2 x) I2 y" R1241788 CONSTRAINT_MGR CONCEPT_HDL Issues with changing focus in Constraint manager using keys on keyboard" O+ V: q# K& k( F- h) l6 A
1242683 ALLEGRO_EDITOR INTERACTIV Color View Save replaces file without warning+ j4 j$ [9 r& a- \8 J
1242818 ALLEGRO_EDITOR PLACEMENT Placement edit mirror option places component on wrong side
- M8 z8 @, G) z8 J2 [! n9 W1242847 ALLEGRO_EDITOR GRAPHICS Need an option to suppress Via Holes in 3D Viewer+ w4 N8 y6 w3 @3 A# K$ O2 a
1242923 ADW COMPONENT_BROWSE UCB reports Missing From DB only after selecting the Row in the search results7 F2 G% X) K8 T; H( [2 c3 s
1243609 CONCEPT_HDL CORE autoprop for occurrence properties
+ ]7 b4 Q% T1 p4 u3 a+ r R1243682 F2B DESIGNVARI after undocking variant icon cannot be redocked back to GUI2 O( o5 l" K$ Q: @( i) E* H
1243686 ALLEGRO_EDITOR GRAPHICS Invoking Edit->Text, the infinite cursor disappears until edit mode is changed.
$ @5 J( C+ N" q1243715 CAPTURE PART_EDITOR Pin name positioning get changed after rotating or mirroring
8 `$ C7 a/ _' U) G- c/ o P1244945 CONCEPT_HDL PDF PDF Publisher does not include image when file is not located in the root folder
; ^( R$ e. d! j1 C, w- a! _( _5 R1245568 CONCEPT_HDL CORE Dual unselect needed for wires attached to other net/source and property is not deselected when component is
4 d- t: C2 U: J4 t# {* x2 s+ Q% G% A3 c1245819 F2B PACKAGERXL wrong injected properties information passed during packaging of the design
2 L0 }/ {; {3 P% g& R1245916 SCM CONCEPT_IMPORT Where does the folder location reside for DEHDL imported blocks?. E! R2 q1 Y1 J& J% b
1246347 CONSTRAINT_MGR CONCEPT_HDL DEHDL crash if environment variable path has trailing backslash character
" T/ N5 T2 F8 e9 {/ u4 C3 b1246896 ALLEGRO_EDITOR DFA DFA_UPDATE on Linux reports err message if the path has Upper case characters
8 H2 Y3 m- A( [- B- P/ G1247019 SIP_LAYOUT DIE_STACK_EDITOR SiP Layout - refresh/update symbols is mirroring the assembly drawing data on DIE that is placed ChipDown: ?/ E* K. m+ `0 ?
1247037 CAPTURE LIBRARY_EDITOR Copy & Paste of library parts resets pin name and number
' U7 S# {* ?& E! V7 c1 ~1247089 CONCEPT_HDL CORE Group Align or Distribute > Left/Center/Right crashes DEHDL
|2 {' a4 \; _6 r1247163 CONCEPT_HDL PDF Physical Net Names in PDF not maintained
8 B% G# A0 P* D' |1247462 CONCEPT_HDL CORE Text issue while moving with bounding box
! F# h9 d9 q3 o7 F7 P6 T2 @1247464 ALLEGRO_EDITOR UI_FORMS When using the define B/B via UI the end layer dropdown arrow is partially covered
9 ^9 k9 Q( y- p! Q! b3 U+ p& u1249063 CONCEPT_HDL CONSTRAINT_MGR CM and SigXP doesn縯 respect PACK_IGNORE at components! f0 I* K8 I. }- i# P
1250270 CONCEPT_HDL CORE Part Manager Update places wrong parts+ Y Q; c4 U4 p4 c( J
1251206 ALLEGRO_EDITOR ARTWORK Aperture command cannot create appropriate aperture automatically from design. U* s) R( [& }
1251356 ALLEGRO_EDITOR INTERFACES Some STEP models are missing in 3D view of footprint, although all components have STEP model mapped in footprint. _1 G% U; U1 ]3 I; b. Z5 |. f
1251845 ALLEGRO_EDITOR EXTRACT Crosshatch arcs do not extract correctly
0 E% ?% r8 K! g' M/ |5 H1252143 APD OTHER When using the beta "shape to cline" command the tool is removing the shape instead of converting it.. e! B& Z u9 x" K
1252737 SIP_LAYOUT OTHER SiP Layout - Option to create shapes from Pins for WLP wafer level packaging technologies, E0 ]5 f1 Q) t* j$ Q8 H0 P
1253424 SCM SCHGEN Export Schematics Crashes System Architect2 Z( D1 Y* c* N8 ~ s5 Q
1253508 ALLEGRO_EDITOR INTERFACES Bug - Export IPC2581 exports Crosshatch shapes as filled7 n- Q5 d7 s; v: t% [* u
1253554 SIP_LAYOUT OTHER SiP Layout - Add Netlist Spreadsheet export to SiP layout to help with connectivity auditing
; n" z' D* @# v4 h: L8 @$ B1254578 SPIF OTHER Specctra crash with Error -1073741819 for Auto router
' G. o/ |- h, ~1254637 ALLEGRO_EDITOR DRC_TIMING_CHK adding nets to a net group causes constraint assignment error1 [0 C3 ]; a @. v' M2 N" \( C& T: _9 J
1254676 GRE IFP_INTERACTIVE Rake Lines disappear when Auto-Interactive Breakout is enabled., q. O) _1 N) q" D
1255067 SIG_INTEGRITY REPORTS Allegro hangs on Net Parasitc Report generation
% H) r' a4 Y/ e! ?) \2 m! q1255267 ALLEGRO_EDITOR SKILL axlDBGetPropDictEntry does not return a list of all objects P; ]% d: G% f6 C2 a% ]
1255383 SIP_LAYOUT IC_IO_EDITING cant move bumps or driver in app mode
: }; j# x2 K _ ~+ z+ E1255703 ALLEGRO_EDITOR SKILL axlCNSSetPhysical and axlCNSGetPhysical return nil if a constraint set name is provided6 n \$ l) Z7 m# o. e1 O0 W
1255759 ALLEGRO_EDITOR INTERFACES Change the silkscreen OUTLINE from layerFunction DOCUMENT to layerFunction BOARD_OUTLINE
8 z" a$ K2 ]" B- I1256457 CONCEPT_HDL CONSTRAINT_MGR Extracting a XNet from CM crashes the tool
" M: O1 U$ d2 C& D5 O6 m" ~1256597 GRE CORE Allegro GRE crashes while running Plan Spatial, on a particular design
: {) {" O$ V$ w$ H1256650 ASI_PI GUI PFE - Cannot generate model file error when using company decap library
0 m% ~4 i6 |+ a9 ^; I9 t2 r* Z1256837 SIP_LAYOUT DIE_EDITOR Open and close of die editor takes too long) a! `8 i3 l, ?7 K: u Q' A8 \3 i( J: G
1257732 CONSTRAINT_MGR OTHER Bug - Export Analysis Results in CM makes Allegro crash
8 W5 E( Q1 c6 P% q1257755 ALLEGRO_EDITOR OTHER Editing time in Display > Status seems to be logging wrong time
( l- N$ g4 m& E# b- r& [6 `1258029 APD WIREBOND The bondwire lost after import the wire information e! ^: g& g6 {
1258979 APD NC NC Drill: There is difference of number of drills.& S) u( @/ u* g+ ^, i) C
1259484 SIP_LAYOUT OTHER SiP - calc min airgap calculate minimum airgap beta feature improvement' w. l6 K7 S& q$ d) a/ R
1259677 CONCEPT_HDL CORE hier_write -forcereset cause component prop change.
6 z$ A" @- w" {9 `* T1259913 ALLEGRO_EDITOR UI_FORMS Unable to save setting of "use secondary step models in 3D viewer"
. _8 b8 a; l' x. L1261758 ALLEGRO_EDITOR EDIT_ETCH Auto Interactive Delay tune (AiDT) is deleting clines- j4 p4 |' Q2 c( Q M& r( M
1262543 ALLEGRO_EDITOR MANUFACT merge shape results in moved void. ^* b" p; l! ^% ^
1264767 ALLEGRO_EDITOR DRC_TIMING_CHK XNET is choosing to resolve to a different name from 16.5 to 16.6 and is causing constraint loss
9 k) [8 u9 Q. n. @' L, U) ~& v9 I5 o. c$ J2 W) W' W
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