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本帖最后由 dsws 于 2014-4-28 12:56 编辑
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链接: http://pan.baidu.com/s/1dD9XLPB 密码: ujuq# g+ r5 a( _; u% ], K% |9 q
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DATE: 04-25-2014 HOTFIX VERSION: 0271 b2 C. @% ]8 V& k* u& U
===================================================================================================================================
; K# l/ B, Y6 x& sCCRID PRODUCT PRODUCTLEVEL2 TITLE
5 Q9 v2 o7 a& O. j& i' F. Q: \===================================================================================================================================
) r4 [) q w; p% E# I( Z308701 CONSTRAINT_MGR OTHER Needs to delete user defined schedule in CM- y3 b8 ?/ K7 @! n
481674 allegro_EDITOR pads_IN No board file saved from PADS_in5 u; M7 h& E7 \" C, f% c8 f
982929 ALLEGRO_EDITOR EDIT_ETCH can't route on NC pin and other that are not pin.5 _1 M6 d5 I0 L- d% \
1012783 FSP OTHER Need Undo Command in FSP1 \3 H, Y- i4 V& s3 s. w3 l) q! B
1017381 ALLEGRO_EDITOR DRC_CONSTR Need Dynamic Phase to be able to measure back to the Drive Pins.
1 j3 K8 E' p- D, L4 d! Y1072673 PCB_LIBRARIAN GRAPHICAL_EDITOR Copy paste goes offgrid if mouse is moved' D" N3 f2 C! q$ V* z
1073231 concept_HDL CORE Copy-paste of signal names goes off-grid in Windows mode.) W5 ^" a$ ^, ?- ~, Q# t) N0 O, ]5 h
1105371 CONCEPT_HDL INTERFACE_DESIGN Strange behavior when shorting two Net groups
* V0 \4 G4 z* O* Q% I# }5 a' o1116498 CIS LINK_DATABASE_PA link database with modified part results in Capture crash/ h w( n1 q! s# X: q/ q5 |
1118632 ALLEGRO_EDITOR GRAPHICS Text display refresh issue while in Edit > text command/ F4 y: g9 \4 W" F0 R
1155821 SIG_INTEGRITY LIBRARY Xnet are not recalculated correctly when model is changed on the Series switch part defined as discrete with Espice mode, X* `2 E1 M/ Y' ]% f! Y4 Z0 g9 c4 T
1157372 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase for Diff Pairs not reporting back to Driver pin if pin escapes present
+ m- n. E8 w% E2 Y3 M5 I, N" g1171951 ALLEGRO_EDITOR CREATE_SYM Jumper has a limited of count when it add to list.& T: G# k! R! H4 e% |& B4 z
1180871 CAPTURE LIBRARY_EDITOR Copied parts don't retain pin name and pin number settings
6 ?4 R$ E0 l7 P+ F- O. [1185575 SIP_LAYOUT DIE_STACK_EDITOR Updating symbols causes the graphics for the Assy layer to change from Bottom to Top.
% J3 f9 n/ K# I) C9 O, V1185772 PCB_LIBRARIAN CORE VALID_PACK_TYPE warning when cell was opened in PDV) V9 O& N6 L0 t( I" e( ~7 j! w/ _
1192377 CAPTURE SCHEMATIC_EDITOR Pin name/number position is incorrect on schematic if it is changed for a rotated part.5 l* I$ D: f4 Y' @( N
1202654 ALLEGRO_EDITOR GRAPHICS Zoom using mouse wheel shall maintain the center co-ordinates
; }* x6 B! R5 t4 C- \1208031 ALLEGRO_EDITOR INTERACTIV Snap to Pin for via during Copy command do not snap to connect point everytime" k. l9 ], x+ |, h) r" o' i- `1 u1 t
1208478 Pspice PROBE Attached project gives overflow error with marching ON.( j5 G" j$ L, O4 j0 \$ H% D
1210015 CONCEPT_HDL CORE The value of $PN should be not turned on spin or rotate symbol; }7 i6 ?$ _, j4 Z! H P! h
1210425 CONCEPT_HDL CORE When moving a circuit tool reports that connectivity has changed
! r- ~ L. Z. Z; B, c0 V1215858 ALLEGRO_EDITOR SHAPE Force update does not void cline with the shape
( c4 K4 ~# ?9 a; m7 S2 Z8 R1215906 ALLEGRO_EDITOR SHAPE Dynamic shape fill smooth failed when copying to other layers
: ^: [! D" w9 H$ I) V6 M6 |1216358 CONCEPT_HDL CORE Can we improve our export BOM function to check if user did export physical function before exporting BOM?
" s" U! G2 T$ u6 @# T& [) n1217364 CONCEPT_HDL OTHER Netlist reports fail because error: GScald failed.
3 Z! M6 X2 q& b2 z' i& ]1217529 CONCEPT_HDL CORE ADW checks do not catch single quotes in PTF values
4 ~( c: p: e9 D. S# R9 o1217556 F2B PACKAGERXL signal name change not sent to Allegro after packaging
$ p/ ^3 U# Q+ X# R4 y1219283 ALLEGRO_EDITOR DRC_CONSTR Show constraint is inconsistent when displaying region information
' h7 M6 P+ Q; l- v1220078 F2B PACKAGERXL Export Physical crashes when ALL the part pins are added1 R' w) L0 j/ p' J6 T
1220393 CONSTRAINT_MGR CONCEPT_HDL HDL import physical from board file will annotate CM data back to HDL which includes cross-section thickness.
' @% A7 L t9 H6 t+ A0 |; b1220540 ALLEGRO_EDITOR GRAPHICS Need an option to see the pads inside the internal plane shapes
" Q) |, X$ t0 W: `/ X% I1220936 CONCEPT_HDL CORE About crash by vpadd/vpdelete command on Linux! ~ K3 A; N% U% H
1221059 ALLEGRO_EDITOR DRC_CONSTR Get a "Shape to Thru Via Spacing" DRC error only the first time when the shape is manually voided.
5 n( n' U( {( }- n/ G- h4 M6 ~8 v1221182 ADW TDA Team Design with SAMBA5 @4 n, n Z- I1 i# F7 U3 i: c6 x
1222442 CONSTRAINT_MGR UI_FORMS Duplicate pin pairs appear in DiffPair
6 S9 p5 R6 U; }) t1223175 CONCEPT_HDL CONSTRAINT_MGR Schematic crashes when opened% }+ r" F& h& z2 r; a V6 r
1223533 ALLEGRO_EDITOR GRAPHICS Why the through pins for STEP models are shown at an offset when viewed in 3D inside Package Symbol?7 K5 f$ @, l9 @8 L! U
1223680 CONSTRAINT_MGR ECS_APPLY Improve ECSet mapping by allowing user to address ambiguity of Parts
2 c. G& t4 z# Q) F5 o9 q7 s' K$ v1 F1224156 SIG_INTEGRITY SIGWAVE Exporting spreadsheet with filter Subitems in SigWave exports all waveforms7 J! h4 ?# a) v* Y
1224417 ALLEGRO_EDITOR PLOTTING Hidden font pattern is not showing correct in 16.5 version also 16.6 version.
' O; D, r$ i( G$ W; }1224704 F2B DESIGNVARI There is no lock for the variant.dat file - multiple users can open the editor
# z+ Y% L! O; k7 @/ \/ V1224968 ALLEGRO_EDITOR INTERACTIV Delete >(RMB click) Cut> Snap Pick to>off grid loction does not work for lines.
1 e; r) A( c% h5 y1 Y$ @4 ^1224982 CONCEPT_HDL PDF commandline publishpdf does not work when there are spaces in the path5 U' F, ?" ?% a( I8 T/ r$ ~/ n
1225114 CAPTURE GENERAL H-pins added after netgroup pin get color as of netgroup pin+ v+ R% Y+ X( z5 w6 L' P/ c) h- {& \' X
1225494 CAPTURE DRC Different DRC results for Entire design and selection
% U+ A5 N! ?% U) k6 z% t1226153 ALLEGRO_EDITOR INTERFACES Export STEP should include PART_NUMBER property9 B# ~+ j, ` w
1226235 ALLEGRO_EDITOR EDIT_ETCH Enhancement to include Pin_delay of descrete forming Xnet
- I5 Y& ]6 l' I, y0 d, S1226372 CAPTURE GENERATE_PART ENH: Functionality to add pin spacing in New Part From Spreadsheet
4 d) w+ W! h/ {& ~$ [7 {) H6 i1226477 CONCEPT_HDL CORE DE HDL縮 `Allowed Global Shorts? function is inconvenient for Global Signal a# B/ O) O6 J$ i
1226813 SIP_LAYOUT LEFDEF_IF ERROR SPMHLD-120 when importing a DEF file. Request to increase the number of characters/line in a .cml file
) C5 }; c5 S, q6 f. o. j' d1227453 ALLEGRO_EDITOR SHAPE Addition of Fillet generate Pin to Shape Spacing DRC errors and DBDOCTOR errors
; M7 j- `4 S0 R; k6 T+ T$ @1227461 ALLEGRO_EDITOR SHAPE Sliding a cline for certain net changes the thermal relief connects for pins connected to another net from 4 to 5,6,7,80 m1 m( z' X# U9 I% K7 K$ s$ `
1227469 CIS DBC_CFG_WIZARD Oracle Views not visible on Step2 of CIS Configuration
1 h4 t. I1 j |. v# y* Z5 O1227780 CAPTURE ANNOTATE Inconsistent behaviour when annotating heterogeneous part
! O) Q! X1 j; O* _4 j) b1227831 CONCEPT_HDL CORE Pin text and H-block name in upper case" @% }0 h, g2 w% C" a4 g
1227954 CONCEPT_HDL OTHER supress check for global signals when wires are unconnected to pins
4 Z- ]8 }1 q. [1228190 ALLEGRO_EDITOR OTHER Unable to close the 'usage' window during license selection
0 U `5 ]5 q# c- H1228899 CONSTRAINT_MGR INTERACTIV Export/Import constraints in "overwrite" mode from same design shows different results when imported second time.
% J1 J* D6 |( n e$ r; j8 [) Z$ H L1228934 ALLEGRO_EDITOR EDIT_ETCH The "View Active Layer" option like the Board Station should be provided for dynamic layer visibility.* u2 A5 M4 v2 I' n' Z) U
1229316 ALLEGRO_EDITOR EDIT_ETCH When routing with Hug only enabled we were able to route through other routes(sometimes Hug).
( I1 M/ f1 A2 F, S1229545 CONSTRAINT_MGR OTHER Allegro indicate bundle scheduled nets in CM$ a( u. W7 U- y$ l8 C% ~
1230056 ALLEGRO_EDITOR GRAPHICS Bug: 3D View of Mechanical Symbol with the drill hole defined7 q* h4 H+ H7 n6 r/ e
1230432 CONCEPT_HDL CORE No Description information in BOM7 o, E# A3 |. |' g5 j# @0 M
1231148 F2B DESIGNVARI The variant.dat file is not updated with library PTF changes
( g( Y, a/ M5 O; F" o1231625 F2B DESIGNSYNC VDD at command line needs to support sch2sch and test variable to write out report files: a7 e. |$ t; [) K
1231697 CONCEPT_HDL CORE If any locked files exist force a pop-up dialog restricting certain commands3 \0 o2 V. s; }+ p& r! s j0 J
1231767 CONCEPT_HDL OTHER Unable to find under the search options single bit vector nets- U$ C# q- w, N8 Z+ R& {& I6 k2 ~
1231961 ALLEGRO_EDITOR SHAPE Shapes not updating to smooth unless we use force update and as a result false DRC's appear in board.* s& [* x8 `/ N3 x
1232100 CONCEPT_HDL skill Unable to execute the SKILL commands in viewer mode; s( ?7 T# q& g1 X: p; O* s
1232336 CONSTRAINT_MGR CONCEPT_HDL cmFeedback takes 5hrs to complete during Import Physical& U; ^$ ?- M& ?7 D2 j: [. Q
1232710 F2B DESIGNVARI Dehdl crash while moving component in variant viewer mode; U' K, J0 e! l; `* v6 N2 Y( C/ k
1233894 F2B PACKAGERXL The page data is missing in the pst* and PCB files
* X) P" `- e- W c1235785 CONCEPT_HDL CREFER cref_from_list custom text is not subsitituted in complex hierarchy% ^( ]# p3 g5 m1 A9 D/ n2 k
1235928 CAPTURE SCHEMATIC_EDITOR OleObject modifications not saved$ y3 d8 e/ M% T1 F8 E: d2 C
1236065 CAPTURE PART_EDITOR Mirrored part after being edited get pin name locations incorrect5 O7 {+ ?2 b$ k9 r4 z- d5 i' d1 ]
1236071 ALLEGRO_EDITOR SHAPE Airgap for Octagonal Pads ignores DRC Value when Thermal set
& q* P6 |3 D1 x1236072 CONCEPT_HDL CORE Page 122 cannot be saved as logical page 119 has different page mapping in connectivity data and schematic
9 ]7 o- p+ y3 `2 x$ e1236161 CONCEPT_HDL CORE Import Design shows the current project pages1 ?" x) {- p4 x# s5 H8 p1 m
1236432 ALLEGRO_EDITOR PADS_IN pads_in doesnot translate via and shape in some instances.) J" L4 ]/ [# Y8 m, L# @6 y
1236557 CONCEPT_HDL PDF Running Publish PDF on command line in linux doesn't output progress until completion7 v+ g% U7 [) e- E- n: Z! {! k
1236589 CONCEPT_HDL PDF Enhancement license failure error should appear in pdfpuplisher log file& l7 C4 S: Z% X3 Y% ]; k C
1236644 ALLEGRO_EDITOR EDIT_ETCH create fanout deletes shape
; @* l* o- {' x0 t- a" w1236689 ALLEGRO_EDITOR GRAPHICS Graphics displays extraneous lines when panning or zooming7 q1 \ ]9 I* G4 D
1236781 F2B PACKAGERXL Export Physical produces empty files8 W6 a( \ Y8 o& M m! C( ?2 w p
1237331 PSPICE ENVIRONMENT pspice.exe <cir file name> - hangs when run
5 g! a! `6 X0 c# R) Y1237400 CIS EXPLORER Capture hangs on 2 consecutive runs of `refresh symbol from lib? command8 j% T6 C: T4 y- W- H% {! ^- |8 d
1237437 CONCEPT_HDL CONSTRAINT_MGR CM Crash when saving after restore from definition
/ _% H" n9 z a# G. b7 `' t% n1237862 CONSTRAINT_MGR OTHER A way to remove the RAVEL markers from the Constraint Manager." ?4 v8 K! y! w7 G
1238852 CAPTURE GENERAL signal list not updated for buses
& M- G) J* O8 c& q1238856 FSP DE-HDL_SCHEMATIC FSP schematic generation crashes
: n. t+ P6 D S, k" g$ [; j: X1239079 ALLEGRO_EDITOR INTERACTIV The 16.6 Padstack > Replace function leaves old padstack.
Y' Z/ E9 c6 Y7 |1 L1239706 CONSTRAINT_MGR ANALYSIS The reflection result on a differential signal in the CM when Measurement location is DIE
( X% F& F/ F& [/ l j" f8 m9 m7 \1239763 PSPICE PROBE Cannot modify text label if right y axis is active3 z/ h' k* b7 H
1240276 ALLEGRO_EDITOR GRAPHICS Printing to PDF from SigXp is giving unreadable images, l" T& ?4 E# G! k* V" S
1240356 CAPTURE IMPORT/EXPORT Can縯 import SDT schematic to Capture.& U+ v2 k; `! w; @2 q
1240502 F2B PACKAGERXL Corrupt cfg_package does not stop PackagerXL from completing2 t5 K0 K/ A6 Y' Z4 f: x; _3 Z
1240607 ALLEGRO_EDITOR OTHER Footprint of screw hole got shift in DXF file$ c- q! }' M+ B+ y+ r3 c: o* k' I
1240670 ALLEGRO_EDITOR PLACEMENT Select multiple parts and Rotate makes them immovable
& M1 P. `: d9 x, {! J: _1240773 CAPTURE DRC DRC check reports error for duplicate NetGroup Reference in complex hierarchy
+ t- v$ O, K" T! j. @' F, V1240845 SIG_EXPLORER EXTRACTTOP Narrowband via models for Mirrored BB Vias not extracted in in the interconn.iml and this gives bad ringing in waveforms
p% C7 T9 `/ T9 p! X) [1241634 ALLEGRO_EDITOR OTHER Netshort for pad-pad connect not working
" S1 i# C' {; P8 w4 u1241776 CONCEPT_HDL CORE In hierarchal design not all pages are getting printed.5 {/ o' c5 E: j0 a H. o# s( Q
1241788 CONSTRAINT_MGR CONCEPT_HDL Issues with changing focus in Constraint manager using keys on keyboard
( ~* y0 _; ]4 _8 v1242683 ALLEGRO_EDITOR INTERACTIV Color View Save replaces file without warning
+ p1 f0 ? D3 [$ X1242818 ALLEGRO_EDITOR PLACEMENT Placement edit mirror option places component on wrong side
" ^+ s/ N- {: }# H7 W( L1242847 ALLEGRO_EDITOR GRAPHICS Need an option to suppress Via Holes in 3D Viewer
d F- E3 \! M- A8 p" m) W1242923 ADW COMPONENT_BROWSE UCB reports Missing From DB only after selecting the Row in the search results( B0 c5 D& C1 L3 \' U
1243609 CONCEPT_HDL CORE autoprop for occurrence properties! n6 F/ R- E0 n: E5 V8 `& {
1243682 F2B DESIGNVARI after undocking variant icon cannot be redocked back to GUI# s5 c- Z5 k$ s* X% U
1243686 ALLEGRO_EDITOR GRAPHICS Invoking Edit->Text, the infinite cursor disappears until edit mode is changed.4 d' h: X0 E, D4 g {
1243715 CAPTURE PART_EDITOR Pin name positioning get changed after rotating or mirroring
9 P; L. l+ ]6 F0 g, m1 s1244945 CONCEPT_HDL PDF PDF Publisher does not include image when file is not located in the root folder
' ^4 v w3 A B* y8 }+ M1245568 CONCEPT_HDL CORE Dual unselect needed for wires attached to other net/source and property is not deselected when component is- f- M7 ] m) B
1245819 F2B PACKAGERXL wrong injected properties information passed during packaging of the design/ X! s* H7 }, c& U1 E- L
1245916 SCM CONCEPT_IMPORT Where does the folder location reside for DEHDL imported blocks?
' ]" V4 Y2 _+ a/ }1246347 CONSTRAINT_MGR CONCEPT_HDL DEHDL crash if environment variable path has trailing backslash character
; U' m) _4 G7 F. |* {1246896 ALLEGRO_EDITOR DFA DFA_UPDATE on Linux reports err message if the path has Upper case characters
) }# R/ _5 p# @. Z1247019 SIP_LAYOUT DIE_STACK_EDITOR SiP Layout - refresh/update symbols is mirroring the assembly drawing data on DIE that is placed ChipDown$ k8 |$ M) s. C7 Q
1247037 CAPTURE LIBRARY_EDITOR Copy & Paste of library parts resets pin name and number: C/ d, v! q5 S( `
1247089 CONCEPT_HDL CORE Group Align or Distribute > Left/Center/Right crashes DEHDL# N, a: h g7 \# I. u2 a
1247163 CONCEPT_HDL PDF Physical Net Names in PDF not maintained
5 z5 Y3 n) ?+ S# _1247462 CONCEPT_HDL CORE Text issue while moving with bounding box- s; C& G5 `8 d5 }0 w$ K
1247464 ALLEGRO_EDITOR UI_FORMS When using the define B/B via UI the end layer dropdown arrow is partially covered
. L) O6 c7 @+ A! a* [" o/ q: D1 s1249063 CONCEPT_HDL CONSTRAINT_MGR CM and SigXP doesn縯 respect PACK_IGNORE at components6 \6 i c; F( ^7 d$ q
1250270 CONCEPT_HDL CORE Part Manager Update places wrong parts) y0 ~- R( ^+ Q! X
1251206 ALLEGRO_EDITOR ARTWORK Aperture command cannot create appropriate aperture automatically from design.
* g1 M% r* j. C. P- W1251356 ALLEGRO_EDITOR INTERFACES Some STEP models are missing in 3D view of footprint, although all components have STEP model mapped in footprint
; w2 R% U+ h2 n! T( M1 W3 S. T1251845 ALLEGRO_EDITOR EXTRACT Crosshatch arcs do not extract correctly
& s g# E4 c4 c5 |% z9 [/ \( d" ^1252143 APD OTHER When using the beta "shape to cline" command the tool is removing the shape instead of converting it./ L$ c9 F- K. r+ g. a
1252737 SIP_LAYOUT OTHER SiP Layout - Option to create shapes from Pins for WLP wafer level packaging technologies
' q) D. \8 M/ d. }5 l) m1253424 SCM SCHGEN Export Schematics Crashes System Architect
9 N1 s x" I1 V) A. \( w. V1253508 ALLEGRO_EDITOR INTERFACES Bug - Export IPC2581 exports Crosshatch shapes as filled, x. J9 p3 M2 O8 {1 W& A5 E+ U( C
1253554 SIP_LAYOUT OTHER SiP Layout - Add Netlist Spreadsheet export to SiP layout to help with connectivity auditing
7 s$ d' t3 F! W( F1254578 SPIF OTHER Specctra crash with Error -1073741819 for Auto router
/ ^& X2 ^' `& ?! d+ [1254637 ALLEGRO_EDITOR DRC_TIMING_CHK adding nets to a net group causes constraint assignment error
/ ?9 j. ^& \" w) ?6 z1254676 GRE IFP_INTERACTIVE Rake Lines disappear when Auto-Interactive Breakout is enabled.
* P; a. ? @, \- o+ f1255067 SIG_INTEGRITY REPORTS Allegro hangs on Net Parasitc Report generation T6 i5 d. N- b: d( D
1255267 ALLEGRO_EDITOR SKILL axlDBGetPropDictEntry does not return a list of all objects1 v! _" p& E" J9 B7 } |+ Q
1255383 SIP_LAYOUT IC_IO_EDITING cant move bumps or driver in app mode4 k: l( B x/ I3 z7 B& K: L
1255703 ALLEGRO_EDITOR SKILL axlCNSSetPhysical and axlCNSGetPhysical return nil if a constraint set name is provided
}" J+ L7 h( ]' e4 F4 }* Y% v1255759 ALLEGRO_EDITOR INTERFACES Change the silkscreen OUTLINE from layerFunction DOCUMENT to layerFunction BOARD_OUTLINE! j6 S& G H7 ^7 Y+ k
1256457 CONCEPT_HDL CONSTRAINT_MGR Extracting a XNet from CM crashes the tool
: | ~, A1 {; B T8 D1256597 GRE CORE Allegro GRE crashes while running Plan Spatial, on a particular design
1 f* U" K& l/ e) P& h/ L6 Q1256650 ASI_PI GUI PFE - Cannot generate model file error when using company decap library2 F4 ?* O+ p( S% r5 @
1256837 SIP_LAYOUT DIE_EDITOR Open and close of die editor takes too long
. ?6 Z4 v" `: Y' d, D" D3 Q6 P1257732 CONSTRAINT_MGR OTHER Bug - Export Analysis Results in CM makes Allegro crash3 U0 q" C( v, t4 m; j
1257755 ALLEGRO_EDITOR OTHER Editing time in Display > Status seems to be logging wrong time! M0 O) ^. v: f0 L
1258029 APD WIREBOND The bondwire lost after import the wire information
; f+ ?( T! N- F/ I1258979 APD NC NC Drill: There is difference of number of drills.* |' |% h) C/ O9 e# n( Y; R. w
1259484 SIP_LAYOUT OTHER SiP - calc min airgap calculate minimum airgap beta feature improvement% d# i1 K- v2 _- Y9 V
1259677 CONCEPT_HDL CORE hier_write -forcereset cause component prop change.
( a7 a( [4 d0 [! g- o/ _. ~- ^1259913 ALLEGRO_EDITOR UI_FORMS Unable to save setting of "use secondary step models in 3D viewer"( a! j" Z3 Q* w3 A1 m
1261758 ALLEGRO_EDITOR EDIT_ETCH Auto Interactive Delay tune (AiDT) is deleting clines3 y& J/ ?! c+ q5 }
1262543 ALLEGRO_EDITOR MANUFACT merge shape results in moved void
) Z4 v$ A1 e4 o L g6 Y, H1264767 ALLEGRO_EDITOR DRC_TIMING_CHK XNET is choosing to resolve to a different name from 16.5 to 16.6 and is causing constraint loss% Z3 N8 @. D, O+ T f
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