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http://dl.vmall.com/c0fu1auqa8* E1 a& @0 f' g3 x1 |- f9 i
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DATE: 02-14-2014 HOTFIX VERSION: 023
) z9 v6 u& x" D2 ?8 a( Q===================================================================================================================================
+ H6 n1 s8 f* H9 r! O/ S1 iCCRID PRODUCT PRODUCTLEVEL2 TITLE: x+ L/ z4 S! w, Z5 K9 s: q
===================================================================================================================================7 D4 V9 Y; o- B( F
1120183 F2B DESIGNVARI Variant Editor Filter returns incorrect results.
" t# w* S. F& p% ?/ F/ ^" ?7 U1202715 SPIF OTHER Objects loose module group attribute after Specctra0 q/ K' q4 p2 Z" k1 L
1203443 ADW LRM LRM takes a long time to launch for the first time/ x0 ~3 q7 A6 Z6 b7 t
1207204 CONCEPT_HDL CORE schematic tool crashed during save all6 X! [" M7 e" ]+ Y1 A7 ^
1222101 CONCEPT_HDL CORE Pins are shorted on a block by the Block's title delimiter: N8 U0 v( a& }: s1 D6 Q$ @
1223709 FSP FPGA_SUPPORT Need FSP model of Altera 5AGZME3E3H29C4 FPGA0 A7 d2 E3 M- G, w/ ]3 V$ _/ d
1224025 ALLEGRO_EDITOR INTERFACES The 3D viewer when working on a brd file shows package placed on BOTTOM side of my board while it is present on TOP side
5 b1 G3 a1 S9 ?. }) S+ h @+ `1225591 F2B PACKAGERXL Aliased net signals starting with equals sign are not resolved correctly in cmgr9 b9 w* W9 w. w7 i8 |" h! X
1226480 ALLEGRO_EDITOR EDIT_ETCH Routing time is took to double increase when using the Add Connect because DRC is Allowed.
0 o$ k3 A5 x' [" X0 Y2 v+ D1229234 FLOWS PROJMGR Can't open the part table file from Project Setup
% o8 I1 h c: c1229555 ALLEGRO_EDITOR ARTWORK IPC-2581 not recognizing pin offsets correctly.3 u& }# G& |3 O
1229610 FSP FPGA_SUPPORT New FPGA device request - Altera Cyclone V ST: 5CSTFD6D5F31I7" ^* y2 d/ ~. \1 q
1229664 ALLEGRO_EDITOR SHAPE Shape not voiding different net pins causing shorts with no DRC's
- s( a# U8 C* }8 m# M3 n- ], d9 H1232601 ALLEGRO_EDITOR MANUFACT Cannot add test point to via on trace.3 F8 I V) u6 s
1232772 ALLEGRO_EDITOR DATABASE When applying a place replicate module Allegro crashes: d2 J# D( q9 V
1233216 SIP_LAYOUT DIE_ABSTRACT_IF Allow more than 2 decimal places for the shrink facor in the add codesign form. w3 T* E7 o& T0 l8 e. ?: y* O: l
1233690 PDN_ANALYSIS PCB_STATICIRDROP PDN IRDrop: Mesh mode in Report is incorrect.
. y- g) a' W4 X( h* s$ O1233977 ALLEGRO_EDITOR INTERFACES single shape copied and rotated fails to create when importing IDX
5 ^: J+ F1 ?6 d+ m6 X% S* K t- Z1234357 SIP_LAYOUT SCHEMATIC_FTB DSMAIN-335: Dia file(s) error has occurred." T/ E8 |: b! H( ^
1234450 ALLEGRO_EDITOR INTERFACES clines, pads, etch shapes to be at the same level with the board when viewed in STEP viewer.
& E! d. w- d+ O7 x+ x" b* i. k1235587 PSPICE MODELEDITOR PSpice Model Import Wizard does not display symbol graphics for DE-HDL Symbol
+ r7 m+ [+ v! l3 L8 W- t1236571 ALLEGRO_EDITOR GRAPHICS Allegro display lock up and panning issues8 w4 \3 }/ |8 z( {/ o4 u3 Z8 i5 U
1237415 ALLEGRO_EDITOR INTERFACES Multidrill pad is exported with single Drill in the STEP File
0 K/ r# K' u; y& Q& G) V5 m3 t1237807 ALLEGRO_EDITOR SCHEM_FTB The line feed code of netview.dat |
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发表于 2014-2-18 16:44
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