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http://dl.vmall.com/c0fu1auqa80 v$ S* @! V9 f8 ?
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DATE: 02-14-2014 HOTFIX VERSION: 023
" X, l/ F: y. f===================================================================================================================================
8 ` ^8 E7 k2 MCCRID PRODUCT PRODUCTLEVEL2 TITLE
' I1 ]. J# h0 r- W===================================================================================================================================2 u) P- w; y4 B7 o* ^- F
1120183 F2B DESIGNVARI Variant Editor Filter returns incorrect results. i: K9 S8 A$ ]3 y, Z. e
1202715 SPIF OTHER Objects loose module group attribute after Specctra+ f, a4 G: h9 Y) J$ `4 y) x
1203443 ADW LRM LRM takes a long time to launch for the first time$ E1 x# c9 S+ K; U5 c
1207204 CONCEPT_HDL CORE schematic tool crashed during save all+ O. C1 ]3 R' g f) Q
1222101 CONCEPT_HDL CORE Pins are shorted on a block by the Block's title delimiter+ ]% }: M, A8 G s
1223709 FSP FPGA_SUPPORT Need FSP model of Altera 5AGZME3E3H29C4 FPGA. E& t+ F5 R7 Q( C
1224025 ALLEGRO_EDITOR INTERFACES The 3D viewer when working on a brd file shows package placed on BOTTOM side of my board while it is present on TOP side
$ i) L. {+ n0 ?# G5 p1225591 F2B PACKAGERXL Aliased net signals starting with equals sign are not resolved correctly in cmgr& A; ]5 w& ~; Q% W. m
1226480 ALLEGRO_EDITOR EDIT_ETCH Routing time is took to double increase when using the Add Connect because DRC is Allowed.
) P( K3 @2 R) y, k: O2 t1229234 FLOWS PROJMGR Can't open the part table file from Project Setup
8 S8 V+ o+ ]2 s; p7 Q1229555 ALLEGRO_EDITOR ARTWORK IPC-2581 not recognizing pin offsets correctly.3 W$ }2 A3 @! P4 I2 z9 y* {
1229610 FSP FPGA_SUPPORT New FPGA device request - Altera Cyclone V ST: 5CSTFD6D5F31I7& c1 P6 A( {) m- X, ~
1229664 ALLEGRO_EDITOR SHAPE Shape not voiding different net pins causing shorts with no DRC's
* z% f/ S" S+ a6 z6 N1232601 ALLEGRO_EDITOR MANUFACT Cannot add test point to via on trace.
8 z5 X- }8 W$ p$ B: q! S1232772 ALLEGRO_EDITOR DATABASE When applying a place replicate module Allegro crashes" H/ G" @+ F0 b: c
1233216 SIP_LAYOUT DIE_ABSTRACT_IF Allow more than 2 decimal places for the shrink facor in the add codesign form
5 {5 A' B4 ^8 t2 Q, Y7 p; z1233690 PDN_ANALYSIS PCB_STATICIRDROP PDN IRDrop: Mesh mode in Report is incorrect.! O/ x$ [% d {8 @0 A9 L
1233977 ALLEGRO_EDITOR INTERFACES single shape copied and rotated fails to create when importing IDX
0 @9 R: @8 }% c& y6 F1234357 SIP_LAYOUT SCHEMATIC_FTB DSMAIN-335: Dia file(s) error has occurred. G- j* g+ ^( M, X6 m: J
1234450 ALLEGRO_EDITOR INTERFACES clines, pads, etch shapes to be at the same level with the board when viewed in STEP viewer.2 s/ f$ r4 K0 W
1235587 PSPICE MODELEDITOR PSpice Model Import Wizard does not display symbol graphics for DE-HDL Symbol4 ~* o+ Y. S0 S+ N, I) }5 }
1236571 ALLEGRO_EDITOR GRAPHICS Allegro display lock up and panning issues$ S! V- B. q6 H* `" x
1237415 ALLEGRO_EDITOR INTERFACES Multidrill pad is exported with single Drill in the STEP File5 }: j$ O0 P6 T2 u1 y
1237807 ALLEGRO_EDITOR SCHEM_FTB The line feed code of netview.dat |
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发表于 2014-2-18 16:44
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