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http://dl.vmall.com/c0fu1auqa80 r: x, @$ v6 d$ O9 p( g
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DATE: 02-14-2014 HOTFIX VERSION: 023
1 g5 C* w3 E+ e8 b===================================================================================================================================
: Z. ?+ }, x9 ~! Q# ]4 `9 }CCRID PRODUCT PRODUCTLEVEL2 TITLE
7 n+ i+ n# Q6 x, e; s===================================================================================================================================
( l. D! W! p3 G3 l0 A1120183 F2B DESIGNVARI Variant Editor Filter returns incorrect results.
" F/ u2 K% M9 }* _% y1202715 SPIF OTHER Objects loose module group attribute after Specctra2 i6 B3 B# }4 F# P) R
1203443 ADW LRM LRM takes a long time to launch for the first time
6 m* y. Y) k+ X t. G5 \: U1207204 CONCEPT_HDL CORE schematic tool crashed during save all
3 z9 C" Y( N' U0 F7 N5 {1222101 CONCEPT_HDL CORE Pins are shorted on a block by the Block's title delimiter0 E; W# F8 f3 a: C
1223709 FSP FPGA_SUPPORT Need FSP model of Altera 5AGZME3E3H29C4 FPGA
8 B, q! U7 J; r6 _- Q1224025 ALLEGRO_EDITOR INTERFACES The 3D viewer when working on a brd file shows package placed on BOTTOM side of my board while it is present on TOP side
+ F; b& M5 D& g4 n: B1225591 F2B PACKAGERXL Aliased net signals starting with equals sign are not resolved correctly in cmgr* ^. d4 T. |1 [5 H" f8 V+ u* Y i; z9 C
1226480 ALLEGRO_EDITOR EDIT_ETCH Routing time is took to double increase when using the Add Connect because DRC is Allowed.
# L) x( H/ b2 S& Q2 }9 i' C( j1229234 FLOWS PROJMGR Can't open the part table file from Project Setup
3 j2 f8 Q" B9 `1229555 ALLEGRO_EDITOR ARTWORK IPC-2581 not recognizing pin offsets correctly.
- H& i0 g( O8 h7 h1229610 FSP FPGA_SUPPORT New FPGA device request - Altera Cyclone V ST: 5CSTFD6D5F31I7% d, O- w: A8 j7 v+ _: O7 o
1229664 ALLEGRO_EDITOR SHAPE Shape not voiding different net pins causing shorts with no DRC's5 N' p/ S5 ^: w
1232601 ALLEGRO_EDITOR MANUFACT Cannot add test point to via on trace.
$ e: _* e5 L% t1232772 ALLEGRO_EDITOR DATABASE When applying a place replicate module Allegro crashes
2 }8 D# Q' ^. K+ O1 k+ J' g Z1233216 SIP_LAYOUT DIE_ABSTRACT_IF Allow more than 2 decimal places for the shrink facor in the add codesign form
1 J* A# Y" k4 m% D7 V# g1233690 PDN_ANALYSIS PCB_STATICIRDROP PDN IRDrop: Mesh mode in Report is incorrect.
% m C0 Y' o$ K4 Z( w1 O# i6 }1233977 ALLEGRO_EDITOR INTERFACES single shape copied and rotated fails to create when importing IDX) z/ E! S8 k: w: j2 K- _1 }/ o- }9 t
1234357 SIP_LAYOUT SCHEMATIC_FTB DSMAIN-335: Dia file(s) error has occurred.
1 _$ h. Y1 u* J8 ]% \1234450 ALLEGRO_EDITOR INTERFACES clines, pads, etch shapes to be at the same level with the board when viewed in STEP viewer.
. ]* V( J( G% J) {1235587 PSPICE MODELEDITOR PSpice Model Import Wizard does not display symbol graphics for DE-HDL Symbol5 n- V- b# B6 }8 t; \, {6 f
1236571 ALLEGRO_EDITOR GRAPHICS Allegro display lock up and panning issues, I% I: o2 H+ x
1237415 ALLEGRO_EDITOR INTERFACES Multidrill pad is exported with single Drill in the STEP File3 ?' P' |/ c6 Z- E) _' T
1237807 ALLEGRO_EDITOR SCHEM_FTB The line feed code of netview.dat |
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发表于 2014-2-18 16:44
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