|
|
http://dl.vmall.com/c0fu1auqa8+ v( [9 a5 o/ V B6 ?8 R
; s6 f+ @1 _; t. H8 v/ Q L( R: \
, u" {# b' g5 c B) w/ k! b( O6 U/ H
DATE: 02-14-2014 HOTFIX VERSION: 023
}6 V. g- C6 S===================================================================================================================================0 [8 T( R0 X8 `& i
CCRID PRODUCT PRODUCTLEVEL2 TITLE
& t; `. ~+ o, u: k* f/ t4 j5 y===================================================================================================================================
/ m, ]+ b* `1 U% i1120183 F2B DESIGNVARI Variant Editor Filter returns incorrect results.2 m. ^, n7 }6 m
1202715 SPIF OTHER Objects loose module group attribute after Specctra
9 }# Y3 P' E3 P5 H% X1 I: f1203443 ADW LRM LRM takes a long time to launch for the first time
: W, h4 k" T5 B: W' K: M& s+ Q% f1207204 CONCEPT_HDL CORE schematic tool crashed during save all
; O! H* f, C0 i, ~! f; z, H1222101 CONCEPT_HDL CORE Pins are shorted on a block by the Block's title delimiter
2 q% f& v b" j1223709 FSP FPGA_SUPPORT Need FSP model of Altera 5AGZME3E3H29C4 FPGA3 F C% t2 _% @! G3 T, }( a/ A# ^
1224025 ALLEGRO_EDITOR INTERFACES The 3D viewer when working on a brd file shows package placed on BOTTOM side of my board while it is present on TOP side5 b7 s6 M# I' d# ?4 n# j
1225591 F2B PACKAGERXL Aliased net signals starting with equals sign are not resolved correctly in cmgr
8 S: N( J' J8 ^1226480 ALLEGRO_EDITOR EDIT_ETCH Routing time is took to double increase when using the Add Connect because DRC is Allowed.: V) c. o: ?' `
1229234 FLOWS PROJMGR Can't open the part table file from Project Setup5 [4 q7 Y8 U N
1229555 ALLEGRO_EDITOR ARTWORK IPC-2581 not recognizing pin offsets correctly.
4 ~3 S, S4 r% x2 ?0 N! j" e/ b- e6 U1229610 FSP FPGA_SUPPORT New FPGA device request - Altera Cyclone V ST: 5CSTFD6D5F31I7
4 H+ f: r& W. _6 ^3 {1 G) t# Y1229664 ALLEGRO_EDITOR SHAPE Shape not voiding different net pins causing shorts with no DRC's
: h/ n& v* W" v1232601 ALLEGRO_EDITOR MANUFACT Cannot add test point to via on trace.
$ J/ I+ F2 j+ f' q) K7 F1232772 ALLEGRO_EDITOR DATABASE When applying a place replicate module Allegro crashes
3 P6 k9 K4 T& M) C$ e+ }1233216 SIP_LAYOUT DIE_ABSTRACT_IF Allow more than 2 decimal places for the shrink facor in the add codesign form9 i1 x8 E; c3 k% S. ^0 D" Y
1233690 PDN_ANALYSIS PCB_STATICIRDROP PDN IRDrop: Mesh mode in Report is incorrect.
a3 e Z" Y. V' u0 c# a" ~* R% W1233977 ALLEGRO_EDITOR INTERFACES single shape copied and rotated fails to create when importing IDX' U$ Q5 @6 E! i# t. T
1234357 SIP_LAYOUT SCHEMATIC_FTB DSMAIN-335: Dia file(s) error has occurred.# B, g, C! a8 c: J: U( W" G
1234450 ALLEGRO_EDITOR INTERFACES clines, pads, etch shapes to be at the same level with the board when viewed in STEP viewer.. B# X7 O$ |+ o- ~ U4 q
1235587 PSPICE MODELEDITOR PSpice Model Import Wizard does not display symbol graphics for DE-HDL Symbol
8 M2 Z4 {( l$ l t; s- N1236571 ALLEGRO_EDITOR GRAPHICS Allegro display lock up and panning issues
& h7 E' ]6 q3 Y" ? l6 k1237415 ALLEGRO_EDITOR INTERFACES Multidrill pad is exported with single Drill in the STEP File
, G. `9 i4 X& m, ]) I4 D3 o8 ?1237807 ALLEGRO_EDITOR SCHEM_FTB The line feed code of netview.dat |
|
/1 
发表于 2014-2-18 16:44
收藏
淘帖
支持！
反对！
楼主
