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http://dl.vmall.com/c0fu1auqa8
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% O7 m/ u9 |5 X: MDATE: 02-14-2014 HOTFIX VERSION: 023
- P: H* s/ m# U: Y8 ~& x$ D$ R===================================================================================================================================
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===================================================================================================================================
7 ~' T" V+ }5 ?' B7 Q1120183 F2B DESIGNVARI Variant Editor Filter returns incorrect results.7 g) |% i7 ~- A# `% m" x0 I% r
1202715 SPIF OTHER Objects loose module group attribute after Specctra
' P5 T7 }2 [8 |! n8 c B) N; q) N. R1203443 ADW LRM LRM takes a long time to launch for the first time T, [' P& ?3 G9 q3 P9 G) D5 }. y
1207204 CONCEPT_HDL CORE schematic tool crashed during save all$ r9 o0 ?3 N3 {, S
1222101 CONCEPT_HDL CORE Pins are shorted on a block by the Block's title delimiter
" H, w3 u, D$ M: h3 v( v) p1223709 FSP FPGA_SUPPORT Need FSP model of Altera 5AGZME3E3H29C4 FPGA
, X1 t! I! p- D& z8 N' R4 ^1 R/ B& I1224025 ALLEGRO_EDITOR INTERFACES The 3D viewer when working on a brd file shows package placed on BOTTOM side of my board while it is present on TOP side" m' M& h7 D3 W3 Y% t- _
1225591 F2B PACKAGERXL Aliased net signals starting with equals sign are not resolved correctly in cmgr# U" R2 k# { H4 {( }0 G
1226480 ALLEGRO_EDITOR EDIT_ETCH Routing time is took to double increase when using the Add Connect because DRC is Allowed.
% n u2 f# n7 o% R1229234 FLOWS PROJMGR Can't open the part table file from Project Setup
& v$ |( O2 q- k) g( `% B, `1229555 ALLEGRO_EDITOR ARTWORK IPC-2581 not recognizing pin offsets correctly.- S# { Z4 N _. V
1229610 FSP FPGA_SUPPORT New FPGA device request - Altera Cyclone V ST: 5CSTFD6D5F31I71 ~- s5 ` f' y k# j! b
1229664 ALLEGRO_EDITOR SHAPE Shape not voiding different net pins causing shorts with no DRC's0 h% l$ o. l% Y9 M$ K9 J3 V
1232601 ALLEGRO_EDITOR MANUFACT Cannot add test point to via on trace.
& F) U- r. K0 H \9 N& f1232772 ALLEGRO_EDITOR DATABASE When applying a place replicate module Allegro crashes
3 m6 T" C5 S2 }: D3 i5 I1233216 SIP_LAYOUT DIE_ABSTRACT_IF Allow more than 2 decimal places for the shrink facor in the add codesign form8 Q1 u( }/ `3 v2 b0 M2 c& o
1233690 PDN_ANALYSIS PCB_STATICIRDROP PDN IRDrop: Mesh mode in Report is incorrect.7 g& d0 k) v8 v- Y u# K
1233977 ALLEGRO_EDITOR INTERFACES single shape copied and rotated fails to create when importing IDX
: A: R0 C' l: _% K- l" K+ D5 F1234357 SIP_LAYOUT SCHEMATIC_FTB DSMAIN-335: Dia file(s) error has occurred.
8 k5 W3 @4 e1 O1234450 ALLEGRO_EDITOR INTERFACES clines, pads, etch shapes to be at the same level with the board when viewed in STEP viewer.6 B" _! B& X) l6 I6 W4 M
1235587 PSPICE MODELEDITOR PSpice Model Import Wizard does not display symbol graphics for DE-HDL Symbol2 C1 {1 L" q: l4 E1 h% F9 m/ x( D8 Q
1236571 ALLEGRO_EDITOR GRAPHICS Allegro display lock up and panning issues
2 }3 v* _. I! O1 i7 a b& z9 e R1237415 ALLEGRO_EDITOR INTERFACES Multidrill pad is exported with single Drill in the STEP File1 N. A7 B$ G- C. f9 N4 A
1237807 ALLEGRO_EDITOR SCHEM_FTB The line feed code of netview.dat |
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发表于 2014-2-18 16:44
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