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reg state;
( u# \6 D6 E8 Z, l7 D0 y. zassign sram_cs = 1'b0;
) Z+ ?: } k8 W: v8 Xassign sram_data =we?8'hz:wirte_data;; U5 {: m v+ X @
always @(posedge clk or negedge rst)
! y$ m) x8 N( F% J. ^0 hif(!rst) R. o& v- C' {" O
clk <= 1'b1;3 k9 }7 v) i+ n7 D
else8 i* z( y. m8 M. h8 H4 h( K* T
state <= ~state;
, T1 g1 t- L8 ~6 d" H) V: l, Y1 ]0 x* `3 Y' \9 A
always @(posedge clk or negedge rst)0 [. ^ i9 Q* L
if(!rst)
; \. x5 i+ P2 Z begin
) |- ]- i* k& \ end
+ [$ e1 q5 C( ^$ _' telse
, o L! y+ m% v( j begin
& x2 Q* ~; t W: M4 I if(state ) //读,- r: O1 T+ ~" d- D! X
begin) P' \: n9 \2 D
sram_addr <= read_addr;
. K0 x6 N$ G& x$ q( e- | sram_we <= 1'b1;3 O1 W* O5 K- w% H
sram_oe <= 1'b1;3 s5 J" H8 m$ V8 g1 O
end
9 J2 x! v. x f. Z& T else
2 ^/ O. k4 g# m/ x% M) D begin //写; h2 |- G. i t: |& L+ U
read_data <=sram_data
' k% t$ I0 \. V; O3 e. A$ g sram_addr <= write_addr;2 Y2 O I2 e3 k! ?$ I
write_data <= video_data;
r6 w- ?) W- r* {3 H3 i sram_we <= 1'b0;
4 L+ v1 J. c2 a* @5 i9 K" X; a2 }; C* J sram_oe <= 1'b0;5 x4 y- V1 M7 G7 d6 |3 D
end
+ Y3 S2 B% e! e8 W end
# L _4 m. i8 ~. Y i1 s
: q* @ b+ |! w3 D* I2 x: Z
& D* p9 ` \# z4 @- Y+ \
1 C! p% `* a# s. k$ r( L
% n4 q0 X* c( l1 {endmodule |
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