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我的还是不行呢,好多的帖子都试过了,一直出现
, `. W2 V: d2 J' p3 L. sTranslating E:/SPB16.3/Allegro/temp/project/S713OBX_SUBFPC/11.asc.
, ^6 e( `, V6 E7 E6 z, \) WUsing translator version @(#)$CDS: pads_in.exe v16-3-85D 11/3/2009 Copyr 2009 CADENCE DESIGN SYSTEMS.- _( R/ @5 B4 Z9 s D
Reading PADS ASCII file header.1 _; M! n4 j9 p( ~
Version = PowerPCB4.02 D( b i1 X* e" w. Y* w
Route Layers = 2
" K$ d8 x B( ` Units = METRIC, f/ s. F2 K* I* t; q1 R
Hatch mode = Vertical / Horizontal
) o0 A7 L7 Y1 ^; H- l7 ]! i Hatch grid = 0.100000, angle = 0.000000, anti-pad spacing = 0.000008
! ~1 T P2 k, ]: {* S' u" `Initializing new database.. E& P4 F0 G9 u/ T7 ?& T2 N
Creating layers.5 V6 d: z9 j; D. [
Reading PADS ASCII file body./ C4 K, {& \4 R) W, ^1 W
*MISC*
( x) z4 g" @; q, Z3 |/ L& d' B! | *MISC*1 `# f$ |3 y( E" D
Information: CSet 1_5_6 renamed to DEFAULT
) }. n4 l" Z6 U" n& |+ @/ d: ]) r* A. O2 ^8 v/ |1 V
Warning: Allegro doesn't support default electrical CSets.2 h" c4 s/ U9 ]
*MISC*
2 J" }6 w% v5 D+ R+ U6 c$ h *MISC*
0 ]# Q! ^ o" C. o *MISC*
; g) G6 ?& G* I" S9 ILZ帮忙看一下什么问题呢? |
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