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我的还是不行呢,好多的帖子都试过了,一直出现' W# g% d% ~( ]7 Y: y
Translating E:/SPB16.3/Allegro/temp/project/S713OBX_SUBFPC/11.asc., x( ?/ E }* b- y. s% P+ e
Using translator version @(#)$CDS: pads_in.exe v16-3-85D 11/3/2009 Copyr 2009 CADENCE DESIGN SYSTEMS.3 S; i ~0 `. O- n% h; Z
Reading PADS ASCII file header.& L2 W$ }2 Z9 @0 j4 r# q& j6 n
Version = PowerPCB4.0, O+ ]5 t( y, J6 }
Route Layers = 2
$ y/ O7 Q: N* Y, k6 \ Units = METRIC
9 t+ G; h6 }2 G; b% o* Y1 [ Hatch mode = Vertical / Horizontal$ i1 e1 g1 C7 L
Hatch grid = 0.100000, angle = 0.000000, anti-pad spacing = 0.000008. s* n4 k. K1 s
Initializing new database.
% r2 e+ }# p& A$ v- x/ ~. C Creating layers.0 k% B, j, q* \; H; f+ { w' E" i
Reading PADS ASCII file body.( e% B! m; s4 K( T+ O% y
*MISC*
& s% H/ v- q' F2 U6 S+ r% z% t *MISC*
1 T. `5 q& P% @Information: CSet 1_5_6 renamed to DEFAULT4 {! Y$ n# K7 d0 r( |; d3 G2 @% M
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Warning: Allegro doesn't support default electrical CSets.
3 |6 c8 {7 _) G/ A *MISC*7 K! {6 `& M# _* M8 {9 [4 L5 ~% g
*MISC*
" Z0 e6 E0 Q" u j; H+ Z *MISC*
: Z- g7 c7 m5 Z @2 RLZ帮忙看一下什么问题呢? |
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