剧透：DesignCon2013的获奖论文

stupid

1. A reusable generic platform for validation and characterization of high speed mixed signal designs
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9 j$ A. J4 Z' G( p$ j* ]  m; }2. A rapid prototyping of FPGA-Based duobinary transmitter/receiver for high speed electrical backplane transmission
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/ f$ }! p7 y, G  p' }. I, \" T, K% U3. channel to channel crosstalk behavior and design optimization for ddr4 memory buses
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4. signal and power integrity(SPI) co-analysis for high speed communication channels
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6 L  i5 g8 R0 d5. innovative PDN design guidelines for practical high-layer-count pcbs
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6. Time domain and statistical model development,correlation,and analysis methods for high speed SerDes
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% _. g6 u- F# R9 N) `" Q7. applying microwave techiques to digital systems: a simple case study

8. high throughput,hign-sensitivity measurement of power supply-induced bounded,uncorrelated jitter in time,frequency,and statistical domains
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9. beyond 25Gbps:a study of NRZ and multi-level modulation in alternative backplane architectures
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! t- k8 s- O, I  [10. Memory inteRFace on-chip PDN noise Charachterization,modeling and its impact on timing
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* w- @9 e  P, I. i) r: I5 |11. Enabling DFT logic and timing verification in mixed signal designs

( W* `2 _3 C/ l. `12. analytic solutions for periodically loaded transmission line modeling
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6 H$ Z6 G) l0 F0 Y# m* S13. power-signal co-integrity design for multi-Gbps low-power DDR3 mobile platforms

14. power/Ground bump optimization technique on early design stage

1 j- r! s: E" y  Z/ k3 n! ]15. DDR memory channel design from passive stub eqalizer perspective
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2 U5 z! g* {. P9 `16. using power aware IBIS v5.0 behavioral IO models to simulate simultaneous Switching Noise

- H/ w# C, t1 f5 o4 }: ?17. validating EMC simulation by measurement in  reverberation chamber

1 ~# v/ @" L* A! ?18. 3D interposer design and electrical performance study
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19. Dramatic noise reduction using guard traces with optimized shorting vias
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20. effects of ground via asymmetry on mode conversion for high speed differential signals
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21. design and analysis of a high-speed parallel interface for coded differential signaling
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$ M2 c2 [0 W5 j' r; w2 F% N22. measurement-based simulation:increasing IBIS-AMI model Accuracy with Data from lab measurements
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3 a' T3 U  x& b- H6 P23. accurate receiver clock positioning in high speed parallel buses

% [$ |. g" d9 o, v& g& S9 }; @24. partial response and noise predictive maximum likelihood(PRML/NPML) Equalization and Detection for high speed serial link systems

25. Which one is better?comparing options to describe frequency dependent losses

+ |$ C6 ~; g& p4 Y6 |$ E, ?" c* F26. a reverse nyquist approach to understanding the importance of low frequency information in scattering matrices
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' [9 i: u. s5 o6 i& R! n& q1 U$ k27. Terabit/s packaging design for testing of high speed IC transceivers
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+ U+ P, y) w5 p; v( [. y& e8 s28. Channel operating margin(COM):evolution of channel specification for 25Gbps and beyond

5 z" m$ c  N1 h（7楼继续。。。）
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wanily

很好的题目  能看个详细的就好了

dzgking

看到这些感到学无止境啊，叹自己懂得太少

signory

如何下载这些论文？

understudy

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2 m% K8 s3 c+ a" J% I! W共享其中几篇SPI方向的文章：

2 y8 t, h1 R* \' K3、Channel to Channel Crosstalk Behavior and Design Optimization for DDR4 Signaling
" k% C1 Z+ n( [# j" a" r4、signal and power integrity(SPI) co-analysis for high speed communication channels
9 m# K# _+ F9 Z3 J5、innovative PDN design guidelines for practical high-layer-count pcbs
& _8 p( W0 ?2 O( B5 k8 F; \# I9、beyond 25Gbps:a study of NRZ and multi-level modulation in alternative backplane architectures

lpch8

非常感谢分享，那里能下载到论文，每年这个时候就期待。

stupid

1. A reusable generic platform for validation and characterization of high speed mixed signal designs
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! y8 y, D* k; a2 d8 |0 z% vRambus 出品。
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2. A rapid prototyping of FPGA-Based duobinary transmitter/receiver for high speed electrical backplane transmission
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宾大和Agilent联手，Agilent方面是Mike Resso.
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3. channel to channel crosstalk behavior and design optimization for ddr4 memory buses

) ~1 ?! Y# e& z6 z2 yIntel，Xiang Li，DDR4连接器规范的制定者。

4. signal and power integrity(SPI) co-analysis for high speed communication channels

" F, }5 K2 W$ u4 ^; RIBM美德研发中心联手。
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5. innovative PDN design guidelines for practical high-layer-count pcbs

作者主要来自密苏里理工，其中Siming Pan 和Jun Fan都来自清华，后都就读于密苏里，俩人貌似有师生之谊。

6. Time domain and statistical model development,correlation,and analysis methods for high speed SerDes
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0 J, L, K! L# @5 B; NLSI和Agilent联合，Agilent是Fangyi  Rao。

7. applying microwave techiques to digital systems: a simple case study
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) R- }7 E" ?8 sCray、SiSoft联合出品。
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8. high throughput,hign-sensitivity measurement of power supply-induced bounded,uncorrelated jitter in time,frequency,and statistical domains

Altera出品，3个作者都是亚裔，其中大家熟悉的Daniel Chow，以及一位疑似华人Shishuang Sun。
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9. beyond 25Gbps:a study of NRZ and multi-level modulation in alternative backplane architectures
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LSI、TE联合出品

10. Memory interface on-chip PDN noise Charachterization,modeling and its impact on timing
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/ E  N2 F- v' F5 u2 f6 YAltera出品，9位作者。

11. Enabling DFT logic and timing verification in mixed signal designs

Rambus和Synopsys联合出品。
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2 o+ g, K- q0 L0 m12. analytic solutions for periodically loaded transmission line modeling
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" v9 y+ n% l2 X6 ~) iIntel 和 Ansys 联合出品。

9 O  Y9 G$ r7 G6 l13. power-signal co-integrity design for multi-Gbps low-power DDR3 mobile platforms

Samsung出品，目前似乎还没有用LPDDR3的手机，但是毫无疑问，这将会很快成为智能手机的标配。
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) W+ A/ T0 V/ y2 i8 i7 M' [14. power/Ground bump optimization technique on early design stage

2 Q9 ~1 q  f0 y7 K: WSmasung出品。
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15. DDR memory channel design from passive stub eqalizer perspective
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% u: k4 N" G! g7 YIntel，貌似1位华人 Qin Li。

: c6 R* q8 O" B" k& ^6 @) v) G16. using power aware IBIS v5.0 behavioral IO models to simulate simultaneous Switching Noise
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Xilinx 和 Cadence出品，非常有用的SSN仿真文章。
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17. validating EMC simulation by measurement in  reverberation chamber

; t  Y8 @; Q  Y来自Cisco，作者中有4位华人，3位来自思科中国研发中心，分别是Xiaoxia Zhou，Hongmei Fan，Jinghan Yu
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4 N2 `) I6 ~* L18. 3D interposer design and electrical performance study

Rambus 联合出品。

1 S4 `$ s1 s# e) }: O' ?+ ]0 v. N, p* {19. Dramatic noise reduction using guard traces with optimized shorting vias
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Eric  Bogatin和Lambert Simonovich联手
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2 _8 j4 _" Q+ {9 T' g! \; ~1 M3 o20. effects of ground via asymmetry on mode conversion for high speed differential signals
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IBM独家出品。

2 g& @4 M6 G% d6 ^; N' y0 l5 u21. design and analysis of a high-speed parallel interface for 16Gbps coded differential signaling
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Rambus、Samsung联合出品。
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22. measurement-based simulation:increasing IBIS-AMI model Accuracy with Data from lab measurements

5 j# J; h+ A5 K, A6 U' {SiSoft、Ericsson联合出品。
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23. accurate receiver clock positioning in high speed parallel buses

6 G7 {! M+ ~+ E3 V5 gRambus、Altera、xilinx、Qualcomm 联合出品。

24. partial response and noise predictive maximum likelihood(PRML/NPML) Equalization and Detection for high speed serial link systems

4 H$ C# N# d. @& G3 I7 U2 dLSI出品，3作者中有一个中国人，Cathy Ye Liu，1995年清华毕业，后去了美国。
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25. Which one is better?comparing options to describe frequency dependent losses
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Eric Bogatin联合CCN，Simberian出品。

, r& r5 C8 O9 A4 {26. a reverse nyquist approach to understanding the importance of low frequency information in scattering matrices

3 N6 |! Z6 f# _8 ?* K- rAnsys出品

27. Terabit/s packaging design for testing of high speed IC transceivers
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5 q5 c8 H, |) j: i/ u$ w- O出自鼎鼎大名的IBM T.J.Watson Research Center，Xiaoxiong Gu是众多作者中的一位。
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/ V4 N; Z0 U5 |! v/ d28. Channel operating margin(COM):evolution of channel specification for 25Gbps and beyond

6 x2 J0 {& t& K, J8 S8 _Intel、Altera联合出品，Mike Peng Li出手啦。

9 s9 m5 G7 |+ }" A从今年DesignCon的获奖论文看，Rambus依然是论文大户，共有5片论文获奖，其中4篇是和别人合作。Intel 4篇，2篇与人合作。Altera 4篇。IBM独自贡献了3篇。 Samsung 3篇，一篇和Rambus联合，跟最近整个三爽的势头一样，表现的很猛。LSI 3篇。Agilent、xilinx、Sisoft都是2篇。多产的Bogatin博士，也是2篇。仿真大户Ansys这次只收获了1篇。 整机厂商，如Cisco、Cray、Ericsson则均收获了一篇。
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) E  B: V+ z; x# S密苏里理工表现优秀，乔治亚理工则没有收获。

国内SI的领头羊，华为亦有论文宣讲，但未中奖。另外Qualcomm的有线部门开始发力，他们目前的重心应该在10G 以太网上。

3 z. L, Q& ?+ A9 R8 L另外，几乎每篇获奖论文的作者都有一个华裔，从侧面反映出来中国人苦逼，到哪儿都是做民工的命，呵呵……
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lpch8

分析的好，慢慢看吧。

sleeper2008

只能看名字，还是顶一个

qiye408

学习下，楼主V5

2821462144

路过，了解，

chenqianwjkx

想下载，不知道哪里能下到这些有用的文章

stupid

chenqianwjkx 发表于 2017-3-21 05:51
想下载，不知道哪里能下到这些有用的文章

本论坛就有下啊

frank2

技术无止境，慢慢看