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在原理图package的时候出现Parts DataBase中没有某个符号的Part Number是什么原因

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1#
发表于 2012-12-19 20:37 | 只看该作者 |只看大图 回帖奖励 |倒序浏览 |阅读模式

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我在原理图package的时候出现Parts DataBase中没有某个符号的Part Number是什么原因?! T7 j2 G& O  H# \7 I( p6 O
检查symbols和Parts都有Part Number啊,错误提示如下,请高手帮忙解答。
0 m' U3 y6 V9 J# R
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ERROR: There is no Part Number: FCT16245 in the Parts6 H7 z3 i3 @6 q, Q6 j1 A/ Z  L0 c
DataBase for symbols with Part Name: FCT16245 and Part Label: 16-Bit Transceivers.3 e2 Y$ C7 W* |2 ]% P5 ~
[Please add the Part Number to the PDB either directly
# e) d" Z" A8 R6 G+ T$ Lor by having the project file point to a PDB that contains it.]

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发表于 2013-10-18 23:42 | 只看该作者
hittjd 发表于 2012-12-30 15:03- c. F2 j% J( W
所以器件都做part了,而且可以确定是从part view里拖出来的。。。

& }: m  ?  o6 o0 s  V% e6 T* j请教个问题,我在做part时,遇到下图的情况,好像是symbol的pin(s)没有映射,请问如何设置啊,谢谢

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3.JPG

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2.JPG

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2#
发表于 2012-12-22 22:30 | 只看该作者
删掉有问题的元件,重新调一边进来,再PACKAGE就好了。

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3#
发表于 2012-12-23 19:34 | 只看该作者
打开中心库对应器件的symbol,检查左下角是否有Part Number项。

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4#
发表于 2012-12-24 09:23 | 只看该作者
看看库里的Part Label,这个也需要对应的
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5#
 楼主| 发表于 2012-12-29 08:54 | 只看该作者
sunny_sun1022 发表于 2012-12-22 22:30
9 y, q4 w2 t/ \! B- h删掉有问题的元件,重新调一边进来,再PACKAGE就好了。
. h7 i0 H+ y/ T; l3 ?0 {
试了,不好使。。。

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6#
 楼主| 发表于 2012-12-29 08:54 | 只看该作者
simhfc 发表于 2012-12-23 19:34
- r8 h: ~# x9 `1 \) l7 B& ?打开中心库对应器件的symbol,检查左下角是否有Part Number项。

3 W& _- L: E" e/ e/ @有,这个肯定有的。。。

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7#
 楼主| 发表于 2012-12-29 08:56 | 只看该作者
zxli36 发表于 2012-12-24 09:23
8 Y) G; z2 t- p5 `2 f3 x看看库里的Part Label,这个也需要对应的
& f2 ^  ^3 [& X
请问怎么对应?我原来的Part Label跟Part Number不一样回来我都给改一样的了,还有part name ,还是一样的问题。。。

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8#
发表于 2012-12-29 09:02 | 只看该作者
本帖最后由 zxli36 于 2012-12-29 09:03 编辑 # ~6 f7 n) L2 I* A6 S

8 |4 H4 o( @& h' P- W对应是是你的DxDatabook里面的这个项的名字要和你库里的Part里面的这个项对应起来。  M+ ^: Z" d% z. M" Q
比如你Dxbook里面的器件:4 s+ `* ?* ?9 b9 |
PartNumber: IC1234PN0 @" q8 b0 ]. r* _$ B! ]. t
PartLable: IC123Lable5 I3 D* M6 o' ?* E" x% ?/ l
PartName:IC123Name
# I; {4 G* x' u  N$ ?: U这是你的库里的Part也需要想上面的那样写名字

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9#
发表于 2012-12-29 09:04 | 只看该作者
能不能把你Package时的信息发上来大家看看。

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10#
 楼主| 发表于 2012-12-29 09:49 | 只看该作者
zxli36 发表于 2012-12-29 09:04
( \6 Y, M: H6 b! O能不能把你Package时的信息发上来大家看看。

/ W1 U% W; }! N7 TPackage时的信息如下,总共有二十几个问题,几乎所有器件都有问题,这个问题困扰我很长时间了,麻烦您帮我看看,非常感谢
* x3 B; m" y" H* m# ^' `. _
1 p8 s! B, l. m8 G# Z* [-------------------------------------------------------------------------------------------------------------------------------------------------------  Y6 |( @6 z' p8 H. e" ~0 E) h
Started C:\MentorGraphics\7.9.3EE\SDD_HOME\wv\win32\bin\packagerui.exe F:\demo_dx\demo_dx.prj /d Board1 /nobrowse /config "C:\MentorGraphics"8 p8 B) q- J9 V) _! K9 c+ G

- e- I' v7 F, ?. XPackager Version: 020806.00
5 S% i" M7 A3 h5 o0 L  F1 S( Q7 ?, e$ C/ \9 @
Commandline is: "C:\MentorGraphics\7.9.3EE\SDD_HOME\wg\win32\bin\package.exe -jF:\demo_dx\demo_dx.prj -nBoard1 -Add": ?. n5 l8 d8 k7 Z% D

( b. X: e3 C/ Y  N8 H9 `+ yThe Common Database is at "F:\demo_dx\database".
4 C: l% |) F$ D; N
" @! |: s) r0 m0 g, z% r1 k4 IThe Root of this design is "Deme_Root_1".. y$ \/ V! N" \% v6 F7 G
/ C) `7 E$ T; p2 Q
The Front End Snapshot of this design is "DxD".
" H) l1 }% d3 i1 S1 A, D  d' J9 h2 }
The PCB Design Path of this design is at "F:\demo_dx\PCB\Board1.pcb".
" Q* a2 P2 ~1 _0 [; o# \- }# I* a! T+ P- t! @8 E
The Central Library is at "F:\Central_Library_for_DxD-Exp\Central_Library_for_DxD-Exp.lmc".
' ]0 k  ?8 p" r: \% Z9 I2 |( G* y# j' \# J* T4 F1 G2 C' y1 q, H) V3 d
Unable to determine the Disable Repackage status.
* U# s& |4 i6 \9 z- {% s9 j!Repackaging will be allowed!$ E; w! M5 F# e+ W! g

, [& G1 P2 r# |1 f" r, W* [The PDBs listed in the project file will be searched to satisfy the parts
9 k; v, H: i6 l+ H$ M  T4 F) |requirements of the iCDB only for parts not already found in the
, X) _7 q4 N6 ]5 cTarget PDB.
+ F% U! m' Z/ e" v9 h2 v# z6 c
) Y1 f+ A* S  J9 y" J& OThe AllowAlphaRefDes status indicates that reference; s9 p: _6 n( z$ ^
designators containing all alpha characters should be deleted/ W6 N+ X7 o4 n
and the relevant symbols repackaged.
9 D! N- A( T, `7 f5 y( n/ t, Z/ D* D1 m
The cross mapping of symbol pin names to Part Number pin% _4 K. l: X& p: u7 A6 P
numbers will be checked for packaged symbols and mapped correctly2 u; c, i7 d# n( ^
for unpackaged symbols.8 d& z5 ?" N  K* J- x) F
( k, E! Z7 L' u! Y' j( O+ S
Properties that have been checked off in the Property Definition Editor. P5 y" P* g6 p0 r
found at Library Manager/Common Properties will be checked for value
8 j. Q% |. z% S; ?differences between the PartsDB and the non-null properties on symbols.
" p3 l& I/ Q' A2 rThose properties checked off (other than Part Number)
4 E2 J2 _; [/ M8 f- Xwill not be transferred from the PartsDB to symbols.) j' w( u* e/ i7 Q
The following properties were checked off in the Property Definition Editor:
0 {4 y* _3 y+ d9 i: l"EPFIXEDWIDTH"
7 d/ ]. B/ ]9 a' H$ z"EPFIXEDLENGTH"3 k' N$ o# n* ^( e
"Term"9 F- D1 c! W" L4 V( [) |
"SIM_MODEL"
( o# M/ B: _# w5 v) g"SIM_MODEL_FILE"
& n* ]2 E+ Q- ~/ J"Array Component". h" S4 m8 T8 s( `, N5 D
"ICX_PART_MODEL"9 o4 A& G' |$ n) K
"Use Verilog"# |8 ~& y- Z- k0 B1 w
"Order"5 N$ N8 s% c3 }9 a. x5 j
"Parametric"
* o! d8 ?1 A& v4 c2 D9 G6 `5 e( C"Value2"
1 f% Z' L4 j! E"Tech"
* y  z7 o7 U) E4 @0 ^"IBIS". [& E; W! o, F
"Part Label"! {# n$ A  N& F
"VHDL Model"' ^, Z$ I$ `, v! a7 X1 F0 z
"Verilog Model"
6 u' V/ V; k* S7 ?) Q; V1 ^- q"Cost"# ?4 _# s3 e7 I) c0 I/ t3 ~
"Tolerance"6 j4 ?. [5 Z/ a8 x8 O( d
"Part Number"
6 d% }8 l' o) ]/ A7 S"Value"  f: u; j. a1 Z, c2 _& f) R9 H: p
"Part Name"1 W  W5 S4 W! h2 @% ?( H, c2 @3 `

4 a+ c+ \3 T: d$ o1 P8 j
* z: O! i# p2 [) y- ~) E9 iTesting of Packaging is being terminated with 22 errors and 1 warnings.1 O2 T% [0 U. m# s7 G0 B
Design has NOT been packaged.  x% K6 l. E2 g& \- l3 N
* J- H: T! l% v1 n. Z# G7 y4 s
Writing to Log File: Integration\PartPkg.log
( b& c; w/ z/ d- `& {7 M& Z4 H. W$ [5 A9 D1 `
There have been 22 errors and 1 warnings.' J' @3 u6 {( L" |6 ~4 B
4 l9 b1 M+ Y! C( Z
///////////////////////////////////////////////////////////
8 |2 J& @4 j& v4 i///////////////////////////////////////////////////////////
7 ]0 e; @6 x8 F8 s///// The Log File will now be copied to this window. /////
  \$ r/ G# s2 `///// Therefore the data above will also appear below /////
3 I( A4 B" E9 v, D///// with more specific error and warning messages. /////
8 T1 b& D" s2 w* _+ n/ y, G///////////////////////////////////////////////////////////
0 \2 u: C) f. p9 ?( M3 A///////////////////////////////////////////////////////////
4 y9 `4 d6 Z# |$ t; S
: T+ \8 U: j0 ?% c% G
1 B6 S* K' d( U: l' B/ jPackager
: M6 z4 ]' [+ ^9 K: W4 R. V--------
+ M4 G- b" h& S$ ?/ f# Q0 _2 b( C% R1 X/ ]$ e! @/ P+ G
09:27 AM Saturday, December 29, 2012
4 ]$ E( q$ U( d8 ]: k5 m: FJob Name: F:\demo_dx\demo_dx.prj
1 X( |  R0 a" |( I7 O: N2 z1 W* c( z( y  n

' P0 t& x1 b* k$ W$ NPackager Version: 020806.000 V3 ^# n  \; Z2 k  a3 G% S. Q

; a( \- K/ F/ p( R0 f( b* yCommandline is: "C:\MentorGraphics\7.9.3EE\SDD_HOME\wg\win32\bin\package.exe -jF:\demo_dx\demo_dx.prj -nBoard1 -Add"+ N2 @2 x0 F: y9 B3 J4 K
* v  ~+ i1 v- F2 r7 J) b3 i
The Common Database is at "F:\demo_dx\database".
% H& `1 |$ B" O8 |2 x8 A$ _3 w4 G* w( Y; w2 o& [
The Root of this design is "Deme_Root_1".
% j5 U: p( g! g0 ?9 V  J3 C
/ y5 g7 d' d. E4 j" u/ X) AThe Front End Snapshot of this design is "DxD".
* c  [  ?/ c0 e$ V& \
  i. T8 q4 ^5 S* h7 \5 l8 lThe PCB Design Path of this design is at "F:\demo_dx\PCB\Board1.pcb".
% E: x6 F7 _, I6 d" p
9 c# B4 n6 l, O. S) s' r. SThe Central Library is at "F:\Central_Library_for_DxD-Exp\Central_Library_for_DxD-Exp.lmc".( G3 T/ S7 T& |0 q' P6 O9 c  j( \6 B
; r* y6 l' q9 l; e
Unable to determine the Disable Repackage status.3 u( V2 J* H1 }' Y1 V+ L5 ^2 b- ?
!Repackaging will be allowed!9 I4 I$ Q  w) G* |( ]7 K: n

9 p6 W4 h" ^' i# R0 L0 N: o2 SThe PDBs listed in the project file will be searched to satisfy the parts# w4 K6 w7 L; n- p
requirements of the iCDB only for parts not already found in the& x% @" Z0 u# J# p
Target PDB.
0 w; o6 Z' d. V3 r4 N( p2 T% z8 _5 b: j: T$ ~3 I' n) t+ |
The AllowAlphaRefDes status indicates that reference
3 k- h, M1 x  t! r! c3 ^designators containing all alpha characters should be deleted
" L, [) \5 ^5 v4 @. jand the relevant symbols repackaged.5 x& S5 l  w5 `% v1 ?/ {
0 ^( m8 M+ V! B" L# u, B# U2 x
The cross mapping of symbol pin names to Part Number pin9 d: `% X! a6 l# G0 k
numbers will be checked for packaged symbols and mapped correctly
9 L$ H8 e, S  ~+ I' b/ f& ~for unpackaged symbols.# R1 g6 U9 v$ `! F8 q2 Y
1 _. y" t" {: K" N
Properties that have been checked off in the Property Definition Editor
" P+ Z( W- r2 V- {found at Library Manager/Common Properties will be checked for value
2 l3 |$ S- P7 ~/ I. M* cdifferences between the PartsDB and the non-null properties on symbols.' ~5 B. _# P0 x( Y- M  H' {
Those properties checked off (other than Part Number)1 K# x7 i' c: [, q5 Z. a
will not be transferred from the PartsDB to symbols.4 ~& V+ z0 }( i& n* f  m
The following properties were checked off in the Property Definition Editor:
$ \7 g2 w5 c" {- c. u6 N"EPFIXEDWIDTH"2 p  T" }0 U$ X/ S5 Z" }/ C# t
"EPFIXEDLENGTH"
8 A$ I! O  t# x; s: S/ Z0 w. c7 t, J0 H+ @"Term"
4 @/ u% j1 ~; c: U, m! J% M. D2 f"SIM_MODEL"
8 f& `! D. ~; v2 |9 O  Z) Q"SIM_MODEL_FILE"+ ^6 u8 s5 U, P3 |; ^" Q7 Q+ ?
"Array Component"' |' W/ ?; {* F2 p  V& o7 {
"ICX_PART_MODEL"7 i! G* ?. S4 t( ~* w+ @5 B
"Use Verilog"& L7 g: w/ w0 h- X+ ?7 I8 t* C  ~
"Order"
9 i* q2 d' Z: ^( k; Y, }"Parametric"3 |4 U6 H! [& ?9 O+ a) M! ]4 o
"Value2"
# m( w: ~; }; j, f6 U* }# I"Tech"4 W+ t4 o- n" s0 N4 X9 O/ e
"IBIS"
% ^+ [/ J: T4 J* ?0 l; ~; H"Part Label"2 w5 t7 \3 j: h9 E) Y
"VHDL Model"  ~0 O! h, n* D
"Verilog Model"; R1 d9 y3 u; Z" [- z! \/ B
"Cost": y5 d0 |$ ]1 D( u. A- u
"Tolerance"
  k( @/ M$ ?/ q+ I"Part Number"/ l! a4 l( m' p7 n( j. Z
"Value"
4 a# M" r, h% y3 d/ ]! Y/ M"Part Name"
# g. R8 `6 B+ A8 K) B5 g7 i7 p
% W# s; Q4 z& h$ u+ dChecking for errors in the ICDB...
0 `$ h5 N: m5 _9 |7 q
* f) n9 _# ^5 _No errors found. Proceeding with packaging...
4 v: _& m1 {' z" ?, M( Y5 c6 F# I/ T+ W) c! S  |, A& G/ Q

; S9 V' C( x1 F& N' u% Y
" a. _0 b9 a6 k8 X: Q& oCommon Data Base has been read
& U6 {( E7 {, Z+ S/ i4 Q2 _, a. J
- D- U2 ~5 ]& |8 F& k3 n- fTarget PDB Name: Integration\LocalPartsDB.pdb& Z" T) b  v. [, A7 X& [  L2 w
8 }( C9 R0 y7 k) U+ b
WARNING: There are no PartsDB partitions from which to extract parts.2 r( M4 s8 O% z9 N- ^
Proceeding using the data in the local PartsDB "Integration\LocalPartsDB.pdb".
5 j$ N2 J8 h) W; k8 C/ k% @+ i8 n" [1 T3 D- ]' G) R
Number of Part Numbers: 21
( X0 R0 M: r% v9 [3 h: OPart Numb: BNC_1 -> Vend Part:   `0 r# \" ]0 R+ k
Part Numb: CON_EDG_64 -> Vend Part:
  J" l: n% H+ k9 b# n7 K- J: c% tPart Numb: C_P0.01pF -> Vend Part: - X) M1 r: y7 \3 k! a
Part Numb: C_P3.3uF -> Vend Part:
5 x2 h) k6 t* B; D) K+ N2 FPart Numb: C_P47pF -> Vend Part:
- z* g5 k: T0 x1 hPart Numb: C_0.1uF -> Vend Part: ( _" o1 b: d9 x& M; S) C
Part Numb: DG419AK -> Vend Part: + _8 x! F$ O0 n- j6 J
Part Numb: EPC1064 -> Vend Part:
  _- w6 e7 a( [& @' T+ ?9 ?Part Numb: EPF8282A -> Vend Part:
8 V9 n3 _" d% m7 m% w; h, W8 ]4 j1 hPart Numb: FCT16245 -> Vend Part: , u% c! b; a) C8 W4 w* g
Part Numb: LED -> Vend Part:
- T- z' }4 _/ D+ J. L. Q3 M" EPart Numb: L_50uH -> Vend Part: ( T& s+ r8 U2 M$ j/ R  ?
Part Numb: R_2K -> Vend Part:
, m, {2 U% ?. K) n) oPart Numb: R_10K -> Vend Part: ( s; ]* Z# C5 C" ^* d% R5 r8 Y
Part Numb: R_100 -> Vend Part:
2 ], V5 d5 C4 RPart Numb: R_220 -> Vend Part: ) b9 r8 [* R9 V! S% A' x5 m8 e$ J
Part Numb: R_510 -> Vend Part: 2 Z# Z' e* V* k9 l8 g$ @
Part Numb: TC55B4257 -> Vend Part:
# F; _$ N( |2 N( vPart Numb: TLC5602A -> Vend Part: ! R" @+ b7 t8 W$ Q
Part Numb: 20L10 -> Vend Part: " Q. l! o% h; A: [* j4 |
Part Numb: 74ACT574 -> Vend Part: 6 F" T0 D4 @7 a" f/ B* C
: k' g) w' |5 K& Y4 x( M
Number of Part Names: 1
, \0 y; `/ A, }. M9 [% k' s" o  hPart Name: TLE2037A -> Part Number: ' X$ Q/ l; ]0 H' N
* v# L5 v1 y8 ^# j- g6 k8 N( [0 B
Number of Part Labels: 0* v' N: g# h5 A9 x

+ E! x! E( h7 y  O
$ N3 b! k0 P. U5 u5 o3 dChecking for value differences between non-null symbol properties and PartsDB properties,
8 ^/ C3 s$ F1 ~' q9 d2 m6 V/ ^' Y9 abut only for those properties checked off in the Property Definition Editor
  V' u8 h6 f" |2 V7 q/ d. h. U- j6 ~9 |. {
Checking the validity of the packaging of prepackaged schematic
7 O, k$ N# ~. w% psymbols. Only the first error in symbols having the same2 N. N7 y6 o. O
Reference Designator will be reported.5 O7 d2 X3 d9 x) `% n5 x2 F9 |

- ^6 z% t1 c0 B5 X* \9 DERROR: There is no Part Number: CON_EDG_64 in the Parts; q, N! S$ C/ h2 t. |0 G. j
DataBase for symbols with Part Name: CON_EDG_64 and Part Label: (null).
' W0 B+ j" u3 d9 D. t[Please add the Part Number to the PDB either directly! f2 b) R; y$ Q) K6 _; z: ]6 [
or by having the project file point to a PDB that contains it.]
" N+ ]" h5 E: J4 r6 n* I. |The relevant symbols are:+ h9 a/ g! S4 R! q9 `: w$ e
, P  l! Q4 \( {2 {7 v5 E
Block Deme_Root_1, Page 1, Symbol $1I41
  C2 a8 ]! M; |5 [  L$ @1 E4 U# w) `$ `/ n+ _2 A( e
ERROR: There is no Part Number: FCT16245 in the Parts+ z$ L) O/ g  z; v
DataBase for symbols with Part Name: FCT16245 and Part Label: FCT16245.
. |: P+ S+ I" Y8 f- e2 X& D0 ?[Please add the Part Number to the PDB either directly
* O: V7 Y) N% ~; T: j+ i) S  Kor by having the project file point to a PDB that contains it.]+ l% w  g2 A4 v1 X
The relevant symbols are:6 J; M& f( t  |" I. [

- u  I0 p8 l2 S Block Deme_Root_1, Page 1, Symbol $1I1277
) k% t8 p0 N6 b: U3 Z) F Block Deme_Root_1, Page 1, Symbol $1I1424 5 g* F- F( k, Z  q
Block Deme_Root_1, Page 1, Symbol $1I1395
/ B& @- X8 W9 q2 m2 j Block Deme_Root_1, Page 1, Symbol $1I1366
; \* X3 ~+ ]3 A) {' j! C( \$ ? Block Deme_Root_1, Page 1, Symbol $1I1337 0 H) f: J/ {6 g; `: F" ^
Block Deme_Root_1, Page 1, Symbol $1I1308

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11#
发表于 2012-12-29 10:44 | 只看该作者
这个信息写的很清楚了,只能根据这个信息查先。真不行了就要发库给别人看了。

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12#
发表于 2012-12-29 18:05 | 只看该作者
There is no Part Number: FCT16245 in the Parts2 z# ~; V8 N( @4 t3 _" w
应该是只做了Symbol和Cell,没组成Part;
3 o5 p  e3 }/ M' ^' e0 g: P4 B! b: r) P) c
所以说在实际工程的DxDesigner里,DxDatabook要用Part View,不要用Symbol View。

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13#
 楼主| 发表于 2012-12-30 15:03 | 只看该作者
simhfc 发表于 2012-12-29 18:05 7 x7 i6 ?8 Q# S7 w
There is no Part Number: FCT16245 in the Parts1 ^, ?+ g; {+ M1 v$ S
应该是只做了Symbol和Cell,没组成Part;
3 F6 h7 W0 b, i' ~5 V. r+ _0 P
所以器件都做part了,而且可以确定是从part view里拖出来的。。。

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14#
发表于 2012-12-30 22:41 | 只看该作者
做了Part之后,有没有改动过Symbol或者Cell的pin name / pin number ?4 X0 c" j/ e" C, v4 J' T
9 z$ D* O6 l4 w( d4 z0 {' H% p. ]% l* Y
比较直接的办法是删除那个Part,用现有的Symbol和Cell重新建一个Part,然后去原理图里更换。

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15#
 楼主| 发表于 2013-1-8 19:47 | 只看该作者
zxli36 发表于 2012-12-29 10:44
0 `) \4 F/ u1 r9 J( I这个信息写的很清楚了,只能根据这个信息查先。真不行了就要发库给别人看了。
, d' d& p, }; }  J' a/ \3 r
能给我发个你的邮箱么?我把原理图和库发给你,你帮我看看吧,拜托了!
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