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I2C START / STOP Detector Verilog Code ~, c1 x3 B5 L( {
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. X7 K. J' M; X& R0 N- cmodule i2c_start_stop_detector (
% V% b1 ?, E& q0 f8 X' ]& b: C! y7 l input wire clk, // 系統時鐘 d! F& }! p$ R" S$ v
input wire rst_n, // 非同步 Reset8 ^: I5 I2 d2 K( u, {! X2 o5 I4 ?
input wire sda, // I2C 資料線 D. G- {8 ~! Y2 K. B4 {+ v
input wire scl, // I2C 時鐘線
- N8 D; e' p! S7 N# H% N* O% ^- j/ i7 K output reg start_detected, // Start 條件偵測到1 {2 E5 ~& d4 u
output reg stop_detected // Stop 條件偵測到; h5 Y' u7 f" {* a
);
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// 前兩個時鐘週期的 SDA 與 SCL 值
2 X$ k. m3 J1 t% W( z6 Y reg sda_d1, sda_d2;
6 p6 }0 y; l+ J& e/ |3 O" v6 [9 r reg scl_d1;
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+ ?% A4 X! n! y2 y' G. M wire sda_rising = (sda_d2 == 1'b0) && (sda_d1 == 1'b1);
7 o. s2 [, t. [0 H$ b wire sda_falling = (sda_d2 == 1'b1) && (sda_d1 == 1'b0);- w8 B0 I# I0 I" l* ]. X) o& H
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$ E" G; Z& o; M8 B5 a8 S // Sample SDA and SCL
$ j6 ]+ _' Z6 U' _1 e2 } always @(posedge clk or negedge rst_n) begin
* Q$ h4 @' Z& H( I9 S% W: F if (!rst_n) begin
u4 E7 q1 p; D, e0 Y7 Y+ l sda_d1 <= 1'b1;
, C c: I4 _) g! x( N; v0 B8 Q* \% | sda_d2 <= 1'b1;8 ~ r! D. m9 q. @( u9 }' n
scl_d1 <= 1'b1;
& k6 q: g/ j/ k1 r3 z end else begin: Z7 }* F0 u# u! \% i
sda_d2 <= sda_d1;* m% W' G0 F# k# r
sda_d1 <= sda;$ L0 B" q+ D5 U$ m
scl_d1 <= scl;0 h1 J8 L2 }# U0 _) P2 U
end
1 |/ T3 c( Z; j# {% T$ ] end
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9 V* h# U3 B( d- t" ] // 偵測 Start / Stop 條件
/ v* n# Q, F4 q always @(posedge clk or negedge rst_n) begin
6 `" o/ ]1 x+ h0 J% H; K3 v1 T& j if (!rst_n) begin' \: V. K U0 r0 }. E* W) L: x
start_detected <= 1'b0;+ K& U* f' X( @2 d) O i h
stop_detected <= 1'b0;
# o* i0 O% k9 C8 i end else begin
5 y% _& W O6 P% q T# u // I2C START: SDA falling while SCL is high9 k" x# H/ }3 M" V9 m$ ]
start_detected <= sda_falling && (scl_d1 == 1'b1);
2 w* W- A: u' A2 g5 j6 g" c // I2C STOP: SDA rising while SCL is high% C6 Q* H) D3 K: v1 ^% x
stop_detected <= sda_rising && (scl_d1 == 1'b1);
" Y, t* U' U5 Q, c8 W3 a- j end! \( J0 }: J b" `( M8 p' [
end
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endmodule
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/1 
楼主
发表于 2025-6-27 16:39
发表于 2025-6-28 19:47
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