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现有DDR2的地址总线，在sigxplorer设置后T点之后更新到pcb中发现有一根地址总线add15没有加上T点，报警为红色，以下为更新工程的结果：请教高手原因？
6 r0 O3 j) d; y* JProcessing Net XM1ADDR15 in design S5PC100==V1_0
$ H: s& P! e2 t7 F0 l! ]Date/Time: Wed Oct 24 18:54:42 2012
: G2 E, x" S. M! P8 N
8 a$ i) T Z! e: TMapping Pins of Cset: DDR2_ADD_BUS' c/ ]% Y1 C0 ]3 b3 H" o# J M& x
Mapping Mode: Pinuse and Refdes
" g1 U( o+ A' o9 C/ |6 V- R4 I, H% L*ERROR: There is no net in the Cset that has pins matching those in net# 0 in the Xnet.2 ^2 y+ e% L' B7 ]+ e# v
$ E$ n# a; w2 L, \, H
Cset end point Group Buffer model Value net# W* X+ R2 o$ L6 J+ _' e
--------------------- ----- ----------------------------------- ----- ----! v. B$ f- G9 {: V
S5PC100==V1_0 U12.D18 IO S5PC100X8A_081223_pvhbsudtartg_t_00 NONE 0
2 p+ i5 c7 Q% \/ I0 ^$ C$ WS5PC100==V1_0 U4.L3 IO CDSDefaultIO_2p5v NONE 0" l5 l, [" @# o5 d
S5PC100==V1_0 U5.L3 IO CDSDefaultIO_2p5v NONE 0
$ C6 @+ e$ A/ h+ N2 H' w& U2 I6 yS5PC100==V1_0 NET.T.1 rat-T NONE NONE 06 O- {2 @# U. ?) K) y: I. Y# r. @/ \6 A
! M4 S7 e2 I; Y r+ @7 N3 SXnet end point Group Buffer model Value net#
3 ~" ]! s9 G' f; j--------------------- ----- ----------------------------------- ----- ----
7 ~5 A+ W4 I3 IS5PC100==V1_0 U12.D18 IO S5PC100X8A_081223_pvhbsudtartg_t_00 NONE 0
]0 J. H, ^# \. A2 k, w*WARNING: Due to mapping error, Min Tree scheduling will be used for Net S5PC100==V1_0 XM1ADDR15.* r, v9 [8 z3 g3 e9 ^
5 \% h. [2 R6 K: ENet S5PC100==V1_0 XM1ADDR15 Schedule: Default& f; i J5 g' R5 P7 D1 Z( n& _3 f
Verify Schedule: VERIFY( Y3 W" r8 `& w; _+ w5 [: |
1 i+ c, n2 n8 b' J( d4 m0 s**************************************************************************
, L4 K& @6 r* f5 ]; H- F S7 K6 D, _
Processing Net XM1ADDR14 in design S5PC100==V1_0# `% ~4 \( i1 E: ~
Date/Time: Wed Oct 24 18:54:42 2012% v+ l0 b/ S4 c0 C2 X: a
k/ _ R! ~! }Mapping Pins of Cset: DDR2_ADD_BUS9 W" H1 O9 f, A1 D% t% q F
Mapping Mode: Pinuse and Refdes# p& w5 L( U% T V; p i
" {: y# c1 f* D ~
Cset end point Xnet end point mapping mode / A7 W# S5 `) X ^
--------------------- --------------------------- ------------------
8 Y3 u, m( e4 W& w6 k/ e% zS5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.G13 Refdes
4 t; D$ Z0 d- i! i. r1 P8 d4 pS5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.L2 Approximate Refdes
$ w* D6 O$ j( e g4 a( }S5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.L2 Approximate Refdes# L2 f* @0 `% z2 U7 q
S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR14.T.1 Floating T-Point + v7 `7 V5 _' N
; U3 {6 z5 M. _" vNet Schedule: Template Defined
: m8 c3 R8 F8 F/ }$ C S5PC100==V1_0 XM1ADDR14.T.1->S5PC100==V1_0 U4.L2
- L$ N9 c e9 o* u* K' y: L S5PC100==V1_0 XM1ADDR14.T.1->S5PC100==V1_0 U5.L2
2 [+ C. M# n) E. U6 ` S5PC100==V1_0 U12.G13->S5PC100==V1_0 XM1ADDR14.T.1$ G6 J- w' v, N
- C8 |' D6 R* C& W a5 N& K$ G
Verify Schedule: VERIFY3 r2 M, [3 x- }, i
, I J7 U8 H. [ U/ B
**************************************************************************& m& t6 i% ~0 ^0 b. i
, O' s2 w; q& V1 g: ]) p6 CProcessing Net XM1ADDR12 in design S5PC100==V1_0
K% ~5 |+ |; s6 N4 L2 CDate/Time: Wed Oct 24 18:54:42 2012
1 a o6 U* r" \. U+ V
* y& k) w- m, w- ?Mapping Pins of Cset: DDR2_ADD_BUS A% p! b# }# j) u
Mapping Mode: Pinuse and Refdes. _' f K& o! O4 E4 e: K* N. Z
, t, t/ E/ K7 ^6 T: z6 [
Cset end point Xnet end point mapping mode
5 ], _; p- I" d7 a8 F4 q; {! E--------------------- --------------------------- ----------------
: E& P8 h6 s8 \1 Y) [S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.G12 Refdes S& ^) I" c. O3 z
S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.R2 Refdes % b n- ?: K% g3 F% a- a
S5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.R2 Refdes
@0 |3 R4 |8 g5 E' MS5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR12.T.1 Floating T-Point, T1 n8 ~/ H9 x% q/ _5 ~
2 P; z* L1 i7 x2 A1 E; @& b
Net Schedule: Template Defined! K& Y% A7 y! Y' \! b% d
S5PC100==V1_0 XM1ADDR12.T.1->S5PC100==V1_0 U4.R2. ]# K) h) b- H6 q( {5 ]0 R8 m
S5PC100==V1_0 XM1ADDR12.T.1->S5PC100==V1_0 U5.R2
7 X# Q0 e- L% d+ [ S5PC100==V1_0 U12.G12->S5PC100==V1_0 XM1ADDR12.T.1$ X' u, |% }7 \
E9 z$ M& l8 }9 M# y" _
Verify Schedule: VERIFY
' f$ a" s8 S, l# H7 N, D. ^5 t& a( W$ d, u+ E
**************************************************************************6 u7 h# `3 P9 D" x1 n! j" W8 f% t" J
: `9 O2 o) _6 ]& ~8 EProcessing Net XM1ADDR11 in design S5PC100==V1_0
2 b- w! v, Y: X1 f! g% ^" f; I2 _/ nDate/Time: Wed Oct 24 18:54:42 2012
5 ?: v' f0 |2 P# o; _1 [$ F3 i' j7 L2 r6 }: s8 e% o* T
Mapping Pins of Cset: DDR2_ADD_BUS
& h+ v6 Z# q: zMapping Mode: Pinuse and Refdes
0 E' Z' K8 ^0 e0 O3 e
4 b( r, i( D6 k3 Y' C. vCset end point Xnet end point mapping mode
" z. A9 W& M3 o: ^4 w# O u--------------------- --------------------------- ----------------
; K; `" R1 P3 r* B O5 cS5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.H11 Refdes
9 ~9 \$ F( s! gS5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.P7 Refdes . r/ s# h. V$ g9 z6 H1 @
S5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.P7 Refdes
- Q1 H+ T* v5 \S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR11.T.1 Floating T-Point
% B( H( v; K) V8 L' ~. Y) X. M: o, J& c- b/ o6 N# t j
Net Schedule: Template Defined
. V8 v+ z' X- O7 o0 P1 A4 H3 o S5PC100==V1_0 XM1ADDR11.T.1->S5PC100==V1_0 U4.P7
* m& G! T, l. G: m( q: m+ P# { S5PC100==V1_0 XM1ADDR11.T.1->S5PC100==V1_0 U5.P72 {, a6 S @( P
S5PC100==V1_0 U12.H11->S5PC100==V1_0 XM1ADDR11.T.1/ H% `- U* T. X& z6 J+ P
) u/ N) X9 ~7 t: _8 X
Verify Schedule: VERIFY1 ]3 @0 j% C, O1 o2 n
7 H) [" E& s$ q- A) s4 q* d" W**************************************************************************
3 A; O. C8 L, y+ `* m
, i: O' i# o" b; M* ]8 j2 `0 I# UProcessing Net XM1ADDR10 in design S5PC100==V1_0
6 f2 p' o( N% [- x6 ?* s- \' }Date/Time: Wed Oct 24 18:54:42 2012 O. h7 E1 E. X( U$ ]* I
! j! v3 p+ }. c2 z( F4 y' F, c
Mapping Pins of Cset: DDR2_ADD_BUS
* C$ N1 m5 W% TMapping Mode: Pinuse and Refdes
0 d' Q" k8 H7 Y1 P! n
5 Y# T% [: b) S1 K2 y: ^, SCset end point Xnet end point mapping mode
' n) ?# t% W: J--------------------- --------------------------- ----------------1 r" i( K% k1 d5 l
S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.G16 Refdes
/ W& e+ [9 N+ L% `7 C) o& r, {+ fS5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.M2 Refdes
+ d$ E& U. ?8 s" d" o, k, @4 w- J2 g6 jS5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.M2 Refdes 8 {+ o0 h ^5 O! Q* X7 o
S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR10.T.1 Floating T-Point
# r* y9 I9 b; E% t' A+ E2 M) U7 m N' S* r! M
Net Schedule: Template Defined
+ p, X+ M8 S- f" G- z6 I5 I! L$ D3 p S5PC100==V1_0 XM1ADDR10.T.1->S5PC100==V1_0 U4.M2
) x3 O# a6 ~5 l1 B8 l$ V9 W S5PC100==V1_0 XM1ADDR10.T.1->S5PC100==V1_0 U5.M2! j9 u7 f" Y2 T$ D8 p* h
S5PC100==V1_0 U12.G16->S5PC100==V1_0 XM1ADDR10.T.1
9 N% S9 l/ N# O$ f/ t# {& T: T7 W7 U: x2 S& }
Verify Schedule: VERIFY
1 }$ O/ o$ x2 J# b) r
# Q. f! h5 ~# @) S; @**************************************************************************% ~! G! `" Y9 I6 ? O3 g* ^
c V. ~# q6 r3 |Processing Net XM1ADDR9 in design S5PC100==V1_05 j) _$ p C; J3 M
Date/Time: Wed Oct 24 18:54:42 2012
0 H( T8 w9 L7 E$ E ?9 R O }3 G: F- g: z4 v) \. m
Mapping Pins of Cset: DDR2_ADD_BUS
0 W7 Y1 {; W1 ?) P9 @9 Y! RMapping Mode: Pinuse and Refdes
4 I. b8 p' { N# F/ n2 W
# D8 {' H6 _$ ]$ t+ ]7 X) nCset end point Xnet end point mapping mode
, `; ?; E* g' w& u--------------------- -------------------------- ----------------
- S* U2 x" V$ N/ f8 BS5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.B16 Refdes
7 j; |* B5 a n+ O/ a2 T# @+ fS5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.P3 Refdes
, F! M$ M1 T! x* V# d! KS5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.P3 Refdes
# F8 `; R6 U2 W, h7 }S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR9.T.1 Floating T-Point7 T: M1 k2 p$ ?- W" O3 @
0 D8 \6 l) s. b$ u f* _. n
Net Schedule: Template Defined1 `6 F' b1 E+ F! W
S5PC100==V1_0 XM1ADDR9.T.1->S5PC100==V1_0 U4.P33 }# e7 S: V+ L2 T
S5PC100==V1_0 XM1ADDR9.T.1->S5PC100==V1_0 U5.P3
3 u/ [& @# S: G. o S5PC100==V1_0 U12.B16->S5PC100==V1_0 XM1ADDR9.T.12 G! A' X5 s: A# j4 v
7 i1 q% W- t/ oVerify Schedule: VERIFY1 I3 A8 \9 }6 {# e0 t
3 Y' j( q$ q7 e5 @1 j% S**************************************************************************% P8 U3 s8 @5 ?: o$ @1 D; g
9 P% I& `7 N+ W9 h2 Z, `# d6 u
Processing Net XM1ADDR8 in design S5PC100==V1_0
+ K6 h1 `& `; b/ xDate/Time: Wed Oct 24 18:54:42 2012 N0 y5 \( [5 ?" Q9 A5 L( I
* Z% h% ^/ ~% p# o. P8 DMapping Pins of Cset: DDR2_ADD_BUS( b- M0 A2 n8 {, x' r A
Mapping Mode: Pinuse and Refdes
7 N, Y ~9 B8 A+ X1 h/ e* ?8 Q5 g7 `- v3 f( {3 q1 c
Cset end point Xnet end point mapping mode ! b. {* E0 B' b) e7 E* F! [! ^0 I% y
--------------------- -------------------------- ---------------- p: j0 ]* J8 O7 Y/ k. O3 O
S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.A19 Refdes % v( C! G4 y/ @* d/ ?5 u9 c- b; \
S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.P8 Refdes
/ J! i/ \7 s- f: C0 ^: WS5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.P8 Refdes # s- b' ]2 ^9 m6 H
S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR8.T.1 Floating T-Point7 K! w2 P) p/ [) J' k
$ K- \5 N, ?8 Q, U5 }Net Schedule: Template Defined4 J i. B3 U. _% F
S5PC100==V1_0 XM1ADDR8.T.1->S5PC100==V1_0 U4.P8
/ @4 K, F0 A: s# K S5PC100==V1_0 XM1ADDR8.T.1->S5PC100==V1_0 U5.P89 X' y( j+ z% q4 x% t
S5PC100==V1_0 U12.A19->S5PC100==V1_0 XM1ADDR8.T.18 i+ [% Q" ^( k, m& j! [: {
/ x9 r# t" p4 _! {5 f- jVerify Schedule: VERIFY2 ?! Q9 C8 Q4 ?. Y7 \" t
- n0 X# C/ R" w* A3 q5 g. W
**************************************************************************2 w+ l1 d4 a: ^
, J5 g% [6 f; v4 o8 G( DProcessing Net XM1ADDR7 in design S5PC100==V1_0
" ^$ [2 k2 j$ e/ z! o' ODate/Time: Wed Oct 24 18:54:42 20120 p( M5 B) v6 ]6 L3 Y3 ?( C
" k6 p- Z" y# L8 | u. Y
Mapping Pins of Cset: DDR2_ADD_BUS: s7 g1 R; X) Q* S7 C* T, U8 h, \
Mapping Mode: Pinuse and Refdes4 r0 V! L( W7 E* a" W8 k: |: T6 M
8 g+ |5 B6 I+ m, Z6 BCset end point Xnet end point mapping mode $ ^- f2 t& r e" h2 E& B1 f
--------------------- -------------------------- ----------------
. ?5 P# }! Y- t5 J2 V/ eS5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.B17 Refdes 5 U t2 L* ~6 _3 D( U( e" ^0 z
S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.P2 Refdes , {3 a4 n3 R; r9 s; i1 z/ L
S5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.P2 Refdes $ m4 }& y0 `! O
S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR7.T.1 Floating T-Point. S z! T* I) A! g
- i/ O4 E! V1 c8 Y/ b5 X0 \
Net Schedule: Template Defined
% _! E# `0 [. x" c" } S5PC100==V1_0 XM1ADDR7.T.1->S5PC100==V1_0 U4.P2
, e/ k2 \& [, H S5PC100==V1_0 XM1ADDR7.T.1->S5PC100==V1_0 U5.P25 g7 h$ j$ d5 i v
S5PC100==V1_0 U12.B17->S5PC100==V1_0 XM1ADDR7.T.1
5 m; f9 W7 Z; Y5 I
1 c# O, [2 {) U* m9 q+ ]Verify Schedule: VERIFY
. C" H- a. `2 F; H5 I: |
) P! f. ~; O1 W**************************************************************************3 t8 t$ b4 d1 b' v; L+ D; v
" w( C. A) C4 l
Processing Net XM1ADDR6 in design S5PC100==V1_0
$ L# L; [7 m& p& U8 e$ L s$ GDate/Time: Wed Oct 24 18:54:42 2012
6 k& h' N1 U% E* G4 |3 Q( T
- D8 a+ g# P" S% e! K9 A qMapping Pins of Cset: DDR2_ADD_BUS; Y+ p: T: F: Q$ L( u5 i
Mapping Mode: Pinuse and Refdes/ ]9 M; O% ~( R0 z0 }5 k& I
( L C* E+ {2 f8 q$ N* a' aCset end point Xnet end point mapping mode 8 m1 L' n( T! c- U6 V( V! m
--------------------- -------------------------- ----------------# g2 a4 ` d8 ^8 k1 j: f
S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.G11 Refdes
) S& P7 o- d0 p7 p% d: eS5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.N7 Refdes
* m4 y4 x6 D7 G1 dS5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.N7 Refdes 3 D3 X2 L* B' l2 d9 ^
S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR6.T.1 Floating T-Point& C4 F5 P$ `2 V& n) g- Q
' S+ {% G$ [5 r* I' V
Net Schedule: Template Defined
7 d* G3 E* e! I S5PC100==V1_0 XM1ADDR6.T.1->S5PC100==V1_0 U4.N78 y6 v S. |# q* u) d
S5PC100==V1_0 XM1ADDR6.T.1->S5PC100==V1_0 U5.N7. v4 V+ a; U3 B5 {6 b( j2 q
S5PC100==V1_0 U12.G11->S5PC100==V1_0 XM1ADDR6.T.1
3 |# U+ n+ i5 u1 K1 L$ n+ n6 K: m/ ?/ k( B! B; g3 o( t
Verify Schedule: VERIFY$ E7 \- J( r: G5 Y; r
( y" E4 h; D: y; X f, O**************************************************************************2 I, J0 t/ T$ H2 u" ]. ^8 E
/ ~2 G4 n" g' J. Y6 Y+ c0 eProcessing Net XM1ADDR5 in design S5PC100==V1_0
7 M$ c1 q# k" y) z5 \Date/Time: Wed Oct 24 18:54:43 2012
: q! N: t7 t$ V. ]& I6 c$ g( s3 ~/ C+ A& C
Mapping Pins of Cset: DDR2_ADD_BUS
" R, }, I2 E; Y+ @9 |9 i1 f) N# kMapping Mode: Pinuse and Refdes& C6 _% Y2 O- J+ n# R, _
$ y* ^( Z: ^) O; }Cset end point Xnet end point mapping mode " E m4 Z% |1 l- Q t
--------------------- -------------------------- ----------------
K- F% F$ F6 NS5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.B15 Refdes / f' q! F: ]- S" b% v
S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.N3 Refdes
% E; k( {- ]1 w3 AS5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.N3 Refdes ! u/ f3 N. Q" N& S
S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR5.T.1 Floating T-Point/ O1 {5 p/ I$ P" ?6 Y' B8 l
! Q p, p) |8 ]: m: o
Net Schedule: Template Defined9 B9 a9 d, f- p k1 Z
S5PC100==V1_0 XM1ADDR5.T.1->S5PC100==V1_0 U4.N3
- v b+ P. I& S; A: }& H( U2 A S5PC100==V1_0 XM1ADDR5.T.1->S5PC100==V1_0 U5.N36 g; |# h8 I3 U1 P4 ?$ q0 T
S5PC100==V1_0 U12.B15->S5PC100==V1_0 XM1ADDR5.T.1- b; c3 {' m' i( a1 @# \- B
( ^! R5 |7 n' {9 @! _3 [Verify Schedule: VERIFY, C9 g$ m/ B+ j% R9 G
$ W s8 Y4 F4 O* I2 g" n, ?**************************************************************************: I0 y2 Y. Z# ]4 R
" m2 n3 t5 a6 w- Z+ b8 ~+ J
Processing Net XM1ADDR4 in design S5PC100==V1_0
- r! Y/ K4 V# U8 ODate/Time: Wed Oct 24 18:54:43 2012- m9 ?" t4 A! f
. _, j# _8 N# q, S; M; L9 W" Z$ Z3 aMapping Pins of Cset: DDR2_ADD_BUS' |) U! l9 r- G
Mapping Mode: Pinuse and Refdes
B! A. I; b1 [8 e( Z" Z5 F* S& l2 x; P9 C) x
Cset end point Xnet end point mapping mode % O! w9 L4 p8 @/ P9 s8 q' E
--------------------- -------------------------- ----------------" `1 \7 b; S ^- a$ R2 b3 S
S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.A17 Refdes
" E% X4 D. m. M- J' e0 zS5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.N8 Refdes
$ u& n( t* O# FS5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.N8 Refdes
. W/ y5 E* C" G0 U7 v3 G- YS5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR4.T.1 Floating T-Point$ B+ h0 A! U% h" G
- f$ a* R/ O, Z6 K: H& ] o( I
Net Schedule: Template Defined
6 D" m1 n0 ^2 \* P0 Y S5PC100==V1_0 XM1ADDR4.T.1->S5PC100==V1_0 U4.N88 z0 v$ @, B2 f! D, m; g5 ]
S5PC100==V1_0 XM1ADDR4.T.1->S5PC100==V1_0 U5.N8
+ e! F( l, k0 s: W$ i* n- V8 Y S5PC100==V1_0 U12.A17->S5PC100==V1_0 XM1ADDR4.T.1
+ n0 X) n9 G7 ^$ }% H' {
% ^' H0 [6 h# ]' v* v! Z9 r: t& zVerify Schedule: VERIFY% ?) A, `+ P3 @2 x* `
! J8 }# B5 n2 _ q0 b
**************************************************************************
4 Y+ U% K2 S! g2 N9 l& G/ J* \7 ~4 |' y- k
Processing Net XM1ADDR3 in design S5PC100==V1_0
! i+ K& Y8 E8 O$ x6 z: y$ LDate/Time: Wed Oct 24 18:54:43 2012
3 w* `5 [+ b! F
0 p" v: J- v) k. \Mapping Pins of Cset: DDR2_ADD_BUS8 c! A+ e4 D1 R& [, ?
Mapping Mode: Pinuse and Refdes3 z: U. W0 Z. c7 g& ?7 a
$ n7 i) P- j' B% [
Cset end point Xnet end point mapping mode / z( b5 O' _0 _9 q. x+ d+ v
--------------------- -------------------------- ----------------
" y( O# S, p7 L! h+ W) i5 PS5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.B20 Refdes # {9 K& T0 o! y$ E+ N
S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.N2 Refdes
* d8 m# c j! n3 J% N( ^S5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.N2 Refdes ; i! t: `8 {: ?3 r
S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR3.T.1 Floating T-Point- T- \# {! l! ~' I' m0 F* ~
8 I" i4 l# w) [% Q; l3 e3 Q& `Net Schedule: Template Defined
# x- F; `4 _4 C3 ` S5PC100==V1_0 XM1ADDR3.T.1->S5PC100==V1_0 U4.N2
% l9 J0 q8 r: n S5PC100==V1_0 XM1ADDR3.T.1->S5PC100==V1_0 U5.N2, h- S2 f7 o) I2 F5 Z
S5PC100==V1_0 U12.B20->S5PC100==V1_0 XM1ADDR3.T.18 X' k5 [- ]3 G: L: U9 O0 ]
9 N# I/ d2 d( Q4 y" x' {) V1 P
Verify Schedule: VERIFY. A- t5 p7 P* f( t
# y( `1 q1 D$ E- N**************************************************************************
! O% {/ ?2 p5 A( _$ D% }1 u+ c* k% B9 k1 @9 N. i+ H/ H
Processing Net XM1ADDR2 in design S5PC100==V1_0
! k2 `2 r- {1 r3 [# lDate/Time: Wed Oct 24 18:54:43 2012. x: O9 n4 K0 `; P- t
# `' Q$ P& r- I3 Q! o+ S/ y6 z& p3 t% e
Mapping Pins of Cset: DDR2_ADD_BUS
, E6 |' h3 q. F2 wMapping Mode: Pinuse and Refdes
, y( }) t1 S8 \, o
; ?+ {/ F2 e& C Y. X# \# oCset end point Xnet end point mapping mode 4 w4 ]) c" ^* V
--------------------- -------------------------- ----------------5 Z, v8 Z( B. L, A% P
S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.C23 Refdes % t& V |8 W- S7 f [
S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.M7 Refdes
8 Y) }1 i6 g4 y2 h" mS5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.M7 Refdes
0 _( Y+ L" Z5 ^' {S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR2.T.1 Floating T-Point
* ?5 d |* C) W6 F8 i
+ _8 V. o/ ]+ A, X2 R* x; q! a3 tNet Schedule: Template Defined' a- O/ ] @# j/ g6 q* w
S5PC100==V1_0 XM1ADDR2.T.1->S5PC100==V1_0 U4.M7
+ [" I6 U+ L% o( ]9 O# K S5PC100==V1_0 XM1ADDR2.T.1->S5PC100==V1_0 U5.M77 U0 f% `/ K+ B, ?( V
S5PC100==V1_0 U12.C23->S5PC100==V1_0 XM1ADDR2.T.1
% J9 B: t' `) C' L- }
: B' C# i {8 y$ y# dVerify Schedule: VERIFY+ ?0 [8 C9 t# G, b( E% Z5 f$ g
: Z0 r! d S( U( _& h' B**************************************************************************
; ]) d0 G% t2 g2 W( s1 ~3 g$ w5 Z
% Q# r0 M! U5 {4 sProcessing Net XM1ADDR1 in design S5PC100==V1_02 J. v' }+ w1 G
Date/Time: Wed Oct 24 18:54:43 2012# w v7 H- F! f5 C
8 y. i0 k% j6 J7 |$ B: r& pMapping Pins of Cset: DDR2_ADD_BUS; D1 {; R( {% o: J* G4 t# S+ Y# `
Mapping Mode: Pinuse and Refdes
) t0 U. g9 q" I* g6 A" k4 z5 ]5 I$ A) c5 \$ ]: J( S5 _1 M" F9 H+ s
Cset end point Xnet end point mapping mode % t( u/ n; P8 {, {/ n0 z- U
--------------------- -------------------------- ----------------
9 O- P# w& ]% F; CS5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.C19 Refdes
" m! S- C2 D7 m' | ^S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.M3 Refdes
" a! \% E6 P7 S6 OS5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.M3 Refdes
6 p- R4 c; L0 F7 A" J! a G' |5 `S5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR1.T.1 Floating T-Point, E! e: S4 d, }% `0 S, v
) ^' f4 x* Q8 K' lNet Schedule: Template Defined
9 l5 D% f4 q0 E/ o S5PC100==V1_0 XM1ADDR1.T.1->S5PC100==V1_0 U4.M3
# M& @) F, \: }$ z" i9 s) w7 Y S5PC100==V1_0 XM1ADDR1.T.1->S5PC100==V1_0 U5.M3, e8 W* Y! } R) G8 N h0 |) Z& z) p
S5PC100==V1_0 U12.C19->S5PC100==V1_0 XM1ADDR1.T.1
5 e9 ]' A% P/ a/ N- X5 x5 f
8 B* P& P7 @0 T( ZVerify Schedule: VERIFY/ A: ^: `# h) M4 t; p5 i3 r
. C+ P4 f5 P, C5 p' B+ P" ^/ g**************************************************************************
) }* E! H8 I% i, {+ \0 l( [& D& i2 H# R9 a4 U
Processing Net XM1ADDR0 in design S5PC100==V1_0
5 z, S" g3 |6 W! {Date/Time: Wed Oct 24 18:54:43 2012
2 }3 x: p9 X& ]( V2 A: X. h* }& T" l0 b( Z% g/ u+ @) |6 F& \; l& C7 d
Mapping Pins of Cset: DDR2_ADD_BUS1 s" x. ~6 i5 S$ T% s# \' J- g' y
Mapping Mode: Pinuse and Refdes
' c7 p; K6 O" n5 c1 g
/ s; e: \/ T8 {6 V2 iCset end point Xnet end point mapping mode
. a7 B" {. c0 q) I9 l: v) r--------------------- -------------------------- ----------------- t0 ~9 f. }3 q
S5PC100==V1_0 U12.D18 S5PC100==V1_0 U12.G14 Refdes * c6 ?1 s# W" w4 _" c( f
S5PC100==V1_0 U4.L3 S5PC100==V1_0 U4.M8 Refdes % R2 x- s9 L7 Q+ S2 v. x8 T$ [
S5PC100==V1_0 U5.L3 S5PC100==V1_0 U5.M8 Refdes
, t( y. U6 ?1 J0 g0 r, |$ ^( I$ RS5PC100==V1_0 NET.T.1 S5PC100==V1_0 XM1ADDR0.T.1 Floating T-Point+ H" }7 {9 @ G; r2 _
6 P9 ?& A$ R+ G: ^, h6 L! k/ u
Net Schedule: Template Defined
0 A) f# W: U$ p& W9 l S5PC100==V1_0 XM1ADDR0.T.1->S5PC100==V1_0 U4.M81 b, D' x' c: X# p" l3 L
S5PC100==V1_0 XM1ADDR0.T.1->S5PC100==V1_0 U5.M8
+ H0 |/ D3 K. k; U S5PC100==V1_0 U12.G14->S5PC100==V1_0 XM1ADDR0.T.1
% S4 w% G, l1 x
+ V9 z0 h6 ]0 m$ {( YVerify Schedule: VERIFY1 t: O4 b/ u- @2 B9 O1 @7 U% W
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发表于 2012-10-24 18:56
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