PCB框图有问题

xiang_liling

report提示如下
& r+ X& D# @2 u* ~2 `3 ADesign Name  D:/cameralink_FPGA/pcb/cameralink_fpga_route1.brd
Date  Wed Aug 22 15:38:45 2012
1 P% B( o( O, f: ?' l
DRC Error Count Summary DRC Error Type DRC Error Count
6 v  d& o% j/ B& o: K9 f) A- _Route Keepin 1
# Y& H/ p2 M3 a. TRoute Keepout 4
6 w& n; z* Y1 x6 J5 e7 CEtch to Pad 4
Total DRC Errors 9


Detailed DRC Errors Constraint Name DRC Marker Location Required Value Actual Value Constraint Source Constraint Source Type Element 1 Element 2
8 p" A; M; I' c" {8 s, ]( ]% l& fShape to Route Keepin Spacing (-137.796 178.740) 0 MIL 78.74 MIL DEFAULT NET SPACING CONSTRAINTS Shape "Gnd, Etch/Gnd" Rectangle "Route Keepin/All"
Shape to Route Keepout Spacing (1900.000 4037.008) 0 MIL 0 MIL DEFAULT NET SPACING CONSTRAINTS Shape "Gnd, Etch/Gnd" Shape "Route Keepout/All"
) q3 ~9 u5 O! h5 L# l% HShape to Route Keepout Spacing (-2400.000 4037.008) 0 MIL 0 MIL DEFAULT NET SPACING CONSTRAINTS Shape "Gnd, Etch/Gnd" Shape "Route Keepout/All"
$ z8 d: Q, D; b# |8 e3 H1 RShape to Route Keepout Spacing (1900.000 100.000) 0 MIL 0 MIL DEFAULT NET SPACING CONSTRAINTS Shape "Gnd, Etch/Gnd" Shape "Route Keepout/All"
Shape to Route Keepout Spacing (-2400.000 100.000) 0 MIL 0 MIL DEFAULT NET SPACING CONSTRAINTS Shape "Gnd, Etch/Gnd" Shape "Route Keepout/All"
Thru Pin to Shape Spacing (-2303.150 296.850) 5 MIL 0 MIL DEFAULT NET SPACING CONSTRAINTS Shape "Gnd, Etch/Gnd" Mechanical Pin "Outline."
Thru Pin to Shape Spacing (2027.559 3840.157) 5 MIL 0 MIL DEFAULT NET SPACING CONSTRAINTS Shape "Gnd, Etch/Gnd" Mechanical Pin "Outline."
& G4 d8 L2 N  r. TThru Pin to Shape Spacing (-2303.150 3840.157) 5 MIL 0 MIL DEFAULT NET SPACING CONSTRAINTS Shape "Gnd, Etch/Gnd" Mechanical Pin "Outline."
% r- J& b9 x  q& b# D- {9 jThru Pin to Shape Spacing (2027.559 296.850) 5 MIL 0 MIL DEFAULT NET SPACING CONSTRAINTS Shape "Gnd, Etch/Gnd" Mechanical Pin "Outline."

香雪海

这是drc报告和框图有什么关系