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在 Logic与Layout 导入时提示以下内容怎么解决？
. }3 L* D3 m8 E! [; ~8 ?9 @======================================================================' t2 a0 I- S' w' ?) m- | s6 \. D
9 X: r! s6 h3 z1 `. z; @9 `4 GDatabase Integrity Test Report on file SPS.pcb -- Sun Jul 08 13:53:46 20122 l- u* l' n) E0 q9 _2 Q+ ^
* ^# D% _% L( K0 \' N" E======================================================================2 l9 R- Z! x& \* j
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ERROR: Component R11 (Id: 10) has box outside design space$ j; X/ \0 ]# a2 E2 X
(-16002.5, -16019.72) (65, 45) R: F. L1 g0 B3 {5 G
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ERROR: Component R4 (Id: 15) has box outside design space
4 [; M9 t+ f, ?* ]+ L) R% s (-16002.5, -16019.72) (65, 45)! P# y; x) ]3 j, `& I. I! |
1 U, a: q. A, JERROR: Component R5 (Id: 17) has box outside design space
3 Y) C/ T, F& j! C2 R z (-16002.5, -16019.72) (65, 45)
1 }% Y1 j, x0 W9 Z: _. Y; J/ M. P: ^- P4 E6 p7 l
ERROR: Component R8 (Id: 24) has box outside design space
: l4 L! m+ ]! H+ K (-16002.5, -16019.72) (65, 45)( r. ?) C: x5 t. h
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发表于 2012-7-8 13:55
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支持！
反对！
楼主