菜鸟求组:仿真multi-threshold cmos,实现NAND gate

ak11112222ak

source 总是出现以下问题，描述的时候已经说了是接地的了啊，为什么还是会当作断开的呢？
# c+ w9 v" T$ g+ \" }% T6 FCircuit: *Main mtcoms file

  d8 B3 L0 Z) I( o% sWarning: There are nodes with less than 2 connections.
The table of nodes with less than 2 connections is generated after sourcing...

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, d9 L* t) _- s! A***warning***: the following singular supplies were terminated to 1 meg resistor
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- I3 F0 O5 O. y7 u& I- Nsupply       node1            node2
" Q, I" R# |0 G2 i/ yvdd           vdd                  0
5 S" H9 X0 a# }; ]* }0 jv1           a                  0
! F) D0 U; {% I& N6 p* t2 q. i1 s" B. ?v2           b                  0
1 u2 Y/ u3 ]3 V! d1 P' rv3           sl                  0
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The following nodes have less than 2 connections:
-------------------------------------------------------------------------------------
# r& Y8 |, w2 [7 `$ _3 V* U| sl                 | b                  | a                  | vdd                |
; v( l) P. K& B7 g-------------------------------------------------------------------------------------
0 M5 \; ?: c8 [: B* S一个描述netlist的文件：

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: V8 i/ Q; B* ~" o' x' h6 K* SPICE export by:  S-Edit 15.13
* Export time:      Tue Jun 12 11:15:52 2012
$ M$ Z+ k" w: G" L* Design:           mtcoms
: _: w( f+ }8 l6 E# _& E2 {* Cell:             Cell0
* InteRFace:        VResistor
( t# ?6 ]' ]7 s+ i4 q1 A* View:             VResistor
* View type:        connectivity
8 k) C& A0 k9 r2 [  \* Export as:        top-level cell
* n, ?1 U, e  j  X/ Z* P( p: C, I& E6 c* Export mode:      hierarchical
, x5 |) h7 ^6 o% Q4 Y! P* Exclude empty cells: no
$ I$ ?$ X0 e  {. F3 f5 N! ^/ l* Exclude .model:   yes
) l( {6 n: x* ]* Exclude .end:     no
* Exclude simulator commands:     no
* Expand paths:     yes
5 p- ]# r) S8 w3 a; W) }* Wrap lines:       80 characters
) T! X" u0 G4 r+ b6 h* Root path:        \\en-file\users\houx\Profile\Desktop\ankun_dong hw2\mtcoms
* Exclude global pins:   no
* Exclude instance locations: no
& K/ I6 m" @" V+ F  @* Control property name: SPICE
* o! F% y$ Z" A9 }2 |, o! g& @: S" ]
********* Simulation Settings - General Section *********

9 X7 G& e! h/ J8 j*************** Subcircuits *****************
+ f  C, `3 S" s. h& o.subckt INV A Out Gnd Vdd  

*-------- Devices With SPICE.ORDER < 0.0  --------
* Design: LogicGates / Cell: INV / View: Main / Page:
& w* t9 X/ F' T8 j: Q* Designed by: Tanner EDA Library Development Team
& n  v3 i' @$ X) e; [1 U4 C1 m9 ^* Organization: Tanner EDA - Tanner Research, Inc.
6 y5 ~1 _- B- Z- f& y5 c7 V$ ]6 Y* Info: Inverter
' M0 p- `; K- x/ B. |* Date: 06/13/07 16:17:11
/ p* n" u( D# p, B6 [$ g$ Z3 F1 b* Revision: 3 $ $x=7600 $y=600 $w=3600 $h=1200

  ^, Q( o+ k# r! }/ b*-------- Devices With SPICE.ORDER > 0.0  --------
MN1 Out A Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $ $x=4600 $y=2600
/ L. @1 _- J0 Z1 Q2 s# W+$w=400 $h=600
9 ]- f* y5 [+ o8 A6 }1 }MP1 Out A Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p PD=6.8u $
6 }: W0 q' g7 W+$x=4600 $y=3600 $w=400 $h=600
% ]( \/ w) ^# ?2 i) r9 e.ends
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8 _9 {  L/ }& r/ T. C) g: n

*-------- Devices With SPICE.ORDER == 0.0  --------
***** Top Level *****
2 c" c- K  K2 m$ A9 ]5 f) n( K$ yXINV_1 SL N_2 Gnd Vdd INV $ $x=350 $y=-2300 $w=900 $h=600
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*-------- Devices With SPICE.ORDER > 0.0  --------
0 K4 ^1 A9 u) M5 I% KCCapacitor_1 VDDV Gnd  1p $ $x=3100 $y=-400 $w=400 $h=600
: F) x) e2 k* |; j. SCCapacitor_2 GNDV Gnd  1p $ $x=3100 $y=-2500 $w=400 $h=600
MNMOS_1 Out A N_1 N_1 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $ $x=1100
+$y=-800 $w=400 $h=600
) v2 ^. ~+ ^& S7 `MNMOS_2 N_1 B GNDV GNDV NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $ $x=1100
8 n  j! w- [8 C4 C6 c: j! W0 F$ o8 g+$y=-1500 $w=400 $h=600
5 p( t( a" P3 a$ P" U+ _8 }MNMOS_3 GNDV N_2 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $
/ |+ Q* u. C' l4 @. @! ?0 b+ \+$x=1100 $y=-2300 $w=400 $h=600
- Y2 c, [' k1 f4 d" r; F' {9 s  ?MPMOS_1 Out A VDDV VDDV PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $ $x=300
+$y=-200 $w=400 $h=600
MPMOS_2 Out B VDDV VDDV PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $ $x=1900
+$y=-200 $w=400 $h=600
. x" a7 z( D4 E' S: {MPMOS_3 VDDV SL Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $ $x=1100
+$y=700 $w=400 $h=600
7 Q( x& n6 ^% {! L3 {  x: m  B0 Q
********* Simulation Settings - Analysis Section *********
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/ ]5 S. @+ p3 f- Z********* Simulation Settings - Additional SPICE Commands *********
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8 U$ V3 d4 v( c0 C4 u! v: ]; V6 v! q.end
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icy88

source接地的描述应该是 vdd vdd 0 0,你后面少个电压的值