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错误如下
3 U3 f2 V3 Z. ^, z, b' zERROR ack:679 - Unable to obey design constraints (LOC=CLB_R38C1.S0) which" b! |2 c1 @" R% y/ u% A
require the combination of the following symbols into a single SLICE. L4 ^4 d# p5 X+ ^+ u0 k1 Q6 |
component:
' B- u# Y- {" C1 ~% N& R9 x# f# k4 r8 V FLOP symbol "Chain[37].uChain/Node[0].uNode0/uFdce" (Output Signal =
6 ?0 H. y: L: B. P* f Chain[37].uChain/wOutA0<0>)$ `( j3 |/ F( n7 g" d
FLOP symbol "Chain[37].uChain/Node[0].uNode1/uFdce" (Output Signal =
* e4 r, D) N6 x Chain[37].uChain/wOutA1<0>)7 U: q. ?8 W) w- E- ]6 h
The set/reset signal Reset_IBUF_1 of register/ @. u1 T! ~+ `& |# E8 I- R* x
Chain[37].uChain/Node[0].uNode1/uFdce doesn't match the existing usage of the
4 \. q& V% g: j, a- M, P' l SR MUX. The signal Reset_IBUF_2 already uses SR. Please correct the design
& `' X6 B0 L K. ?/ v" E4 z8 H* [ constraints accordingly.1 j0 B2 @' C' \* [( i$ n
请大侠帮忙 |
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发表于 2012-6-8 17:35
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淘帖
支持！
反对！