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DATE: 02-17-2012 HOTFIX VERSION: 016
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# _7 ?7 a( k% g" yCCRID PRODUCT PRODUCTLEVEL2 TITLE
" ]- Z8 r- Z$ {===================================================================================================================================
, h/ \. w0 u) Q" T6 o, Q840105 PCB_LIBRARIAN USABILITY PTF subtype is getting changed when Save As option is used in PDV
) m7 p" `* A. B6 s- g% G873075 Pspice PROBE Decibel of FFT results are incorrect.% n1 V6 f# r4 H2 T
938744 ADW COMPONENT_BROWSE Need ability to customize shopping cart columns to include any Part property
" t; m* ]2 X- q ?; s943003 SCM REPORTS The dsreportgen command fails with network located project: A( {0 i/ v( k8 J
961530 allegro_EDITOR INTERACTIV The problem of Display measure command
0 ?" E; k- x. w) i6 x3 o) V* ?962157 concept_HDL CORE Where is the setting for enabling the Enable PSpice Simulator menu?
& u9 K k- {% r# N962206 CONSTRAINT_MGR CONCEPT_HDL Import physical not passing all constraints from the board to frontend
$ j) L& T) l0 B$ e) Z968205 PSPICE DEHDL_NETLISTER Change SPLIT_INST property to PSICE_SPLIT_INST for Quad Switch type of design.: X' {# n7 B6 v# e
968509 PCB_LIBRARIAN METADATA Incorrect pinlist.txt was generated if DIFF_PAIR_PINS_POS/NEG was set./ Q) @- U1 @' S
969450 LAYOUT TRANSLATORS orcad Layout to Allegro Translator crashes6 E8 A- l- j( {" U8 C
969997 CONSTRAINT_MGR CONCEPT_HDL ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance pro~% @( z+ ~) K6 l, \% K7 ^
971193 CONSTRAINT_MGR UI_FORMS Copy and pasting a formula causes the application to crash on windows.' @& T( V0 `0 w9 k& |
971601 CONSTRAINT_MGR CONCEPT_HDL ERROR(SPCOPK-1053) and WARNING(SPCODD-66) because of directory structure2 x5 Q/ \" S$ V/ L1 P# Z4 i
973398 CONCEPT_HDL OTHER It should be not packaged with error while working the packaging process if the design has a ERROR
- a& `% E: M0 j1 g2 y4 L973859 PSPICE ENCRYPTION Pspice crashes with encrypted model
7 h. U* o/ _/ V973938 PCB_LIBRARIAN VERIFICATION pc.db is missing% h' e& w- V. Z4 \; Q/ w5 k% Q
974540 CONCEPT_HDL CORE Graphics updates are real slow7 j( K% T5 y% s% l( ~/ O, d1 M( V
974791 F2B DESIGNVARI Variants are not back-annotating to schematic and turning to ?% J6 m: c7 V& J9 O6 N" `; C
974818 ALLEGRO_EDITOR NC Backdrilling produces 0 plunges yet no errors reported.0 I8 D i# N! V5 k
974945 ALLEGRO_EDITOR skill Why is axlPolyOperation is giving different result and not working
! r3 i( K$ G1 H( @974946 MODEL_INTEGRIT TRANSLATION ibis2signoise returns the error - Delay measurement fixture must contain V for ECL technology
# y5 W1 r, H4 j0 a975396 CONCEPT_HDL CONSTRAINT_MGR Constraints are dropped after migrating from 16.3 to 16.55 N+ ?/ V7 [$ \6 ]! A
975633 ALLEGRO_EDITOR GRAPHICS 'dynamic_layer_visibility' option in 3D Viewer when checked or unchecked should not change (until next change)
- n5 i) S1 K( G9 ]975720 ALLEGRO_EDITOR DRAFTING Datum dimension lines not adjusting to text move; {# d; S3 O% ~: @: P* O- T; g% X
975745 ALLEGRO_EDITOR SKILL cdsServIpc different 16.2 vs 16.5 when Allegro exits
5 X0 E- ?; L! H976013 CONCEPT_HDL INFRA Power pin connection of FPGA symbol is missing in netlist.
7 X) d3 D( A. F. Y' Y976058 CONCEPT_HDL COPY_PROJECT SCM Copy project does not create the con and dcf files in tbl_1 views" R' A5 Z/ g' K; w
976073 CONCEPT_HDL COPY_PROJECT All the constraint data is lost in the SCM copied design
! t% A2 I7 L$ s$ z7 |) {976160 CONCEPT_HDL CREFER Cref fails due to some Caeviews error in the design
% W C% s+ K* w1 r( `* H/ N976204 ALLEGRO_EDITOR DRC_CONSTR Application falsely reporting Mechanical Pin Antipad to Shape Spacing DRC0 K' d V; L' }( V9 Y. j& F
976448 F2B PACKAGERXL ERROR(SPCOPK-1069): Invalid POWER_GROUP property value4 ^0 D$ o$ e2 r2 W6 G5 @* {* Q
976521 ALLEGRO_EDITOR DRC_CONSTR multi-thread update DRC causes the application to crash
1 j( K( Y. F) E& h3 U* }# [1 _/ _976838 SIG_INTEGRITY OTHER Unable to create XNET for highlighted nets on attached database even after assigning proper Signal Models.$ Q9 i( F5 x6 @
977517 F2B PACKAGERXL Export physical fails after update to 16.5 from 16.3
; ]" u# p8 N3 p6 ?977902 ALLEGRO_EDITOR DATABASE generate module is crashing allegro/ u7 W% @8 o9 [5 g6 o0 [; M, v
978652 ALLEGRO_EDITOR pads_IN PADS_IN fails with ERROR: Finished with errors.7 ~% B$ O1 _! G, N0 J
978744 APD DEGASSING Some shapes will not DeGas on this design& g' T' s w0 y7 T- q/ N
979940 SIP_LAYOUT OTHER SiP Layout Leadframe autobonding with profile selection6 [& Y! { _! K- S& j5 D
981699 CAPTURE HELP Start Page still shows Hotfix 14 after installing Hotfix 15" n8 e- T& A9 H. J& m$ ~
6 F& Q" {2 B" U# V5 f! E) T
DATE: 02-03-2012 HOTFIX VERSION: 015
# T0 F) p( j: G5 W===================================================================================================================================- I7 P+ F, u0 K; J0 X0 p
CCRID PRODUCT PRODUCTLEVEL2 TITLE
# d- p. _+ S. o0 R, v===================================================================================================================================
1 t" O. M. a7 G$ [* _871567 CONSTRAINT_MGR SCHEM_FTB Ability to filter out Single Node Nets from Constraint Manager
' ~, H1 E5 z" m2 s921436 ALLEGRO_EDITOR MANUFACT Change in 'decimal place' for new dimension changes the already placed dimension
6 V9 Q/ H% k! b1 t5 m3 j- P3 Y941433 CONCEPT_HDL COPY_PROJECT 16.5 Copy Project should warn if trying to copy a 16.3 design; W& P! i7 l$ N. D+ [
954375 ALLEGRO_EDITOR MANUFACT Change dimension accuracy for few instaces of associative dimensioning# L* D5 H4 I/ E, o4 g/ R0 \9 |
961646 PDN_ANALYSIS EMVIEWER EMViewer Help > About shows wrong version$ J. y& _0 W8 {# w: P- N
964912 CONCEPT_HDL COPY_PROJECT ASA project crash after using copy project
+ G! ~) g8 W3 X. S/ `' U* J967223 ALLEGRO_EDITOR MANUFACT Bug:Oval slots orientation in one direction only
( c5 I* m, e( y3 S- I, g- S968865 SIP_LAYOUT DIE_ABSTRACT_IF load of die abstract fails due to differences between component and symbol
: F; c+ J! z: n; R7 ~8 m: D969485 ALLEGRO_EDITOR SHAPE Shape does not update correctly in 16.5
# c6 S0 Z7 h" o970331 CONSTRAINT_MGR ANALYSIS Impedance worksheet shows a zero value for impedance2 K w& j- _9 o9 _
970600 SIP_LAYOUT SYMB_EDIT_APPMOD Option in Die Editor to be able to "physically swap" pins3 Z6 _2 V X4 b
970910 F2B PACKAGERXL Our customer has problem with pin color after pxl 16.5.
2 o o. P* U6 W" W: i970970 SPECCTRA FANOUT Fanout Vias is placed far away from decaps and does not change the Fanout length even when max_length is reduced. N9 {8 R* M# y9 a: y& k4 ~
970985 SIP_LAYOUT OTHER Importing a .spd2 database file using NA2 will cause the APD/SiP tool crash/ F7 @0 [ x5 d: i
971757 CONCEPT_HDL INFRA Crash while Saving/Packaging the Design
1 X- h# C6 x: ^. c% r! ^0 \. v& ^971923 ALLEGRO_EDITOR MANUFACT Allow to change decimal accuracy for dimension instances8 @* X1 p: O! I0 M* F9 x
972568 CONSTRAINT_MGR UI_FORMS Tools >Excel missing from CM; M. ]" Z" z- H! y2 F) }0 M+ z
972821 CONSTRAINT_MGR CONCEPT_HDL connectivity server warning: Unable to add property WEIGHT+ J) R6 o' ]( F0 m- @* x
973185 SCM CONSTRAINT_MGR ASA2 block not seeing all instances in a package.- N$ v& |2 B) N
973211 ALLEGRO_EDITOR INTERFACES IDX Object Type Change not recognized
' M# R0 o4 ^7 s973214 ALLEGRO_EDITOR INTERFACES IDX import package keepout height value change assigns incorrect value& C8 B! o6 N0 \& o. Z) O
973384 CONCEPT_HDL CHECKPLUS The multiple SIG_NAME has to be occurred an ERROR at the SPB16.5.
& T# S O$ p9 O b973514 SIG_INTEGRITY OTHER Mapping error when Ecset is updated to constraint manager from extracted net1 X$ I! T' H& M- C$ I' t" Q
973950 ALLEGRO_EDITOR SHAPE Update to smooth crashes application
( l# ]0 O3 r2 c974533 SIP_LAYOUT OTHER Crashes in Edit > Die Properties and obviously has a setup problem.7 |% }3 c) f1 c8 J( Q
974809 ALLEGRO_EDITOR SKILL argument available for hiding a property with function axlDBCreatePropDictEntry is not working
% Q3 {* R. L- s0 S- L3 h976179 INSTALLATION ISR Installation of ISR S014 to 16.5 on windows is breaking the documentation index
. V* e5 f9 i, c& }5 D. a; p4 S
3 }, r. |6 O2 ^+ _- nDATE: 01-20-2012 HOTFIX VERSION: 0148 a% [) c. z1 V2 Q# f
===================================================================================================================================
- r9 B8 |9 F% ]+ H2 v9 z4 ^CCRID PRODUCT PRODUCTLEVEL2 TITLE3 X/ @; ?, C( [( a, M# x# `
===================================================================================================================================, x4 E: `# y( N
733285 PSPICE SIMULATOR Enhancement:In server-client installation use existing index file from server6 l; F, S/ E& N0 ^5 |: s$ ^* y( H
941020 SIP_LAYOUT OTHER Soldermask enhancement
% F! F9 V- S9 d2 F5 z& C3 ?6 X946407 CONSTRAINT_MGR TDD When is it safe to open a 16.5 design in 16.3?- a3 G1 d% G" P5 q5 b
953067 CONCEPT_HDL OTHER Variant Editor "Error/Warning messages" form is unusable4 o% q. v8 j1 |. g" w$ `
954818 CONCEPT_HDL COMP_BROWSER Replace button turns to Add in component browser when a component replace is done on the schematic
R/ O5 f- k1 x; o956450 ALLEGRO_EDITOR DRC_CONSTR Analysis always shows analysis failed in uncoupled length in some diffpairs7 }6 r* ?1 } e m6 |5 ], p& X
958259 F2B DESIGNSYNC ds.exe crashes on a big design when accessing the design from network drive
( z: f8 `5 c s958395 ALLEGRO_EDITOR SHAPE shape voids won't merge, h( r9 U6 @1 H. ]. p3 q( Y
959212 MODEL_INTEGRIT PARSE Attempting to use "Mark qualified" option on DML File results in dmlcheck and Modelsim wanrings.
8 x% v4 U" S$ k5 J7 X959940 APD AUTOVOID Void all command gets result as no voids being generated.
/ a$ O0 P- W+ v9 V960252 PCB_LIBRARIAN CORE Splash screen in PDV prevents showing error message! i& E3 u0 s) o1 S7 F! a8 R( K
961634 PDN_ANALYSIS EMVIEWER Cannot launch PDN EMViewer from withing PCB SI9 b0 {9 h, b) {, c- o
961645 PDN_ANALYSIS EMVIEWER Standalone EMViewer will crash when opening any result file in the form of *.emv file.; G. z7 V# |2 q( b+ o8 w
961700 ALLEGRO_EDITOR SHAPE dbdoctor reports ERROR(SPMHUT-144): Illegal arc specification1 }0 F. y8 S4 b8 e
961733 ALLEGRO_EDITOR SKILL Allegro crashes. Appears to have a memory leak.' R% m2 ^6 ~" z
961758 ALLEGRO_EDITOR DRC_CONSTR DFA check produces no DRC when the dfa bounds are not a rectangle.
' e2 N& p/ O* P7 h# w961887 CONCEPT_HDL CONSTRAINT_MGR Match Group created from ECSet cannot be deleted in the same session of CM: B8 z' ~. O" V6 o; p* R* x
962552 APD EDIT_ETCH BUG:APD crashing when we try to slideget information but move works fine
; L- L- |/ e- s. K$ l0 o* t962869 CAPTURE STABILITY Capture crashes after RMB click on rotated parallel wires
0 B( p) i3 N5 U/ _963232 CAPTURE MACRO Macros not being played in Windows7
0 y5 h8 X: n! p; @" Z0 o: c: z2 C963300 ALLEGRO_EDITOR DATABASE Create > Module crashes in 16.5 but not in 16.3' ]* U! ?: K1 d
963651 CONSTRAINT_MGR CONCEPT_HDL ECsets are renamed after packaging on linux, L2 c! i9 I0 B% ?; {% | P
963663 CONSTRAINT_MGR ANALYSIS Q- Why the customized worsheet for Diff pair Impedance not analysing at all for this SIP design
5 d1 ]- ?4 Y/ u! C/ M/ L963715 SIG_INTEGRITY OTHER Application only adds the bottom conductor thickness for the via z-axis length
$ T9 X d+ f4 y) H- Z/ i: w; z964068 ALLEGRO_EDITOR INTERACTIV Allegro crash when using move alt sym mirror alt sym...
9 D8 O: o v; }, t: T+ `1 ?& R964267 CIS PART_MANAGER Capture become non-responsive, working on Part Manager and creating CIS BOM, for large designs- P' \* S- |9 }8 E/ E! p
964597 ADW LRM Issue of LRM license checkout after renewal license by 16.5 (ADW15.5_S23+SPB16.3)+ d+ v' E8 G) b) m2 b E6 F" t+ v
966148 APD INTERFACES Character Limit for DIE Files (*.die) Import$ X1 B6 |0 s: G0 u( G! {
966416 F2B PACKAGERXL Cannot package this design, r1 U. J R+ a1 T6 X* i6 ^" j+ i
966421 CONCEPT_HDL CORE DEHDL Crash when applying property on components in duplicated blocks
1 F: ?2 j/ _& R9 X- p$ j966693 CONCEPT_HDL CORE DEHDL crashes when doing model assignment if CM is open
0 B C* T k/ d, a- v; s3 ?966795 ADW ROLLBACK rollback utility does not honor -product option from command line1 k# X5 j3 j0 P6 \
967089 SIG_INTEGRITY OTHER Matchgroups created by ECSet not deleted when ECset is removed from object.; H; p/ `' q9 Y4 E
967222 ALLEGRO_EDITOR OTHER PDF export is leaving data off the drawing
- G- \2 u S- o5 G967240 SIP_LAYOUT WIREBOND Change default bond fingers selected on multi-site leads during "bond to leads" program2 ]4 c3 E0 f4 i5 m$ g5 l! x3 V
967297 ALLEGRO_EDITOR OTHER Dynamic Fillet&Eliminate unused stacked vias cannot be used as the Miniaturization option.
4 V6 E5 H& @& V7 y967576 CONCEPT_HDL CREFER Occurrence location property values do not appear in flattened schematic generated by CreferHDL
* m( M% ~4 X1 \968096 ALLEGRO_EDITOR DRC_CONSTR Mechanical Pin to conductor spacing is not followed.0 ^5 J& P7 S; d* U
968222 SIP_LAYOUT DIE_EDITOR die pin loses IC net for a co-design die with multiple ports within IO-cell
3 H4 H1 h0 x) ?. D# i968358 CIS PART_MANAGER Capture crash on removing a part from subgroup in part manager$ @# Y r& l3 a; w
969594 CONCEPT_HDL CORE The dcf file is not updated with schematic changes( P" ^- w* z2 h% c% U" C
* Q) l4 ~' J) \, O- O$ HDATE: 12-16-2011 HOTFIX VERSION: 013' o3 v. Z; H8 ~" }5 w: q! l
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
9 `% D& E) r; D4 o9 ^' m===================================================================================================================================- l# l) f, O$ H/ ^, L) d, u
875695 SIG_EXPLORER INTERACTIV Enforce Causality check box doesn't work.1 C8 Q* T2 H( W, @: o4 [! u
927148 CAPTURE PROJECT_MANAGER Capture crashes on creating scehmatic folder with name which already exists in design
( _+ F& W2 O1 d6 P' e/ T7 |. }- L5 @938013 CAPTURE NETLIST_OTHER The netlist in RINF Format contained two identical lines for PCB FOOTPRINT
9 ?3 ~% u7 b3 F3 l6 s7 c941409 PSPICE PROBE BUG : Search accuracy wrong in new cursor window
. }. e* ?4 p$ z3 y" n, u% f945242 SIG_INTEGRITY SIMULATION Unable to select "shapes" in find filter for 'show parasitic ' command( D( o" X* V* v1 h3 ~
946293 CONCEPT_HDL ARCHIVER Archiver hangs if there is a whitespace at the end of the path of cref.dat
! F9 W& L p2 N1 M8 ^946770 CONCEPT_HDL CORE 揤iew Design� function is missing in Windows Mode after reseting the menus.' F+ g2 I( o: m% O
950994 CAPTURE NETGROUPS Problem in expanding the netgroup in Auto Connect to Bus function t* W* p$ C' |& F c
953530 SIG_INTEGRITY GEOMETRY_EXTRACT Display Parasitics is displaying wrong results for EMS2D Field Solver compared to topology extraction using Probe.3 S: j) F: P% E
953713 CONCEPT_HDL PAGE_MGMT Random page replacement/duplication in block
0 g+ J; V2 K# s953917 CONCEPT_HDL ARCHIVER archcore should handle errors correctly$ f! R8 |$ F' z3 t" x
953971 ALLEGRO_EDITOR MANUFACT NC Drill files not generated correctly when using the option "搒eparate files for plated/nonplatedholes�% F) J$ o" Q5 G! m
954400 CAPTURE NETGROUPS BUS members of NetGroup are getting converted to Scalars in Export-Import NetGroup.6 n2 W* j6 p7 [" e9 B4 `
954498 SCM B2F SCM crashes when importing physical( J7 _7 F0 _# O
954623 ALLEGRO_EDITOR EDIT_ETCH Unable to complete connection with Add Connect - related to soldermask to cline check?& }# Y( E* A+ g" z5 i" y
954894 ALLEGRO_EDITOR MANUFACT Dimensions disappear when opening database in v16.5 from v16.3
* [& J, w$ u9 @7 |2 h% I955029 CONCEPT_HDL CORE custom text font size not recognized in symbol view6 J5 G. C A! i' n
955133 SIG_INTEGRITY FIELD_SOLVERS The Field solver creates the differential trace model which is reversed T(D1) and T(D2) of bottom side.
# `7 X& s1 S8 d# a. {955290 CAPTURE DRC Description for UPD0014 missing in the Browse DRC markers window$ X0 _9 P9 b# \
955299 ALLEGRO_EDITOR DRC_CONSTR drc text to smd pin does not work any more on this database in 16.3 S039# \' u+ A$ j3 _1 w* h# ?+ t
955338 CONCEPT_HDL CHECKPLUS Need to change PART_NAME; n- d; D, Y7 v, _8 g! S
955447 SIG_EXPLORER OTHER Model path set in DE HDL Model Assignment not used by SigXP from CM in DE HDL
- D% C- J( S3 T* n9 V955740 SIG_INTEGRITY GEOMETRY_EXTRACT Crosstalk with Timing Windows does not work correctly
; @. x* D7 H- o$ b: L) b* [955749 ALLEGRO_EDITOR MANUFACT show element Info shows symbol dimensions on incorrect subclass! p1 u. F! a0 H
955912 ALLEGRO_EDITOR OTHER Shapes with voids that are exported to PDF have gray filled area over the void& K$ P, A* k$ ]8 r
956129 CONCEPT_HDL INFRA DEHDL uprev hierachical design from 16.2 to 16.5 packaging failure.
5 j, p6 U. e* K, V1 n& _9 P956373 ALLEGRO_EDITOR NC drawing name doesn't display in the log file" S6 p3 B K$ g. j
956393 CAPTURE PROJECT_MANAGER "GENERAL" and "TYPE" tabs are missing from " roperties" dialogue box. x" Z* W# O# m. l% y
956448 PSPICE MODELEDITOR Can not generate a DEHDL symbol from Model Editor, because no Capture license found
' l# Y; b8 c2 N) Q7 Q% i956456 CAPTURE NETLIST_OTHER OrTelesis netlist not transferring user properties defined under combined% k3 j: [- u- _3 d* `1 c- q
956489 ALLEGRO_EDITOR MANUFACT dimensions lost when symbol with diemnsions attached to symbol origin placed on board+ [6 o/ M7 T, q8 r
956603 CONCEPT_HDL OTHER Part Manager "has stopped working" after changing a component
7 w- T6 @+ \/ U9 c. q' p/ m956751 ALLEGRO_EDITOR ARTWORK Import Gerber command does not work correctly" \8 B7 p' D2 _: [7 L6 I5 S T
956847 PCB_LIBRARIAN METADATA PDV - Partdeveloper symbol to function linkage broken/changed in 16.5 y: j3 I/ ?7 Q( x; _
956987 CAPTURE OTHER Find from "Search toolbar" doesn't gives complete results& c B3 F2 ]. d( ?' l* [. G! n0 z0 G
956996 CONCEPT_HDL INFRA Correction to ERROR(SPCODD-7): Following Primitive instance causes CM to empty& t8 D1 e8 L$ x) s
957009 CAPTURE NETLIST_OTHER Problem getting database property in mentor PADS PCB netlist! N8 P- I: b; p
957137 APD DXF_IF DXF out command dose not work correctly.: M' h) F% f0 G7 p' h, K
957167 APD GRAPHICS Highlighting for Static shape with display_nohilitefont environment variable.
, \9 Y& o3 @6 z* t957232 SIG_INTEGRITY OTHER Allegro crash during Model Assignment.+ I$ m" `: ~2 M
957267 CONCEPT_HDL INFRA Packager Error after Import Design' W: A' v1 P! x; u) O, x
957866 SIP_LAYOUT DATABASE Cavity outline is not getting deleted from symbol file
9 f: j2 x: a% ]$ P958010 ALLEGRO_EDITOR REPORTS Wants the ability to extract "Batch" reports from Partition ".dpf" files.
) W- [$ g, X8 ]) l4 P# U' ^958252 ALLEGRO_EDITOR TESTPREP Resequence testprep with the option - Delete probes too close crashes the design
7 T" t6 I9 R- d( \958253 ALLEGRO_EDITOR REPORTS Shape did not have thermal relief connected to pin but unrouted nets still shows zero.* N( ^# K# U6 |. ^5 s: q
958433 ALLEGRO_EDITOR DRC_CONSTR False embedded component DRCs
! Z* h5 W" a1 T8 F! m- c958753 ALLEGRO_EDITOR SHAPE Dynamic shape is getting corrupted in 16.5
9 e6 F X# _1 ^4 y959011 ALLEGRO_EDITOR OTHER copy problem of via and cline
: z( X0 O, X- ~. j" ]( q4 K959101 ALLEGRO_EDITOR EXTRACT Using extracta with excluding Thermal reliefs
: ~! R7 p' L/ ]; ?959253 CONCEPT_HDL INFRA Design will not open
6 p% }* A9 k: d( m2 N959299 APD MODULES Getting ERROR(SPMHDB-279) when trying to update modules placed on the Top side% m [/ a3 J- l! X9 a5 E8 g2 n; j
959884 CONCEPT_HDL INFRA Design Uprev/concept2cm crashes with Application Error/Out of Memory Error.3 O' C* T. i& ^+ M: ~
959909 ALLEGRO_EDITOR SCHEM_FTB Site level propflow.txt file is ignored property is transferred( J( ^: R- j$ G/ L
960067 SIP_LAYOUT PLATING_BAR Creation of plating bar removes "NODRC_ETCH_OUTSIDE_KEEPIN" property from the clines.3 N7 t0 i: v. w( [
960126 SIG_EXPLORER EXTRACTTOP Allegro PCB SI license is used automatically at Topology Extraction of Allegro Physical Viewer.
. r0 E! G1 G/ I9 T, d6 V960143 SIG_INTEGRITY GEOMETRY_EXTRACT Running simulation in Bus sim happened crash while enable Coulpled Via model to S parameter
& s- t+ l2 y) m% H961349 CONCEPT_HDL HDLDIRECT Motorola designs have broken connectivity compared to 16.38 Y6 P" t* h* ?: }0 R; T7 r- s
961816 ALLEGRO_EDITOR INTERFACES Normal Export > DXF fails and offsets the pins of the BGA symbol6 P0 C' t9 U# o* D% g1 o
962519 SIP_LAYOUT WIREBOND Align option doesn't work for wb_tackpoint fingers
# r7 ~/ ^$ A! n2 I7 o1 k3 v) u
" Y: S9 M9 T9 P% W+ J3 q# zDATE: 11-30-2011 HOTFIX VERSION: 012
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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% P5 Z* I- }# y959581 CAPTURE NETLIST_OTHER PCB Footprint is getting replaced by VALUE in OTHER netlist formats
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DATE: 11-18-2011 HOTFIX VERSION: 011' e: K/ v8 l& S3 H1 y
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CCRID PRODUCT PRODUCTLEVEL2 TITLE* G' w4 O2 ~9 U
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2 i( {% b$ J; J% O7 N735439 PCB_LIBRARIAN CORE PDV Moving line-dot pinshapes by arrow keys breaks the pinshape8 \0 ]( T+ r, V' ~7 @$ B6 k" i
894815 CONCEPT_HDL COMP_BROWSER Why does genlibmetadata command give 'Aborted $PROG' Message?
: D$ E4 |1 {) s: a. V! |2 N903073 ADW COMPONENT_BROWSE datasheetl_url directive should support a display string for URL1 M5 g, }8 f" ~6 G9 D
909919 CONCEPT_HDL OTHER Why is the PublishPDF UNIX command line looking for "true" script?0 u* ]+ e: ~& P( Z* w& r2 f; H) Q
911561 CAPTURE CORRUPT_DESIGN Capture crashes on trying to save the design.
. h. F. {: `5 ~; v919579 CAPTURE PRINT/PLOT/OUTPU Print mode be selected based on schematic mode
6 v: P4 B' ]& A921247 CONCEPT_HDL COMP_BROWSER genlibmetadata.bat file does not have err defined Z( B3 E/ `% Q/ d/ c
925182 CAPTURE PROJECT_MANAGER ENH: Feature to run update cache on all the parts in design cache at once.- ~" L. X* O: J# l/ t3 l
926858 CONCEPT_HDL CORE Usability- Modify Component dialog forces user to do 'Reset Filters' to see other ppt rows
% }+ P7 c( b% p; S4 n" `927657 CAPTURE NETGROUPS Enhancement: Placement of netgroup definitions under design cache list5 m1 l$ ]* @- O
934684 ALLEGRO_EDITOR MANUFACT The relation between the linear dimension and the symbol breaks.- @8 z/ V5 M8 b+ L( Q$ m% D
935836 SCM SCHGEN ASA crashes when generating Flat Document Schematic7 P5 J9 V4 t( \; Q1 P. @
937165 SCM SCHGEN Can't generate Schematic
! M* t8 P- T; ]8 v4 W# m937292 CAPTURE GENERAL Memory usage keeps on growing and finally gets exhausted while search7 s6 H) H4 K4 M# w* [$ f9 y+ \
937322 CONCEPT_HDL CORE Master.tag file alters the sequence of the files and Genview fails$ o4 H* s1 w3 q+ |
939135 CONCEPT_HDL CORE Unable to uprev a 16.3 Design to 16.5 with DEHDL-L License
9 X. q# t6 t8 u3 R7 t2 }2 e3 q940373 CAPTURE TCL_INTERFACE Enhancement: TCL command to add nets to Netgroup
( C: S4 m- p; d+ O940547 TDA CORE ERROR(SPDWSD-69): highspeed cannot be checked in
3 X; [0 Z) `8 {; w1 j940607 SIG_EXPLORER OTHER Inconsistancy in License usage for opening sigxp -orcad2 x4 O0 o/ E: g( a/ P
940790 F2B PACKAGERXL User doesn't want to display pin numbers after Export Physical 16.5. Q6 Q# i$ J4 B: {5 h
940944 SIG_EXPLORER OTHER Inconsistant license usage while opening Orcad PCB SI using allegro -sq -orcad and allegro -sq" @0 t. i [# t
941354 CAPTURE NETGROUPS Enhancement: Option to rename the unnamed NetGroups
# n. d# t7 u {941455 ALLEGRO_EDITOR MANUFACT The Dimensioned mechanical symbol when placed in the board does not show all the dimensions.
8 O# U* e, d. K2 l4 |6 O1 H941863 ALLEGRO_EDITOR EDIT_ETCH Different behavior of design in v16_3 & v16_5 when add connect is executed on a segment thru script
# T" M8 `9 U' r! o8 L6 F3 d6 W941881 CONCEPT_HDL COMP_BROWSER How can I suppress the dialog from universalbrowser -genlibindex?9 c; }4 n$ c: e2 x* W9 O
942474 CAPTURE NETGROUPS NetGroup member type of last added member must be remembered by Capture
" `/ g, q- k! ~3 `& ]942522 CAPTURE GEN_BOM Export in excel check mark doesn't invoked BOM in Excel1 I0 R( t6 I7 Z- y6 Q5 e5 R c( q
942557 PCB_LIBRARIAN EXPORT_OTHER PDV Export to Capture crash
0 ^; p0 e2 R. s942569 ALLEGRO_EDITOR MANUFACT Dimension move and change text deletes leaderless balloon0 Y. @% C/ U- V
942573 ALLEGRO_EDITOR MANUFACT Balloon type parameter has no effect on leaderless balloon.
5 ~& \+ i$ E) o9 V, }. U* _942613 CONCEPT_HDL CORE Genview supports only SCHEMATIC/SYMBOL/VERILOG/VHDL views as input type. .xcon not recongnised9 z1 P' a; Q' @7 F
943032 SCM OTHER ASA is not passing the correct reuse_module name to Allegro PCB layout.
9 ~: a* H! }2 `943401 CAPTURE NETGROUPS Alphabetical ordering of NetGroups in Place NetGroup8 u. p2 x# r4 V5 U4 d% G& @
944006 ALLEGRO_EDITOR EDIT_ETCH Vias added to shapes behave differently% g' E& M# ?6 D2 q2 k( `
944367 CONCEPT_HDL OTHER Too late to do Model Assingment in conceptHDL 16.55 G; y9 W" @1 m
944788 ALLEGRO_EDITOR GRAPHICS Oblong Pad shows unexpected lines
" K7 A) r$ ?* M K. n& x945221 CONSTRAINT_MGR RETAIN_CNS CM Conflict Resolution fails on more complex designs using ECSets and constraints
% Z5 E0 r2 V& g" O7 i( _% E5 \946270 ALLEGRO_EDITOR PLACEMENT The Rotation Type was changed to "Absoute" if the "iangle 90" use at placementedit mode of spb16.5
/ ?* I$ K: I' l% N o+ `5 [946350 F2B DESIGNVARI Variant Editor rename function removes all components
2 n( |- _5 F+ u* _9 U4 |946380 F2B DESIGNVARI Some VARIANTX properties are hard some soft - why?' y1 e* \7 n ^, ]0 E
946419 SIG_INTEGRITY SIMULATION Cannot select component on BoardModel for controller in bus setup form# c" \, ^5 F7 q% X
946458 SCM SCHGEN Schematic generator adding an unnecessary page
0 s, q, L$ V. k0 t$ \& Z947667 ALLEGRO_EDITOR PADS_IN Need support for PADS-POWERPCB-V9.3-BASIC
# H2 a K. Y, T* H' E8 K947789 ALLEGRO_EDITOR MENTOR mbs2brd crashes during translation on the attached design.
- N& Z2 M s5 s5 S948110 CONCEPT_HDL CONSTRAINT_MGR Concept HDL craches when opening SigXP from CM
4 B7 U* V9 N$ A950970 ALLEGRO_EDITOR MANUFACT Unable to generate artwork, dbdoctor fails to fix errors.# K6 n6 O0 D' E4 ~1 p
951901 ALLEGRO_EDITOR EDIT_ETCH In 16.5 add connect to same net is shoved
, H: i4 Q2 i9 N+ o951919 ALLEGRO_EDITOR OTHER Exported package symbol soldermask and pastemask padstack locations not the same as original
5 O: l+ d3 J8 a& o: J& N$ I6 R& ~951926 CONSTRAINT_MGR OTHER What is MaestroNotifyNotSetReport.txt file?4 \2 F2 R! d' ~; V7 P( U6 u
951939 F2B PACKAGERXL Uprev to 16.5 is changing refdes for some pages5 w" [/ N. m- }3 } F) T
951983 CONCEPT_HDL INFRA Problems converting an Allegro design from 16.3 to 16.5
" B1 n: ~3 K" c4 M952057 SCM PACKAGER Export Physical does not works correctly from SCM) Z4 q! b1 j: \
952217 ALLEGRO_EDITOR GRAPHICS crash when opening 3d viewer in PCB Editor
: A& X9 L! K6 Z8 e, g952634 CONCEPT_HDL CHECKPLUS Checkplus logical rule fails on a design which packages fine in 16.51 U) W$ n- Q5 ]- a, D8 Z# A
953018 APD REPORTS Shape affects Package Report result.- f H0 n* u! i/ s1 ~4 c7 V, x1 c# c
953337 ALLEGRO_EDITOR OTHER Allow netname and padstack names to be visible for testpoint vias when viewed in Allegro PDF Publisher.. `/ |! d9 n$ o
953827 ALLEGRO_EDITOR EDIT_ETCH Snake Breakout function crashed Allegro* B8 `8 c; ^" S
953918 GRE CORE GRE cannot route second and third row of pad in die symbol.0 V$ h& ]$ o" U4 {# J
954055 CONCEPT_HDL CREFER Crefer fails with UNC install path7 ~" y2 a+ R3 W8 N8 g; \ l0 s
954920 SIG_INTEGRITY CIRCUIT_BUILDER Each neighbor crosstalk simulation crashes or returns blank report8 a R& [/ c3 V
{, }3 M! B4 n' z/ V3 S6 ]6 s% tDATE: 11-7-2011 HOTFIX VERSION: 010: F1 A5 C9 D. V0 ?/ H* U, X9 s. |
===================================================================================================================================
5 [6 h1 X" q2 U- `CCRID PRODUCT PRODUCTLEVEL2 TITLE
: R- j4 a. K' m! b- }$ r, T===================================================================================================================================
) z8 g' o' I1 o: ~- q658866 ALLEGRO_EDITOR EDIT_ETCH enhancement option - so that Sliding a via inside a pad does not create a cline
6 b) ?: t2 J- m% a* ?928624 ALLEGRO_EDITOR GRAPHICS Layer visibility control for 3D Viewer
& m" W9 f$ g2 M- ?4 r934991 SPECCTRA LICENSING Specctra_adv option is not working correctly for PA3100 plus PS3500 license in v16.5 tiering profile$ ?6 ^2 p( ]$ o& [0 R% F
938073 ALLEGRO_EDITOR PLOTTING Plot Page size A0 and A1 with problem1 A; L1 s0 r5 M; y; f9 }
938128 ALLEGRO_EDITOR DRC_CONSTR DRC changes when do update DRC.
. R9 e- l1 R+ ~$ P h6 a938648 ALLEGRO_EDITOR GRAPHICS Enh - Requesting a way such that Package keepout appears transparent in 3D Viewer
% ?0 Z$ R4 g( y* d* M* Z; O940518 SIP_LAYOUT SYMB_EDIT_APPMOD Swap pins command doesn't complete" t; a. b5 n% {
941426 CONCEPT_HDL COPY_PROJECT Copy Project fails - Updating opf view This can't happen!! @% U0 o" W' w2 l1 g
941499 ALLEGRO_EDITOR DRAFTING BUG imit Tolerance isnot working for Dimensioning {8 f2 S+ @0 U" m g
941814 CONCEPT_HDL CREFER CreferHDL crashes during ScheGen+ _; C9 c9 [* c/ U/ n$ |
942914 SIG_INTEGRITY OTHER ZAxis delay calculation7 s5 O9 {; q+ S( Z4 L9 _
943053 ALLEGRO_EDITOR SHAPE Modifying the Board Outline shape will cause the tool to crash2 g" H& A: D/ f7 ~* Q1 l& d
945321 SIP_LAYOUT EXPORT_DATA generation of a xml file from cdnsip for shrunken die
& Y: W1 w) n# P9 I/ i945350 ALLEGRO_EDITOR SHAPE iPick does not work on shape boundary edit.8 O, }5 p% g& ^3 m
945449 APD SKILL When they create a new menu entry with skill APD crashes with next menu selection.4 ^3 w! n* Q2 {6 v6 a- o: P, ^# L
946390 ALLEGRO_EDITOR DRAFTING refresh_symbol crash when trying to refresh mech sym that has dimensions
2 t8 H7 [% k0 u/ y# V. J: ]946401 APD EXPORT_DATA stream out gdsII results in shorting of PWR/GND nets due to elongated etch+ M* _9 E* |* {) M' t8 g
946819 SIP_LAYOUT DEGASSING Shape degass command
. |4 j5 ?: }5 q7 r3 Y! S! v946869 ALLEGRO_EDITOR OTHER Allegro PDF arc representation needs cleaned up6 c/ l; k3 S/ A. f/ ~8 e& U
947230 ALLEGRO_EDITOR SKILL Skill execution crash Allegro 16.5 but work correctly with Allegro 16.3: q/ D, o, f# a
947603 ALLEGRO_EDITOR OTHER Component Properties (Default or User Defined) not transferred to PDF file; G% D( S" S" B& T3 b) o
950995 SIG_INTEGRITY OTHER Netrev fatal error when importing logic% B0 M( Q, G" W$ q
951123 ALLEGRO_EDITOR INTERFACES IPC fails to output drill hole info in columns 33-37
' {4 n5 Q9 _1 J; q" b* |9 o951557 CONCEPT_HDL CORE Cannot create the entity folder for old plumbing symbol4 S$ _; j; I5 C5 X
1 O( Q$ e( y4 e' A4 A6 \DATE: 10-26-2011 HOTFIX VERSION: 009
/ I. g+ D9 c* c; i \, W===================================================================================================================================
: W1 c+ V. i' VCCRID PRODUCT PRODUCTLEVEL2 TITLE( G" b) w2 c( i* ~
===================================================================================================================================8 n5 }) E# n# R; j7 Y
945788 CONCEPT_HDL CORE Some component properties on the parts are incorrectly changed after Import Sheet9 r! A2 p) f* G7 ?$ j: B4 n
945789 ADW LRM Some component instances are not updated by LRM even though cache ptf is updated from reference1 z2 z* E" Y" {9 O3 |" {# l
/ M$ Z/ f7 W5 ]! m# \" V: g
DATE: 10-21-2011 HOTFIX VERSION: 008% K4 S- [! y3 D
===================================================================================================================================
. {+ |$ r1 I5 u7 K3 C l0 k% x1 CCCRID PRODUCT PRODUCTLEVEL2 TITLE K# b' s/ X7 V
===================================================================================================================================1 f2 N* M7 y7 x" v! l1 K) a1 n
906827 ALLEGRO_EDITOR DATABASE Logic > Parts logic does not work correctly. o q6 S& t. o0 A# ]+ c
923346 CONCEPT_HDL CORE Not able to move the reference designators inside hierarchal blocks after uprev to 16.5, x3 ~+ j& Z& T) v
926347 ADW COMPONENT_BROWSE Usability- Libflow Part check in comment should end up in Comments attribute for UCB/Designer to see it8 D/ y/ V0 ~/ B
929348 F2B BOM Warning 007: Invalid output file path name3 T/ w/ B3 u; V$ q* y1 r! h
929777 CONCEPT_HDL OTHER Component Revision Manager gives internal error
. W2 \: w+ @3 p* D930783 CONCEPT_HDL CORE Painting with groups with default colors
2 i6 w. _) r: o7 t& W936748 ALLEGRO_EDITOR INTERACTIV "Unplace Component" menu inconsistent between General Edit and Placement Edit Mode.
' j/ E+ U+ K9 z; N2 c% Y, R938143 ALLEGRO_EDITOR CREATE_SYM Why is this Extra Property 'ECSET_MAPPING_ERROR7 u9 h; n. }5 v4 A9 I4 q4 e1 {
938281 SIP_RF OTHER export_chips creating bad data when symbol is split and contains V- V+ pins
4 q3 _& Y& b4 T8 ?. \: |938812 ALLEGRO_EDITOR SYMBOL Cannot create a BSM with this DRA, errors out but does not state a reason.$ K2 y F. Z4 i- e2 a
939075 CAPTURE TCL_INTERFACE Texts are getting garbled in command window3 O: R4 @+ n+ J
939193 F2B PACKAGERXL ERROR(SPCODD-439): Connectivity server is unable to load the design.
( W5 a2 w2 h4 y3 o2 M4 f/ w939199 CONCEPT_HDL DOC "Retain electrical constraint on net" mismatch between schematic (YES) and design (NO) x \1 |! ?9 n* _6 w7 f v
939346 ALLEGRO_EDITOR SHAPE Shape disappears when updating with variable shape_rki_autoclip set.% Q( X) C3 L; B C
939901 CONCEPT_HDL INFRA NET_SPACING_TYPE shows �?� on lower hierarchy level nets after Upreving to 16.5 version.- M9 h' w7 Z% R/ m- t1 w
939918 PSPICE PROBE Print > Preview for output file causes Pspice crash.0 W; ^* @ m. ]5 U1 C
940217 CONCEPT_HDL COMP_BROWSER UCB reports 'No Symbol found for the part'" H+ S$ M. ]- L: B+ Q
940835 CONCEPT_HDL INFRA Desing package different after uprev to 16.5 where comp instance propeties are lost lost
9 B8 V, S3 N( W4 G G941125 ALLEGRO_EDITOR DATABASE Performance advisor doesn't skip non plated slot padstacks
+ S% r. k- r3 R' h& c5 l941876 SIG_INTEGRITY OTHER Illegal model name cause pxl fail in 16.3
9 B$ q! E' f, k4 d! @. W942210 SCM OTHER Is the Project File argument is being correctly passed?" E/ J5 t) Q: T% x
942274 CAPTURE PROJECT_MANAGER Crash on renaming a Design Cache part in Project Manage after doing replace cache0 B; a; C5 f! s3 ], H: N7 x) R
942839 ALLEGRO_EDITOR GRAPHICS Graphics Issue- Pads are not visible
/ K5 F7 H, q }943055 ALLEGRO_EDITOR SKILL axlDBCreatePropDictEntry causes application to crash
0 C* J( Z9 _1 x9 d% {- n' k: w4 N8 s2 Z* Z0 ^* F
DATE: 10-21-2011 HOTFIX VERSION: 007/ y8 F8 }" {" k6 k/ ?, ~& H4 R
===================================================================================================================================2 p: I. R. j4 ]
CCRID PRODUCT PRODUCTLEVEL2 TITLE3 P; z4 U0 Y6 a$ A2 W+ `
===================================================================================================================================
- x* v/ U/ i4 h+ }- }841096 APD WIREBOND Function required which to check wire not in die pad center.
: J1 ]; p4 p4 r" \, Z903263 CAPTURE SCHEMATIC_EDITOR ENH: Selecting parent netgroup must select the underlying netgroup bits.
* u# W3 u: W6 V- |906692 ADW LRM LRM window is always in front when opening a project
3 R) W' d% |1 R( M. R912942 APD WIREBOND constraint driven wire bonding1 x2 [# a2 r6 T: K* o! b
912951 CONCEPT_HDL CONSTRAINT_MGR Need to manage temporary files on Linux systems- }. B; C% Q$ J: e9 ~* U
915178 SIP_LAYOUT DIE_STACK_EDITOR Die Pad names changing when updating Die in a design& n7 \4 O4 Y4 |: Z9 g2 N% X& J5 `
917887 PCB_LIBRARIAN VERIFICATION Part should not be released if the alt_symbols has errors
3 G+ L) X9 d' I923315 SIG_INTEGRITY GEOMETRY_EXTRACT crosstalk simulation fails with TMP popup failure$ d! k5 c; `2 B0 z: w$ e0 P( B8 G
927382 CONCEPT_HDL CHECKPLUS 'Verify Symbol' forces the use of 'Concept_HDL_Studio' license# @* _8 m2 w/ B2 R" W; z
927664 CONCEPT_HDL CONSTRAINT_MGR Internal Error disposeipsp* s; W& M. {: j/ |
930152 CAPTURE NETGROUPS Scalar net names when being connected to net group overlap when connections are made one by one
1 n: S. M9 I' ?2 B0 X+ u0 b930180 CIS LINK_DATABASE_PA Visible property position on schematic get reset on "link database part" operation
- g9 W0 ^ Z0 f: }9 Q930188 CAPTURE DATABASE Capture 16.5 crashes in being re-invoked.
7 ?# r( b! E& i4 p930541 CAPTURE NETGROUPS NETGROUP element renaming doesn' renames the associated net ?) x7 h0 l+ Y9 P* f
930866 PDN_ANALYSIS SETUP OrCAD PCB SI Session crashes when we open PDN Analysis with "OrCAD PCB SI" license.
. J% U# g& M8 F- M/ }7 F/ T930926 ALLEGRO_EDITOR GRAPHICS Via and Holes not visible eventhough set to Visible in Color form
+ }5 b: d7 [5 d) ?931274 ALLEGRO_EDITOR DRC_CONSTR Negative Plane Islands waived DRCs reappear after performing update DRC.
4 u- K" X% r" o932091 CONCEPT_HDL CORE Prop attached to SIG_NAME property
$ L; C3 M2 z+ C9 @7 E932255 ALLEGRO_EDITOR GRAPHICS Change in Zoom level makes arc segment to disappear
* d* i0 B3 k' U" a# |& J- f* t932292 ADW LRM LRM crashes during Update operation on a customer design. Y: L$ a ^/ m k, g
932639 SIG_INTEGRITY OTHER Add Connect command hangs for about 14 seconds and then returns.
- q) x5 l! W) R932704 APD DEGASSING Shape > Degass never finishes on large GND plane" ?5 u U8 S$ b
932871 APD GRAPHICS could not see cursor as infinite
x1 C) t5 B9 b" R0 W932882 CAPTURE SCHEMATIC_EDITOR Capture crash with FIND command - ISR05
/ M* c7 R) y S1 |7 g2 Q+ y6 @932969 CONCEPT_HDL CORE ConceptHDL crashes when you save the design in 165 > hotfix #05
! }% _. {! M! J: f6 N933024 CAPTURE NETGROUPS Naming restrictions for NetGroup members! q& _" q$ w4 z, _
933145 F2B PACKAGERXL Add Subdesign list is truncated in Force SubDesign Design Name pulldown* F* a. _& \/ x0 n7 m4 ]
933214 APD ARTWORK Film area report is larger when fillets are removed; F0 V3 _" T9 k; L4 y
933356 CONCEPT_HDL CORE Net prop display size become 0 if it was attached to SIG_NAME prop.
; X. [; W7 |) d, v$ L933532 ALLEGRO_EDITOR COLOR Bad color assign and initialisation during creation of new subclass
* i- V) Q; ]. E5 f933549 ALLEGRO_EDITOR OTHER Chart text missing in export PDF file.
2 a% L9 y8 b" D, ^4 d934008 ALLEGRO_EDITOR REFRESH refresh symbol updates symbol text to some unexpected values
" p2 F8 h. s6 S D0 R934031 ALLEGRO_EDITOR DRC_CONSTR Bug : Update DRC removes Waived status for some DRCs
' ]+ v+ W! { u934087 CONCEPT_HDL CORE Opening DEHDL and Model Assignment before design loads causes crash) o- _6 |: P ~7 A# W- p
934396 CAPTURE SCHEMATIC_EDITOR Find operation is not searching power symbols with + or - signs.! D- j9 e0 x! J. L# n$ K6 Y* J
934533 F2B DESIGNVARI The Variant Editor errors are not written to the variants.lst file
/ p3 b* Q' ~& H6 b, e; S934811 SIP_LAYOUT UI_FORMS CDNSIP should not hang if contraction value in z-copy command is out-of-bound4 u6 q4 |. k3 t% g# {6 s
934909 SCM UI Require support for running script on loading a design in SCM
' k4 r6 `( d0 i, z* ]) v0 g8 V! m& o935632 CAPTURE SCHEMATIC_EDITOR SHIFT+Mouse wheel scroll(horizontal) of page is not working in Auto Wire Mode.! M" L7 l. K' Z) j6 C/ K6 `+ Z8 x
935794 ALLEGRO_EDITOR SHAPE BUG:Shape not filled in 16.5 but it does in 16.3) y9 J4 r. D- F: G$ ^
935988 ALLEGRO_EDITOR INTERFACES When attempting to downrev this 16.5 design to 16.3 the tool will crash* |4 z% Y& R. x+ l
936056 ALLEGRO_EDITOR DRC_CONSTR place_manual crash while moving mirrrored symbol
) k4 e* p' t( c8 v/ ^* g( N7 Y7 D* {( q936098 ALLEGRO_EDITOR SKILL axlDBCreateCloseShape does not work correctly.
9 ]& _8 m- t" Q' Y936212 ALLEGRO_EDITOR INTERFACES DXF not created if Blocks created for Symbol and padstack
. X M+ o! p3 \( n/ ?/ l936797 CONCEPT_HDL COPY_PROJECT Copy Project crash
* U4 L$ c3 z8 e: [3 N0 y* _! |4 U. q936808 ALLEGRO_EDITOR DATABASE Allegro crash replace mechanical symbol
: t# N; G) G$ L1 w- q936853 CONCEPT_HDL CONSTRAINT_MGR DEHDL crashes when trying to extract net from CM$ M- v- y' r/ w( v* w5 ^0 s
937087 CIS DESIGN_VARIANT Upreved design becomes very slow in Variant view mode. DELEET THE DESIGN AFTER RESOLVING THE ISSUE3 X# i( Q; q* Q8 q3 d' Z* ~: Z
937173 CAPTURE OTHER Wrong license information "UNLICENSED" in Capture >> Help >> About* d$ s W/ v4 X* z
937290 APD PLATING_BAR Plating Bar checks does not recognize connection made through etchback through shape.
! t: U) I, t+ b937411 ALLEGRO_EDITOR DATABASE downrev_library reading from one directory and writing to another hangs the command.
% s+ F% K Q1 ?& }5 ^938235 SIP_LAYOUT STREAM_IF Die Orientation is not correct after importing a stream file.
( E5 q! d( I3 P R' s4 b1 J938273 ALLEGRO_EDITOR OTHER PDF export is is not opening viewer with ads_sdlog variable set
* G' f4 x- D; G" c- l9 B2 c9 k$ Y% L6 s* N- J& E# `, f6 `# o$ v( \5 }
DATE: 09-16-2011 HOTFIX VERSION: 006- ` N: z; D0 x+ {4 p$ C
===================================================================================================================================
7 V! k) k6 P# [$ R- zCCRID PRODUCT PRODUCTLEVEL2 TITLE
4 E& H' H) r N( E, Q===================================================================================================================================
- ~5 c$ U, j. t* w$ Z2 j820131 CONCEPT_HDL OTHER Moving symbols to other page will make Allegro components unplaced because logical_path changed.7 W$ E3 U8 v4 C+ V) U! _+ L; V
863860 CONSTRAINT_MGR SCHEM_FTB CM should display or Local Interface and Global nets to help defining low level constraints
% L) m+ L o" U# t- V/ U t$ y919822 TDA CORE Cannot configure LDAP to only list the login name
, ?8 g2 I' h: y! u( k& d922907 ADW TDA 搇ast_callout_file� directive in the BOM section is empty causes tda for show Access Denied error% H3 ]6 g& ]8 o5 A
924322 ADW COMPONENT_BROWSE Random - No instance properties are added on Add To Design (RMB or double click) from Search Results
: s9 }5 z% {6 _! X924448 F2B DESIGNVARI Design does not complete variant annotation
- A1 j; @1 W, F4 l N8 s925584 CONSTRAINT_MGR SCHEM_FTB 16.3 upreved Design passes the SLOT/Function Properties to PCB- `5 l4 O$ a3 O* Z- e) x
927102 ALLEGRO_EDITOR OTHER Question of Conductor Detailed Length Report! n' R! [# j! R) [" T: |4 i
927104 F2B DESIGNVARI Tools > Annotate variants crashes when there are ASCII characters in the property values" `+ \# N D" p8 b6 c( k
927142 F2B DESIGNVARI Incorrect pop up asking while executing variant editor from the command line
* _ u& M* b; \927166 CAPTURE NETLIST_ALLEGRO ENH: Feature like NET_SHORT in Capture Allegro flow which allows user to short 2 or more power nets) p" T$ n% V1 ?5 {
927410 ALLEGRO_EDITOR DATABASE ERROR(SPMHUT-144): Illegal arc specification error when Run DBDoctor' y- H0 k- k1 u& ?
927475 CONCEPT_HDL CORE About forcereset command of nconcepthdl7 Y, \1 O* j& l* W; ]$ H( O
927498 CONCEPT_HDL CORE Pin_Name starting with minus causes incorrect behavior for $PN display
0 A ~! u' F) h# v5 o927608 ALLEGRO_EDITOR PADS_IN Import PADs fails with error message: Failed to close the Allegro database
4 d. M2 r! ?& t* q927637 SCM CONSTRAINT_MGR ASA crashes on change root and also performance is too slow.
; c/ Z2 j( e( W: ^7 s% i4 M928429 SIG_INTEGRITY OTHER Request - Package Wizard to work in PCB SI.
1 x' D* F/ d+ g4 q, I928483 ALLEGRO_EDITOR DRC_CONSTR Running Update DRC removes Via List DRC Error when via is actually not in the list. l# C/ y/ U3 u, C0 Z
928738 PSPICE PROBE Y-axis grid settings for multiple plots# I, s5 S! h& h. g! Y) r
928748 PSPICE PROBE Cursor width settings not saved
- v9 k8 o: p) z. a; v* b& r928779 CONCEPT_HDL CORE Error (1053) occurs on a copied part in SPB165 release: p: V, {$ d" P# B: @& U. Z% e
928838 CONCEPT_HDL CONSTRAINT_MGR ECSets not migrated in 16.55 w" U! p' O; [4 Q4 U; h
928885 SIG_EXPLORER EXTRACTTOP PCB SI crashes when extracting a net from Probe' v" d% X6 N/ O6 A# S) Q4 c
929284 CONCEPT_HDL ARCHIVER archive does not create a zip file
7 }, |* L& s. i7 i M+ k* Z929542 SIP_LAYOUT DIE_ABSTRACT_IF net issue of multiple ports of co-design die in SiP
/ I% J4 t- v. Y4 v) P3 }929656 ALLEGRO_EDITOR PADS_IN PADS translation fails with Microsoft Visual C++ Runtime Library error2 Y/ G! B" M4 A% @0 Z% _/ ~
930063 ALLEGRO_EDITOR TESTPREP Test prep crash Allego when it can not create pin escape7 k. Q2 S8 [/ [. d
930217 CAPTURE NETGROUPS Net aliases doen't gets assigend to bus bits if bus name is checked in NETGROUP.
4 m6 S# D0 G+ G" H# F930355 SIP_LAYOUT WIREBOND about "wirebond add nonstandard" command* V1 f6 a4 x6 c- a$ u
930607 APD OTHER Layer mapping information is reomved from Layer conversion file upon exporting DXF from board file.
: x0 Y, ]. m- O8 @/ {- h# Q930646 ALLEGRO_EDITOR DRAFTING Bug - Adding Linear Dimenstion for ISO standard add the Angle information as well4 y0 Q) @9 M' s; b' h1 z
930894 CAPTURE TCL_INTERFACE PDF export doesn't creates property file if some symbols are used in page name/folder name/ r! T( ~8 |) B. ?# N! U4 v
930944 ALLEGRO_EDITOR OTHER Setting variable 'appmode' equal to 'none' is not changing the Application Mode when reinvoked
& R+ h% J6 `2 N; W! R930978 ALLEGRO_EDITOR SCHEM_FTB 3rd party netin error - Pin is connected to net <netname> not reconnected no longer happens
9 A1 _5 Z% Z8 ?931248 ALLEGRO_EDITOR DRC_CONSTR Match Group was removed if member nets became xnets.4 r' N& Y2 {( R8 D% ?' w6 A q
931278 CONCEPT_HDL INFRA $PN gets copied when upreving design from 16.2 to 16.5 version `9 k! c" q2 ~3 ?3 m8 ^1 U
931349 CONCEPT_HDL COMP_BROWSER DEHDL craches and corrupts connectivity file when using Modify command extensivly.
: V" [6 E7 v" v( ?8 a* M- @. r9 B' D& ~- V$ L% U4 _) `* M+ ?% c- E* M
DATE: 08-31-2011 HOTFIX VERSION: 005
2 ]; v' W1 P8 }0 g. h, d===================================================================================================================================
, f4 ~! I3 P: _4 X, MCCRID PRODUCT PRODUCTLEVEL2 TITLE8 s! M' E& ]% ]! A; U. R
===================================================================================================================================6 r2 f7 ~ g( s2 Y! `
825848 ALLEGRO_EDITOR SHAPE Shape not filled when edges from 2 RKO shapes touch around mouting hole# r5 e, U4 k/ [5 p
837723 CAPTURE PROPERTY_EDITOR Occurrences of external design not related to current root should not show
# X* a _& D1 b K4 J- h- k891079 CONCEPT_HDL CORE DEHDL crashes with large number of commands in Winodws mode# Y/ I8 M# [4 {; M, F* y8 _
910908 SIG_EXPLORER OTHER Cannot open top if Tx AMI dll name contain more than 2 dot.- G* R/ D i, X7 ?# _0 T) N
914036 CAPTURE LIBRARY ENH: Option to delete a corrupted part from a library and leaving other parts intact in the library.+ K2 G5 g" M0 l, l/ `* |
914679 ALLEGRO_EDITOR INTERACTIV Custom toolbars are not retained when switching between brd to dra and back to brd file using the File > Recent Designs
% p6 ?1 |1 E3 J- y1 H914870 MODEL_INTEGRIT OTHER mergedml fails to merger 2 DML files from the model integrity
8 Z& F9 i% K/ |$ l915645 ALLEGRO_EDITOR MANUFACT Allow the user to place the cross-section chart at a desired location$ \/ d& ?4 R1 e
915653 ALLEGRO_EDITOR INTERACTIV unable to delete non-etch shape1 a' H! u* m3 x) j, Z
915711 ALLEGRO_EDITOR MANUFACT dimensioning tolerancing by limit not working$ f! h- ?2 w9 y& @2 |
916321 CAPTURE GEN_BOM letter limitation in include file
8 r$ e: F9 H' E, |# k: ? u6 w916907 CAPTURE SCHEMATICS 揂uto Connect to Bus� should place the wire through non-connectivity objects" S9 W2 L" }. S: c" t4 _( c" M. p! H
920327 CONSTRAINT_MGR ANALYSIS The TotalEtchLength predicate in Constraint Manager does not work for a netclass with a bus. |% _4 L& ?3 g0 u8 H" {
920753 ALLEGRO_EDITOR GRAPHICS If I confirm to padshape with zoom-in after install the s002 It was changed to wrong shape.
$ m2 ^5 {9 `0 R9 B) \* N3 }- v/ |921097 ALLEGRO_EDITOR GRAPHICS Padstack seen partail filled when Zoomed in even "static_shapes_fill_solid" is set/ I$ C, r c( J: u$ y4 |
921226 ALLEGRO_EDITOR DRAFTING Unable to select Package Geometry class when dimensioning in the symbol editor.5 s$ V) i1 A5 ?/ e9 F9 t" k
921623 ALLEGRO_EDITOR GRAPHICS Bug : Symbol not visible when zoomed in 16.5 S002
+ @1 l0 h$ A, L0 a }: f7 Z0 L921891 ALLEGRO_EDITOR DRAFTING dimensions are lost after downrev(ing) a SPB 16.5 design with associative dimensions3 g3 r& z9 j5 \. X* L* X* F8 \
921937 ALLEGRO_EDITOR COLOR Padstacks with shape symbol are not showing correctly" u; g' y/ O% O! A0 x q' q
922066 CONSTRAINT_MGR ANALYSIS Custom measurement Actual not being cleared when layout changes.
^2 N9 k6 t7 _/ I8 C8 r! C922117 PSPICE PROBE Label colors are not correct in Probe
' V1 A- z" V+ y# e) O! S' w( B) V922519 ALLEGRO_EDITOR SKILL add_bviaarray command fails for some clines but not all
% Y# I8 N* a/ U: H8 u! D923224 ALLEGRO_EDITOR GRAPHICS Thermal flash Display problem in Allegro v16.5 Hotfix S002
+ ~6 |. m" g* {9 [( G923286 CAPTURE DRC DRC markers not reported for undefined RefDes4 x' e2 _0 p; z$ q2 n
923362 ALLEGRO_EDITOR PLOTTING Print to Postscript file not correct in 16.5! m# x+ ]9 ~+ J* c
923416 ALLEGRO_EDITOR PAD_EDITOR Pad Designer crash on clicking on the Arrow before Soldermask_top
! t9 n2 N; J$ e! ?923507 CONCEPT_HDL CONCEPT-PCBDW The function of Import Design in the SPB16.5 Design Entry HDL (for data of ADW15.5_S23 + SPB16.3)# K5 ?; r3 Q3 Z( w
923910 CIS PART_MANAGER Copy & Paste operation from Part Manager copies properties only to first section of the part., I" j9 b2 N3 ^. i. K [
923913 CAPTURE PROJECT_MANAGER Capture runs slow on attached design- b7 \2 p! h4 s8 z6 [/ |6 H+ _
923937 CONCEPT_HDL CORE Back annotation time significantly increased with the metadata generation on0 y# F0 V3 n4 w' l7 s& e
923949 ALLEGRO_EDITOR INTERFACES Incremental DXF_IN gives 'Invalid subclass' error
1 K" h- ]+ N' E9 q7 r924458 SCM OTHER Project > Export > Schematics crashes
' `: l" j5 s. W( M5 A924621 ALLEGRO_EDITOR SHAPE Dynamic shapes are disappearing upon updating them to smooth.
' P& \; w0 N3 E4 J925193 SIG_INTEGRITY FIELD_SOLVERS Diffential Impedance (DiffZ0) values computed in the layer stack-up is incorrect5 E2 M, U8 G* Y2 O
925195 ALLEGRO_EDITOR DRC_CONSTR Incorrect pin to shape DRC error
, j" s1 G. m! ?! [# B( [0 s925338 CONCEPT_HDL CORE This application has requested the Runtime to terminate it in an unusual way" Z+ f- M: e- I! p
925435 CAPTURE TCL_INTERFACE Capture crashes if 揝ave design as UPPERCASE� option is disabled.
0 v; S' c! Y5 @5 j0 T925530 SIG_INTEGRITY OTHER Why the single line impedance value for Top and Bottom layers are different for this design?+ Q( y* M6 y, Y( B. l1 _( v
925864 ALLEGRO_EDITOR DRAFTING Ability to add dimensioning to different CLASS/SUBCLASS, G/ A: T, A) b
925976 ALLEGRO_EDITOR MENTOR mbs2brd fails to import data+ O5 v; }+ ~! S) y T
926409 SIP_LAYOUT DRAFTING Exporting a 16.5 design to 16.3 will cause the leader/dimesion lines to be removed.$ ^! V& t4 \% \% i( @9 S$ O
926443 CONCEPT_HDL CONSTRAINT_MGR In new 16.3 "035" ISR Concept2cm will crash with error.
/ r i; ]0 ]* U% K: h6 B) t926503 CAPTURE GENERAL Memory leak Capture/Pspice
1 _" p; [" A9 c0 j926553 CONCEPT_HDL CONSTRAINT_MGR CMGR ERROR There is no net in the Cset that has pins matching those in net 1 in the Xnet
! l F& y* p$ `7 O& y926691 ALLEGRO_EDITOR OTHER Crash while Importing Technology File in CM, with Overwrite Constraints.
: z8 R: k- O6 V7 q6 j3 w9 U. Z926887 CONSTRAINT_MGR CONCEPT_HDL Pin pairs lost after Export Physical$ N% x9 u; l- q# @& t
927159 CONCEPT_HDL CONSTRAINT_MGR Export Physical fails due to errors in ConCM.log when SIGNAL_MODEL injected property is ''1 j$ Z6 a0 v: X5 [
5 T L q8 X& L3 G, M4 b3 `
DATE: 08-19-2011 HOTFIX VERSION: 0048 S. O6 C1 z3 \/ B4 J" z- h
===================================================================================================================================3 T: ]7 F/ V9 U4 |( q. n6 |8 R
CCRID PRODUCT PRODUCTLEVEL2 TITLE8 ] B+ F& V8 |* o v$ n
===================================================================================================================================) @/ D! o! _; L( K
785417 CONCEPT_HDL COPY_PROJECT copyprojectui crashes with a Windows runtime error) j' V3 ]2 Y9 X* a
851044 CAPTURE GEN_BOM "Export BOM report to Excel" does not appear in the Standard Bill of Material Window.8 ~! a0 _: `+ E
868216 PSPICE MODELEDITOR Encryption of subckt names, internal nodes, comments
% \8 Z' r4 Q7 z+ B8 I. P6 W) v6 X: C870247 PSPICE SIMULATOR Encrypt a model and simulate it, info about inside nodes being dumped in the probe file" x0 D# I& x7 j! T
877091 CAPTURE SCHEMATICS Save JPEG, GIF, PNG and other image formats in the database in its compressed form( l$ H; g9 Y( ?' j
894059 CAPTURE OTHER Enhancement: Adding column in edit>browse>parts window4 |! M+ \ n- z5 v
895902 RF_PCB OTHER Alphanumerical allegro pin numbers are unusable in ADS 2009 Update 19 x; b2 c# \. t% l* O/ a$ m
895919 RF_PCB OTHER Round trip Allegro to ADS to Allegro requirement
8 ?$ P( A% M4 {. \903102 ALLEGRO_EDITOR OTHER Zcopy shape command for cline seems not to work correctly.
- Z, }$ r' S# L0 m905562 SIG_INTEGRITY SIGWAVE Noise margin seems not to be measured correctly with Eye Measure function.
, j0 B( I& O" }3 i% J9 X909469 SCM TABLE ASA crashes when opening project
% d# o5 H; j( t' I7 `909595 APD LOGIC Inconsistency between export die text out and show element after pin swap- L/ ^; Y0 {1 R4 m' n0 h( Z; M% s
911123 CONCEPT_HDL CORE 16.2 Design uprev to 16.5 fails with ERROR SPCOCD-152
" s; D: a8 W3 a911569 CAPTURE EE_INTERSHEET_RE Q: Why is capture assigning incorrect Irefs in attacehd design ?% K) {, h( g* k9 ?9 ]1 m
915657 ALLEGRO_EDITOR OTHER Allegro PDF Publisher Mirror capability
# D, U! ]( G! i }915755 CONCEPT_HDL CONSTRAINT_MGR Cannot view net in SigXP$ E ^1 _2 i% s- v8 E2 [
916062 CAPTURE GENERAL Auto Wire Crashes Capture! X7 S8 A5 q [7 t. s4 ~
916820 F2B OTHER RF create netlist with problem
* Z! m: u6 _/ l& {* Y' b" O917967 ALLEGRO_EDITOR REFRESH Update symbol resets refdes location for bottom side components only.; d+ M* q+ ?6 Q1 h
919343 ALLEGRO_EDITOR PLACEMENT Place Manual is crashing the board file/ F' ?& P8 c/ m w
919481 CONCEPT_HDL CHECKPLUS CheckPlus isGlobal function is not working; j5 j8 D9 g( O5 \3 t8 ` [
919510 CONCEPT_HDL PAGE_MGMT takes 10 min to insert page in DE HDL
+ c D8 ?4 b0 j. o2 N% k919976 APD DATABASE Update Padstack to design crashed APD.! \8 k" T5 h1 U% k& z X* [
920418 SIP_LAYOUT OTHER SiP enhancement to Auto Assign Pin Use to add ability to change the pin use definition& P% b& e* g( h ]
920420 SIP_LAYOUT LOGIC SiP enhancement to Logic Auto Assign Net to display a dialouge Auto Pin Use assignment should be run
; P0 D5 ^6 u6 r0 Y& r1 c920712 ALLEGRO_EDITOR ARTWORK Program has encountered a problem ... error when creating artwork8 K/ R3 n7 Z# _7 o6 F& n0 C0 m
920763 ALLEGRO_EDITOR ARTWORK Soldermask gerber missing thru-hole pins
0 n- _) y ?1 s, E% T$ Q0 C920976 ALLEGRO_EDITOR GRAPHICS Question regarding the difference in the behavior of 3D Viewer w.r.t. height_min o3 E: ^9 M6 h5 ?2 S- f( A+ H, T
920993 ALLEGRO_EDITOR DRC_CONSTR Minimum Metal Spacing Error is detected on Same Net9 h/ X& {# ~% s- ]& j4 }2 N
921727 ALLEGRO_EDITOR DRC_CONSTR Pad Boundary causing P/P drc to adjacent symbol.
3 ]5 r( G0 ?5 D; R922579 CONCEPT_HDL CORE Xcon file gets corrupted upon Save of Hierarchical design with Global nets tied to interface nets
, Y& U! g8 |6 N/ w8 A! l) ]' h922592 CONCEPT_HDL CORE DE-HDL does not report illegal connection when Global Net tied to interface net using an Port symbol and named
6 }$ x! i' z- F" A: x922758 ALLEGRO_EDITOR DATABASE Allegro crashes while placing second mechanical symbol with route keepin
( @, l& J) K2 Q3 |# a922839 ALLEGRO_EDITOR DFA The DFA drc display is unstable.% d) j3 z+ D: f2 A- |
923293 ALLEGRO_EDITOR INTERFACES File> Export> IDX is failing for this design while creating an empty error log.
! }0 B9 i5 r: F X3 X924772 ADW PCBCACHE Import Sheet is not bringing in Parts used in the source pages into target cache ptf7 u; b7 O6 u8 x P0 a
) ~& R6 P9 [ ~! Y. j: dDATE: 08-4-2011 HOTFIX VERSION: 003# X+ D) C# I- |6 U
===================================================================================================================================
2 R9 S, V% G; b) h' c \0 v G# ECCRID PRODUCT PRODUCTLEVEL2 TITLE/ c! x ~7 _2 s5 z, c. I
===================================================================================================================================
" @3 d8 P( L, e) L787414 CAPTURE PROPERTY_EDITOR Part value can抰 be moved on schematic if a part has been copied to a new design and not saved yet.
; _2 z1 ]! V) u9 m4 s; ]: a! x903898 PCB_LIBRARIAN GRAPHICAL_EDITOR PDV move symbol graphics and Undo causes corruption in graphics! t6 H4 a, q4 F* S8 b1 q
904287 ALLEGRO_EDITOR ARTWORK some cline with arc is missed, when creating artwork." q( D% a' J h4 c
904418 CHANNEL_ANALYS SIMULATION channel analysis sim does not give valid result0 y/ S" w! M/ b2 h8 |. g
905777 SIG_INTEGRITY SIMULATION User gets popup message that halts an analysis until it is acknowledged
) ~, G" C4 J* ]: U) P906139 SIG_INTEGRITY OTHER Bus sim result were cleared at the next run even if no preference changed.
+ t$ X9 C! h4 |908680 SIG_INTEGRITY OTHER Extra prop delay due to resistance8 U5 Y3 I7 Z J ?3 s) D
909583 ALLEGRO_EDITOR SKILL axlPolyOperation AND operation is not working correctly.' K+ a5 ^- l. i/ r4 q
910315 ADW LRM Import Design with ADW causes partmgr and pxl errors
$ Y1 E+ L9 F5 @5 \+ j910689 CONCEPT_HDL CONSTRAINT_MGR NO_SWAP_COMP warning after uprev to 16.5
9 `' V' T- }* w4 M$ g" E& b911684 CONCEPT_HDL CONSTRAINT_MGR Attribute Definitions are incompatible for attribute 'HEADER'. when attempting to place in 16.5
# L; M# o8 O: R9 S Z$ p1 Z912343 APD OTHER APD crash on trying to modify the padstack7 B. S& s) U9 h3 s, o: j3 g
912384 PCB_LIBRARIAN CORE PDV Symbol Editor often freezes when moving groups objects by arrow keys2 [. t/ X: ?7 y$ x( \: Z) ]" s
912853 APD OTHER Fillets lost when open in 16.3.- N% J" n c7 Y
913586 ALLEGRO_EDITOR ARTWORK Cannot create the drill figures in this design.
8 x3 M" a) \5 {9 y% }1 O% G: Y, `0 p914009 ALLEGRO_EDITOR DRC_CONSTR Diff impedance worksheet showing almost zero impedance for differential pair in attached testcase.6 }' C- K" ^; s
914110 CONCEPT_HDL OTHER DEHDL 16.5 Uprev overides property values on hierachical blocks& @0 J9 ?& Z, E" u
914264 F2B OTHER Cross Probing from DEHDL for global nets present inside block doesn抰 highlight in PCB Editor.
. w, L0 r! b/ w. i7 R5 Q1 k; T4 u914309 CONCEPT_HDL CORE 16.5 DEHDL crash on saving the user design1 K. l+ R }. F F
914558 ALLEGRO_EDITOR ARTWORK Gerber6x00 output creates unpainted niche in a shape- i( h5 X8 J) W: [0 s! C; a, \$ y; d4 o
914633 ALLEGRO_EDITOR ARTWORK Artwork failing in v16.5 while the same design when downrev'd to 16.3 is working fine.0 T# s. I0 q+ K* a3 T5 g9 b, K( R
914634 ALLEGRO_EDITOR SKILL IsThrough flag for a padstack is reset
3 S; V S" _7 B914746 ALLEGRO_EDITOR DRC_CONSTR DRC Update repeats takes longer on each successive pass.) {6 H4 K! ~- Q+ b
914962 ALLEGRO_EDITOR SHAPE Corruption with Shape filling+ X* H; ^7 E7 `' |0 U
915583 CONCEPT_HDL CORE performance issues in 16.5 compared to 16.3
5 c f1 Z8 x6 Z0 n/ `915630 PCB_LIBRARIAN OTHER Error when running SI Model Interface Comparison using IBIS models# J, l4 f/ A9 s
915742 CONCEPT_HDL HDLDIRECT I get a newgenasym error and crash when trying to save the symbol
9 r; p! o! N2 _9 H. s k! Y! D* Q916154 SCM NETLISTER scm crashes when exporting physical database to allegro
3 h5 p# a" f4 V) e% N6 G2 R7 e916448 CAPTURE NETLIST_LAYOUT Capture 16.5 Layout netlist contains errors
; j1 m" c- _/ R0 y) Q916462 ALLEGRO_EDITOR DATABASE Edit>Split_plane>create hangs Allgro PCB Editor5 B# D" W5 u1 r0 }4 `* Z, K- S% l
916469 ALLEGRO_EDITOR REPORTS One Unrouted pin does not show in Unconnected Pins Report4 y6 h f7 f/ Y4 M2 Z* d) b
916495 ALLEGRO_EDITOR INTERACTIV Pick selects components from invisible (Off ) layer
* a% _5 W* w4 L8 q7 t& X916889 CAPTURE NETGROUPS How to change unnamed net group name?
1 j e. E. _( A! P; q Z( b& a4 [, R917002 ALLEGRO_EDITOR OTHER Allegro PDF Publisher creates extra circles not available on film% a* F" D q" f1 o% u
917434 APD OTHER Stream out GDSII has more pads in output data.
) N; r, P& v0 |/ T5 P2 O917739 CONCEPT_HDL INFRA Global Net tied to port is getting split into 2 nets in 16.5, in 16.3 it is treated as a single net
# M% D& c2 t7 r, V1 P/ w918187 CONSTRAINT_MGR OTHER Missing acGetTotalEtchLength predicate.
- k7 |; A- e, f X: F: K q3 f1 L918576 CAPTURE DRC Incorrect DRC is reported for visible power pins which are connected to power symbol3 Q8 I* A2 w2 t3 H
4 L ~5 p; X+ F2 ~" DDATE: 07-24-2011 HOTFIX VERSION: 002
- Q0 V9 Y& }7 L' B4 d===================================================================================================================================
( t) ~$ e* X4 ZCCRID PRODUCT PRODUCTLEVEL2 TITLE3 ~. u% U4 t% q, W. @3 u
===================================================================================================================================
/ b6 q" _* O1 g0 N. V8 ?527444 ALLEGRO_EDITOR EDIT_ETCH Slide command needs to be enhanced for same net spacings
! ?1 [; L4 U7 ]5 S. d7 W1 R" s583257 ALLEGRO_EDITOR EDIT_ETCH Add Connect and slide command needs to be enhanced for same net spacings. V: g. }4 Y: Y. n
592956 ALLEGRO_EDITOR EDIT_ETCH Same net traces will not push and/or shove each other.
% N# W. h; j0 A2 t745285 ALLEGRO_EDITOR EDIT_ETCH Requesting a true "shove" in Route > Slide for Same net routing.
- s* _3 h+ V( |4 A2 c2 E" E2 J* g773503 CAPTURE OTHER Doing "Mirror Horizontally" creates extra un-connects or extra junction dots in Capture V16.3.6 g) D V- ? W* a( z8 G, c$ n
774270 F2B PACKAGERXL Require to ignore space in Pattern setting to prevent duplicated Refdes.
. V* H f; A* y# A& \6 V, p799984 ALLEGRO_EDITOR INTERACTIV Enhance the Fix command to select just cline segs
4 u U2 ~2 a$ h* V809008 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".
4 m) y) w N( z( h/ q# V d810058 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".
7 E7 _1 A+ z! a6 g/ x* ^+ O821133 ALLEGRO_EDITOR MANUFACT Output artwork for pad data that are suppressed unconnected pads with Gerber 6x00 format) e# j, X3 D% I$ C" }
831710 CAPTURE SCHEMATIC_EDITOR Capture adds extra junctions to design by itself
" _8 o2 L+ C# K9 x7 C5 n842410 ALLEGRO_EDITOR EDIT_ETCH Ability to slide with "Shove" for "Same Net" segments/vias.1 g, I8 E. B$ v. R7 Z- k% B
854971 ALLEGRO_EDITOR INTERACTIV Capability to add cline segment in a temp group
' c! V! z1 U% x# @) |4 k9 }( C860772 ADW PCBCACHE Save Shopping Cart (pcbcache) is crashing component browser
: p: G4 C7 C# s( d- O9 o867842 CAPTURE PROJECT_MANAGER Capture crash with 'Open File Location"
0 t$ {" g1 u7 E% W! {( ?0 _/ w868306 CAPTURE CONNECTIVITY mirror vertically removes junction creates extra nets
2 z4 G' W# {" ?' w4 V" c' p2 p3 |882677 EMI RULE_CHECK bypass_plane_split fail if BYPASS_XXXX_EFFECT_DISTANCE
% U0 |- d' X4 j891439 ALLEGRO_EDITOR INTERACTIV moving cline segments
; U6 ~% H( u4 V n893544 ALLEGRO_EDITOR INTERFACES IPC-D-356A netlist issue with BB vias.
4 E# d7 }4 R3 F& r4 [893765 ALLEGRO_EDITOR PARTITION Mail command not sending out email on Linux platforms.8 c5 L H5 V/ u/ m9 x
894390 SIP_LAYOUT EXPORT_DATA Generate all balls in the xml file for export to EDI's readPackage command
6 l. z& Z$ x8 z' L895933 APD DATABASE Update Symbol shifts the center of the Dynamic Fillet and creating DRCs
3 z: Q3 H) h, O# o- a4 S896598 ALLEGRO_EDITOR PLACEMENT error message is misleading
( A2 q/ E$ I4 g897196 CIS LINK_DATABASE_PA Schematic Contents are not shown in CIS window while link Dbase part for parts placed from library/ |6 s$ l3 C8 V3 d7 \$ P, X
898598 ALLEGRO_EDITOR MENTOR Negative planes from Mentor Board Station not being translated.
0 R7 Y, U7 F! {" z899556 ALLEGRO_EDITOR ARTWORK Import artwork seems not to work correctly.
+ p' e# `0 r; s# \900501 ALLEGRO_EDITOR PLACEMENT "lace Replicate Apply" is showing lot of DRC's during placement of replicated circuit in 16.5
2 J( `& z9 {& i- R0 D901141 CIS EXPLORER Japanese character appear garbled in CIS explorer window.* \- s& ?0 |* d8 H! C/ [
901666 CAPTURE OTHER Home page of Flowcad-Switzerland and Flowcal-Poland is not preserved on captre restart on start page
, S- K8 ` ? ?3 x( c4 h902066 ALLEGRO_EDITOR DRC_CONSTR Shape in Region not follow the constrains3 C) T0 v; ]! X p
902349 CAPTURE LIBRARY Capture crashes while closing library3 y0 P$ O% ?/ y# Q. ], N5 X* ?
902508 F2B PACKAGERXL SPB16.5 Packager-XL consumes much more memory than 16.3
7 G1 {% b2 p4 ^1 P" C$ x1 n902841 CAPTURE GENERAL Capture Start page does not show
1 W8 u" L7 N. {2 O# n$ \902876 F2B PACKAGERXL Packager fails on the design upreved in 16.5
: _# k0 i/ G; G902959 CONCEPT_HDL HDLDIRECT HDLDirect Error while saving design
* U- x, y/ `- W/ M903171 PSPICE NETLISTER Why Capture is treating hierarchical power ports as floting nets in complex heirarchy designs?
) a, n9 }& e- @( j% e903713 ALLEGRO_EDITOR PARTITION Placement Replication do not work fine in the Design Partition: e1 c: q% J" Y- @% L: T8 j
903799 SIP_LAYOUT DIE_EDITOR Disappear die pins after exiting co-design die editor. o3 E1 X. {$ o: q, l
904021 ALLEGRO_EDITOR OTHER Export PDF from SPB 16.5 produces a file not text searchable
* r* c$ V1 [# x0 L% _904339 CONCEPT_HDL CORE new design crashes using the attached CDS_SITE
: y& K) }1 Y$ v8 w( p' ~2 n; x( I904522 F2B PACKAGERXL Part will not package in 16.5 but packages in 16.3
- T2 h$ A7 G1 h. ^- t" J7 v904764 APD OTHER Enhance Scale Factor of Stream Out to support 4 decimal places
$ l: i1 q+ U( G904771 ALLEGRO_EDITOR MANUFACT Pin Number display issue.
) B! j4 F K4 R) Q. x904853 ALLEGRO_EDITOR GRAPHICS Enhancement for showing Static shape as it was seen in 16.3$ o, Z4 J2 O6 Y$ l* {! M4 H! S
905144 CONSTRAINT_MGR ECS_APPLY Min Line Spacing is larger than Primary or Neck Gap less(-) Tolerance but No Warning in CM
' Y4 d q) s- F# C x905314 F2B PACKAGERXL Import physical causes csb corruption
1 [- j! f2 _1 {4 J905337 CONCEPT_HDL CORE ConceptHDL crashes after Import Design process.6 I. }6 s* T8 V+ z4 r2 J
905533 ALLEGRO_EDITOR INTERACTIV Pin numbers for components on BOTTOM Side are moved in Preselect mode,when the BOTTOM layer is invisible
7 V6 M$ V$ D: _7 ?) U$ V905796 CONCEPT_HDL CONSTRAINT_MGR Fujitsu CM issue inaccurate concept2cm diff pair issues
: r) ^5 b! J: l, g' w( D7 F905811 CAPTURE EE_INTERSHEET_RE interesheet references in the form of grid grid page number instead of page number grid
4 ] h, H: S3 c) k7 w906118 CONCEPT_HDL CONSTRAINT_MGR Cannot open CM if SIGNAL_MODEL value was not assigned in ptf.- z- V" v+ b: o1 x. ~0 {
906153 ALLEGRO_EDITOR SCRIPTS Unable to run allegro script in batch mode on the attached board. G! r. b; {2 v# {
906182 APD EXPORT_DATA Modify Board Level Component Output format
U' c+ M# P9 E1 L3 h906200 ALLEGRO_EDITOR DFA Enh- DFA drc invoked in Batch mode returns false constraint value in Show Element
8 @6 Z3 b* Z# Q* P906517 PSPICE PROBE PSpice new cursor window shows incorrect result.: J6 ?$ h* y' l- a
906627 ADW COMPONENT_BROWSE ppt options are not read if ucb is launched from FM. works fine if launched from dehdl.
) e$ n% o: Y8 t9 f7 U. `- H8 q906647 SIG_INTEGRITY LIBRARY lib_dist creates a signoise.log in current directory (with backup files like ,1 ,2 etc.) on each run( K# l( Y" o- X
906673 F2B PACKAGERXL Ignore the signal model validity check during packaging; }: |: ?1 _8 a( l' L* E
906688 ADW LRM A copy of source design gets created in worklib of target design after 'Import Design'6 ~7 P/ i( N* O. [7 J' o) G
906750 ALLEGRO_EDITOR PARTITION Importing design partition removes the testpoint reference designation0 ~ H) s' M! g; p
906874 PSPICE NETLISTER Error less than 2 connections for unconnected hierarchical pin! V- w) X2 Q) g1 Y0 o
907095 F2B OTHER Part Manager does not show Error as Undefined when directive ptf_mismatch_exclude_inj_prop is used
- ~9 V2 b1 q$ L. Q907424 ALLEGRO_EDITOR GRAPHICS Allegro add option for pre 16.5 shape display% _+ f) f. w& e
907490 CAPTURE NETLIST_LAYOUT 16.5 Layout netlist is not correct. It differs form 16.3 layout netlist.
6 F1 c7 T: q# e, Q, B, ^5 F3 Y907884 SIP_LAYOUT MANUFACTURING Need to add an "NC" pin text option for "Manufacturing Documentation Display Pin Text"
& j3 h7 V# e" e. k$ |2 v, Y907885 SIG_INTEGRITY OTHER Matchgroup targets lost when importing netlist to Allegro layout in HF31% P4 w* G9 o4 B+ a( F! z! C6 C
907929 CAPTURE TCL_SAMPLE TCL command to delete a property from parts in a library is not working correctly
7 \" g& g) f" L/ z( G, l907933 SIG_INTEGRITY OTHER Single line impedence not working in OrCad PCB Professional
! r$ B8 F/ k1 i# H907963 CONCEPT_HDL CORE Design uprev issue when moving from 16.2 to 16.5# W; p* ?8 Z$ q
908000 SIG_INTEGRITY OTHER Inconsistence z-axis delay reported on Tpoint when define at via location.
% H+ G0 j2 G+ {& j; T; b( X908057 CONCEPT_HDL CORE DE HDL crash with the cut and paste of a signal name0 i! C' I6 V+ ~; }! B% F
908060 CONCEPT_HDL CORE CTRL+LMB Option not working correctly in 16.3
; ^4 d1 i6 z8 e908210 CAPTURE CONNECTIVITY Connection is being lost while dragging a component- y# ?: l+ l O" x5 S
908241 CAPTURE DRC DRC error column is blank in DRC markers window in 16.5
( V3 o4 ~1 x2 q( _* a& P908339 RF_PCB BE_IFF_IMPORT mechanical holes VIAFC are not at the right place- X" L8 d2 Q! O) I4 Q; ^( L* z
908534 SIP_LAYOUT SYMB_EDIT_APPMOD issues with symbol editor and copying pin arrays" H# z7 o+ G; t4 i& w$ U! M
908535 F2B DESIGNVARI When I try to view my variant file the variant editor crashes
" j- i& ^2 H. o$ K908595 APD 3D_VIEWER cadence Design 3D viewer" screen pops up and is all black because the colors have all converted to b
# [* s1 `8 u9 s, R908849 CAPTURE ANNOTATE Getting crash while annotating the attached design. W% y1 z8 v. T5 \9 g3 j2 t
908874 CONCEPT_HDL CORE Part Manager - No Part Found error when using CCR# 775788 feature
( O" `% M/ X$ s' u' N3 {( `909077 CONCEPT_HDL CORE After packaging pin numbers remains invisible even when $PN
4 S* O6 }: k0 T9 L% H909104 ALLEGRO_EDITOR SYMBOL Warning message needs to be modified. It does not save the symbol and also not tell the actual problem.
; P- ~/ A- z0 b3 g4 \909417 ALLEGRO_EDITOR REPORTS "report -v upc" returns 'Segmentation fault' on Linux/ l1 O: `, @! g2 ?
909635 SIP_LAYOUT DIE_STACK_EDITOR Add Interposer crashes in SiP Layout" h7 b; { T3 w/ f8 X
909749 ALLEGRO_EDITOR MANUFACT Allegro Crash during dimensioning/ t* Y8 R' B4 U h7 I2 O
909760 SIP_LAYOUT MANUFACTURING Create bond finger solder mask doesn't follow the mask opening as defined in the padstack* k0 H: m# C. n5 L5 [4 G- @6 D9 A
909861 F2B PACKAGERXL NetAssembler broken within the latest 16.30.031( S, B9 z8 b, M& ~
910006 CONCEPT_HDL INFRA Motorola design fails to uprev from 16.3 to 16.5, xcon file is getting corrupted.& G3 y. p7 N: [; J
910141 CAPTURE NETGROUPS Modify NetGroup definition does not update Offpage Connector
3 b m2 E5 l- _. S% U910340 ADW LRM Import design in schematic, only 1 page import, the entire block is getting imported.
: o& w$ C) O3 x" a910678 SIG_INTEGRITY OTHER The Analyze> Model Assignment> Auto setup is not creating/assigning models to discrete components in 16.5
! _7 ?. R, Z$ v910713 F2B DESIGNVARI Variant Editor crashes when you click web link under Physical Part Filter window.6 ?/ M2 q! u5 P9 g/ c N
910936 F2B PACKAGERXL ConceptHDL subdesign net name is inconsistent
4 I# d/ w5 w5 D# Z4 l911530 ALLEGRO_EDITOR SYMBOL Package Symbol Wizard does not create symbol with the name given
" r: F# c1 ?; ^3 r u1 Q911631 CONCEPT_HDL CORE DEHDL crashes when opening a design+ v$ U U C5 N% D1 t$ ?
912001 ALLEGRO_EDITOR OTHER option_licenses entries are made in allegro.ini even when not set as default
0 k. l% l5 s; y. t/ d7 T. q912459 F2B BOM BOMHDL crashes before getting to a menu, Y4 N# B$ m5 ~ ?
913359 APD MANUFACTURING Package Report shows incorrect data
5 Y3 a4 a* B7 Y5 N
! Z0 ^/ D, H# h4 Z0 PDATE: 06-24-2011 HOTFIX VERSION: 001- b! G A4 d5 u; ?0 e$ Q& T
===================================================================================================================================) K8 s, H2 t( L9 d F
CCRID PRODUCT PRODUCTLEVEL2 TITLE
: I9 u# `" p# E e0 x===================================================================================================================================
; A/ l0 @( D5 P" Q' k293005 ALLEGRO_EDITOR DATABASE Allegro crash when attempting to move mech. symbol
) p g3 N# J- f0 q2 D; `298289 CIS EXPLORER CIS querry gives wrong results
" Q7 Q) N) o# F( c366939 ALLEGRO_EDITOR OTHER Cannot attach refdes on silk subclass with add text8 z! }7 z4 |4 K% t" b7 Y
432200 ALLEGRO_EDITOR MANUFACT Fillets with an arc are required for Flexi designs
+ o# Z+ Q" n1 S. G$ F9 J443447 APD SHAPE Shapes not following the acute angle trim control setting.( f' s( |! L9 ?0 p6 j
473308 PSPICE AA_SENS Passing variables to lower level blocks using subparam
5 Y$ |$ k" C5 i. N J p# t9 w, U517556 PSPICE AA_SENS Advanced Analysis does not support variables being passed down the hierarchy
' S4 h6 i# y/ P* O$ X548143 ALLEGRO_EDITOR SHAPE Dynamic shpe on Etch TOP will not void properly./ \# ?5 l) I! m* D8 e' ]
606959 ADW COMPONENT_BROWSE Key properties with blank values are not getting read in shooping cart) `0 }0 r, ], U0 |
616466 ALLEGRO_EDITOR SHAPE Solid shapes are not getting filled
1 u1 e5 f6 }' L& Y b641358 SIP_LAYOUT DIE_STACK_EDITOR Request for Via and Multi Layer Pin support for DIE stack Area (blue region)
6 e1 S$ k6 O" M: Z644122 SIP_LAYOUT OTHER SiP Layout - xsection - ERROR Adjacent conductive layers are not allowed, but these are diestack layers not conductor, @' I% s# W" f p/ V) J
645816 ALLEGRO_EDITOR SHAPE Slide a cline all removes gnd shapes on board
9 c' K& w! C2 p: U+ q9 O- ?725355 ALLEGRO_EDITOR SHAPE User can not voided Logo correctly.5 g u. M4 n, K" l! v/ h8 }
763569 CONCEPT_HDL CORE Display status of Hide/Show unconnected pins icon in DE HDL UI/ ]5 }! S) V6 b1 ^. R- t
770021 CAPTURE BACKANNOTATE Changing pin group property after pin swap resets pin numbers, @6 ^" k3 h$ A6 G4 z' |9 z
792126 CAPTURE PROPERTY_EDITOR Attempt to change display for occ prop resets
0 G/ x7 ]2 G4 V799014 CONCEPT_HDL CONSTRAINT_MGR concept2cm errors not shown in export physical after hier_write
- C8 _7 Z0 a! a7 F5 T) t803147 CIS LINK_DATABASE_PA Link DB part should not change RefDes of multi package part+ l. H2 X: Q( R: u9 ]
804240 PSPICE DEHDL Problem in simulation result for a multi-section split part.; }. A; Q7 B/ G" }/ O; e
809118 CAPTURE NETLISTS ENH to compare two schematic Capture designs! F1 ?9 v- @% d/ \6 X+ w. G
816568 ALLEGRO_EDITOR SHAPE shape disappears when update to smooth.. State no etch
; K h0 s5 R7 f9 C; n7 ?; G3 Z830053 CAPTURE STABILITY DXF export fails if schematic folder name as /
2 F9 i4 y9 u- f, A832108 ALLEGRO_EDITOR SHAPE Shape void incorrectly., ~5 t9 c* a; H) i1 x
833542 CONCEPT_HDL CORE PDF publisher font is NOT WYSIWIG with respect to what seen in DE HDL5 I1 T5 Q I- h& }- v
835777 CIS DERIVE_NEW_DB_PA For XLS, donot display table as worksheetName$worksheetName to avoid 8012 error% }# g- t6 [4 u
837640 CIS GEN_BOM date format of CIS BOM has broken macros of 16.2 in 16.3 version( A: P4 G% e1 y" G
844074 APD SPECCTRA_IF Export Router fails with memory errors.
7 p* c+ k4 G. S, m2 X3 |851595 CONCEPT_HDL CORE Pin numbers overlap on the pin and increase in size& V) n* g1 V& _; c& c9 }" o
852832 CAPTURE BACKANNOTATE Why is Capture crashing with Mentor back annotation?
, A! V4 Q! ?, W2 v" b# z$ x" v$ \: h855015 ALLEGRO_EDITOR OTHER The rats are NOT connecting to the ends of the clines like they should be.3 ]; T/ `3 o" B0 f. I
859883 CAPTURE NETLISTS ENH to compare two schematic Capture designs
& c! ~! H& [& X7 y3 {# B z9 x866009 SIG_INTEGRITY OTHER Net with Pull-up/down should not be used for Diff-pair.
/ L0 p2 Z; r# ]866830 SCM REPORTS Multiple lines added as separator between title block and report header instead of single line+ d; H9 ]6 x. S: h, i
866833 SCM REPORTS Extra indentation is left in the left side of the report when the Line Numbers are set to OFF) Y% q7 S" `1 {
868618 SCM IMPORTS Block re-import does not update the docsch and sch view* l" C- ]. }- T6 x" k
873402 SIP_LAYOUT LOGIC pin swap for co-design die in SiP7 a: h, J6 v3 t1 v
874010 SIG_INTEGRITY OTHER PCB SI crashes when the Xnet is extracted with VARIANT_TO_IGNORE property.
4 q" `4 w9 F2 M5 H" k2 e6 l& W! B874400 ALLEGRO_EDITOR INTERACTIV Flip mode issue with move command0 L. P! Z: y- q5 y- r4 Z; n
874966 ALLEGRO_EDITOR INTERFACES Placed mechanical component do not get Ref Des or part number in IDF file X+ f$ f' ^0 S! P
875709 ALLEGRO_EDITOR REPORTS Film area report generated incorrect data at l1
; P" U+ r7 d9 u# l4 p876275 CONCEPT_HDL CONSTRAINT_MGR Constraint Manager not retaining target net
M7 |+ v+ x8 O) p& h8 h% x9 j; N879361 SCM UI SCM crashes when opening project7 y9 z x, v9 r7 v' Y! }
879496 CONCEPT_HDL OTHER Customer wants to have the tabulation� key as separator in HDL BOM.0 \; n# E' m }; d3 X3 ~& X% l, l
879514 PSPICE AA_MC Monte Carlo to handle equation as comp VALUE.1 s# P" D) \/ u. G6 Z
881845 ALLEGRO_EDITOR SHAPE Delete island deletes complete shape
8 E7 x" g, W* [8 }& u, t2 \3 W882413 PDN_ANALYSIS PCB_PI PDN Analysis should support routed power nets% Q, r; W& N& h% N, e: m: `1 r6 f9 y
882427 PDN_ANALYSIS PCB_PI PDN Analysis target impedance should have a variable multiplier
9 X- l8 C2 q; m: [3 ^882567 SIG_INTEGRITY OTHER PCB SI crash if boolean type prop was specified to VARIANT env.7 Q& |) x$ _) C* v5 U
882644 ALLEGRO_EDITOR PLACEMENT PCB Place Replicate Function automatically match Enhancement% I6 a, C4 c$ u% [ w! c8 U2 f; C F
883164 ALLEGRO_EDITOR INTERACTIV Vias marked fanout moves away from position when moving component
3 y7 G+ T4 n6 G6 b883224 SIG_INTEGRITY SIMULATION crash while reflection simulation from Constraint Manager
; l: Q9 [, F) F0 F+ T883760 PCB_LIBRARIAN METADATA Incorrectly formatted revision.dat file in the metadata folder0 i& Z% b+ ~/ n7 F
885391 SIG_INTEGRITY SIMULATION RLGC data sampling algorithm and w-element interpolation.
/ `2 R: k; z, v* e' p885849 ALLEGRO_EDITOR MANUFACT Silkscreen Audit cannot find Solder mask for the text string
! L( S. r. t2 _885996 SIG_INTEGRITY OTHER The effect of sn_maxwidthlimit user preference is not seen in cross section impedance calculations
) P) x& @7 Z/ X& S. F [886090 ALLEGRO_EDITOR INTERACTIV Add Arc w/Radius does not snap to grid
! @% |; |, [" e- N( p" k V887180 CAPTURE SCHEMATIC_EDITOR Signals Navigation window doesnt get updated for Buses
3 n: D1 S8 h% H; J( F X1 L3 w: Z1 @" B887442 APD SHAPE Copper pour of Dynamic shapes on Top layer which contains many existing signal traces fails.
' E; K' C- O3 p8 b887578 SCM AUTO_UI Component Replace pops-up the DSPANE-204 Message
! p1 @. p h9 I, v- X* C887926 SIG_INTEGRITY GEOMETRY_EXTRACT Field solution failed if diff trace on bottom doesn't have reference plane.+ |/ R/ X8 y# ?- F0 `
888414 SIG_EXPLORER OTHER View Trace Parameter display the thickness of dielectric incorrectly.
: o* }3 H7 U$ w$ [) g# T888600 CONCEPT_HDL CREFER Cross References not added to Schegen schematic
* g" g1 `* B# N888679 SIP_LAYOUT SHAPE Can't create the Dynamic shape on layer M1_sig without unwanted horizontal openings appearing.+ T( l9 p @+ t2 \
888804 ALLEGRO_EDITOR OTHER Fillet will become static shape after import from partition board.
' t9 Q5 V1 c, N' ?888945 CONCEPT_HDL OTHER unplaced component after placing module6 [3 t( y5 o) X% B
889222 ALLEGRO_EDITOR SHAPE Allegro freezes/hangs when adding shape as Polygon with OpenGL ON.
2 Q7 N& c) e2 F; t8 Y6 E8 r% P: a. ~! b889365 SIG_INTEGRITY GEOMETRY_EXTRACT top/bottom trace impedances extracted to sigxp are wrong in 16.3
Y/ |$ ~( Z5 U, i889404 ALLEGRO_EDITOR OTHER Incorrect pad size for Top conductor padstack written to column 59-62.7 i* J" R j' v2 [0 W" f
889426 CONCEPT_HDL CHECKPLUS CheckPlus does not find single node net
! o, S& P; F7 y2 k889636 ALLEGRO_EDITOR MANUFACT Incorrect spelling of "Visibility" in "Film Control" tab in the Artwork Control Form: X4 q; c C9 v5 I: e
891235 F2B PACKAGERXL Packager crashes without creating a pxl.log file) S9 U) E3 O- ]( ?/ t" \- R7 J
891292 ALLEGRO_EDITOR SHAPE arc routing causes weird undesireable shape fill performance) i. k: [4 I1 ]: `$ T7 \* Q- R
891856 ALLEGRO_EDITOR EDIT_ETCH crash when sliding diff pairs3 F& r6 Z+ h9 D/ B$ \$ G
892375 ALLEGRO_EDITOR PLACEMENT Place Replicate Update disband other groups, irrespective Fixed property added or not.
q: x4 B7 c' F7 n1 \' @! M892455 ALLEGRO_EDITOR SYMBOL Why the overlapping pins are not reported with DRC?. |, `: l+ K- y! z* `
892541 SIG_EXPLORER OTHER Export/Import layerstack through the technology file is changing the layer thickness7 o4 M: C& [# I+ S" F2 n( l1 r
892766 APD WIREBOND Excuting Finger moving cannot push aside finger to move with together by shove all mode1 o% E$ u+ T+ U0 x$ e, \$ K
892907 ALLEGRO_EDITOR DRC_CONSTR DRC not reported for etch_turn_under_pin violations
: L/ K2 [& D( L892963 ALLEGRO_EDITOR SKILL Bad shape boundary created after axlPolyOperation 'OR
! q& O7 X, X9 X" ]" v% a' T$ [892964 SIP_LAYOUT LOGIC Request that Edit Parts List use Dashes "-".
+ l( [# V0 h: u1 B+ v893295 APD WIREBOND Why move wirebond command does not shove wirebonds? This result in drcs.& r9 \4 d/ Q% B6 u4 @" e/ K
893706 CONSTRAINT_MGR OTHER On line DRC hangs on partitioned board
+ g+ B7 c ]' @6 A893743 APD EDIT_ETCH Route behavior when spanning pads not as expected.- d! W! t% X& N2 r I9 S
893783 SIP_LAYOUT OTHER Padstack Design Editing update File menu with a Update to Design and Close instead of 2 operation
' m! ~6 m, X; e- P894456 ALLEGRO_EDITOR REPORTS Request Net names be added to Propagation delay lines of the DRC report.) \$ }2 y$ Z+ a# u
894499 SIG_INTEGRITY LIBRARY Tool crashes when moving a cline or selecting the Info icon with OpenGL on.
2 y' P* c" L0 n894582 APD SHAPE When making a dynamic xhatch Via shapes surrounding are abnormal.
$ A& D% d1 a1 D/ T895542 SIP_LAYOUT WIREBOND SIP design crashing when moving bond finger using blur mode BLUR_BONDFINGER_PRESRV_CON
! U( j3 @0 L; m% V: @895591 ALLEGRO_EDITOR PCAD_IN Importing PCAD file fails to get to the point where we can map layers
: @( H. D3 C/ f1 J895757 APD ARTWORK Import Gerber command could not be imported Gerber data
# q5 i& `9 R* b$ e- W9 o" n( z895964 CONCEPT_HDL CHECKPLUS The CheckPlus command getFileSubstrings is not working correctly" A. p! w$ c( f! _
896428 SCM UI Changed Ref Des value not maintained in DEHDL block when part is replaced
5 ]/ h) d! @% E6 }, c2 J896655 CAPTURE EDIF Import/Export Design of Hierarcy design with OrCAD Capture
X& s0 h$ u3 e' b) v9 k3 H896846 CAPTURE IMPORT/EXPORT Import edif2cap and capture is crashing
, B: r% n& c6 E2 L897155 ALLEGRO_EDITOR REPORTS Copper coverage in L2 and L7 looks like the same but film area report had large gap.
$ r. [: J' @" J" R; b897654 CAPTURE EE_INTERSHEET_RE Capture crashes on adding intersheet refernces in abbreviated format on attached design." D0 N. g" l4 Q# V5 B3 n
899344 RF_PCB BE_IFF_EXPORT dlibx2iff does not provide the component boundary drawing
/ _+ |" R2 x4 B6 S899629 CONSTRAINT_MGR OTHER ECset for Total Etch Lenght is not present in OrCAD Prof; p a+ y$ n6 R4 V
900175 CONCEPT_HDL CONSTRAINT_MGR Few Xnets are lost from Match Group after packaging and importing the netlist to board file.
7 _9 }. i2 j& ?4 r900481 CONCEPT_HDL CORE Genview creates a larger symbol without taking the no. of pin in consideration
* g5 ]( C, \$ b, Z& n900813 ALLEGRO_EDITOR DRC_CONSTR With rotated pads, pad (pin - via) soldermask spacing DRC is unreasonable.
" M" H1 p; E3 ?900905 PSPICE STABILITY Simsrvr crash and RPC Server unavailable error while running simulation.
# q. z1 q6 J. f8 l; k901783 CONCEPT_HDL CORE CDS_PART_NAME is annotated on the schematic canvas after running back annotation in 16.5
: s S3 h4 G( F- c }/ R. K901909 APD EXPORT_DATA The "package_pin_delay_length.rpt" with Z-axis delay turned on seems wrong; u; C( i6 g; I! j2 q
901987 CONCEPT_HDL OTHER SPB16.5 zoom fit does not center the page while ploting the schematic page5 ?/ a3 _# r9 E+ I3 H
902133 CIS OTHER The visible part property value are being shown very distant from part graphics on schematic
- k; S! o/ a, `& D" R0 t902166 SPECCTRA ROUTE Specctra crashes when reading in "bestsave.w" file9 e9 j7 M L: S: M; h8 b- O
902170 ALLEGRO_EDITOR DATABASE Diffpair Issues with OrCad PCB Designer Professional
+ }! f. y$ ~* t; T902177 CONSTRAINT_MGR CONCEPT_HDL Option to view the layer thickness in CM worksheet through worksheet customization3 g1 Q0 b2 D0 \8 [
902463 ALLEGRO_EDITOR INTERACTIV APD crashes when we click ( show element ) on certain components
1 c: v- F) |' t) o902621 CONCEPT_HDL OTHER Design Differences (vdd) Crashes3 H% t5 n2 l2 J$ ]
902909 APD WIREBOND die to die wirebond crash
0 F1 F+ J, f2 O) W7 ?902933 ALLEGRO_EDITOR PADS_IN Pads_in fails while reading PADS ASCII file body5 G6 m2 `9 |: i. R* P& ^( B
903284 PDN_ANALYSIS PCB_STATICIRDROP IRDrop voltage gradients are plotted outside of the PCB outline6 m: T c3 N* Y) M) s( G& P% U+ B/ B
903680 CONSTRAINT_MGR ECS_APPLY Constraint Manager not passing all hiearchical member objects to a custom measurement./ v+ }8 A; f6 f9 ]% g( }
904403 ALLEGRO_EDITOR DATABASE Allegro crashes when refreshing module |
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发表于 2012-2-21 14:58
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