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) N- f) j0 ` ?0 S' jDATE: 02-17-2012 HOTFIX VERSION: 0160 O7 _) a" s) Y# {' Z, T7 p! {9 r
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
1 d: r. h; o3 M2 ^# L, n9 F/ Z* ?/ j===================================================================================================================================
8 Q; u2 |/ C. r% @840105 PCB_LIBRARIAN USABILITY PTF subtype is getting changed when Save As option is used in PDV: J) @& U, \1 A
873075 Pspice PROBE Decibel of FFT results are incorrect.
_! _$ T, m, O3 @. Z, C7 @! `938744 ADW COMPONENT_BROWSE Need ability to customize shopping cart columns to include any Part property' ~' u" |; Z# q3 _* W" y( i
943003 SCM REPORTS The dsreportgen command fails with network located project
/ B/ j, B! S# m& p961530 allegro_EDITOR INTERACTIV The problem of Display measure command% D' k9 t2 M9 U" E
962157 concept_HDL CORE Where is the setting for enabling the Enable PSpice Simulator menu?8 d/ h# v+ |; z3 ~
962206 CONSTRAINT_MGR CONCEPT_HDL Import physical not passing all constraints from the board to frontend
0 @6 d# X' w1 E+ x2 s/ f968205 PSPICE DEHDL_NETLISTER Change SPLIT_INST property to PSICE_SPLIT_INST for Quad Switch type of design.
6 c# \7 E# P. h5 ]* A/ ^( D968509 PCB_LIBRARIAN METADATA Incorrect pinlist.txt was generated if DIFF_PAIR_PINS_POS/NEG was set.
4 |0 Z( w, \2 ?" S( I) }9 _) A7 Y969450 LAYOUT TRANSLATORS orcad Layout to Allegro Translator crashes
* L! n0 D. B# a+ a% l) N969997 CONSTRAINT_MGR CONCEPT_HDL ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance pro~" V' s+ V+ y6 D) s5 I
971193 CONSTRAINT_MGR UI_FORMS Copy and pasting a formula causes the application to crash on windows.
' L8 F& o' V& `, J4 i g9 L# K971601 CONSTRAINT_MGR CONCEPT_HDL ERROR(SPCOPK-1053) and WARNING(SPCODD-66) because of directory structure
$ f9 d% U. l' w" R7 A973398 CONCEPT_HDL OTHER It should be not packaged with error while working the packaging process if the design has a ERROR
* b; @+ E \+ u1 |/ F973859 PSPICE ENCRYPTION Pspice crashes with encrypted model
- ?% m9 p( G$ N/ J. [973938 PCB_LIBRARIAN VERIFICATION pc.db is missing
' M' [7 N s0 p974540 CONCEPT_HDL CORE Graphics updates are real slow
- f: |* P z5 g5 q y& o974791 F2B DESIGNVARI Variants are not back-annotating to schematic and turning to ?
- M# M; ^1 \$ T4 v& A+ w974818 ALLEGRO_EDITOR NC Backdrilling produces 0 plunges yet no errors reported.
! u) W' }* O @+ m9 X( U8 H4 k974945 ALLEGRO_EDITOR skill Why is axlPolyOperation is giving different result and not working
& B- e" m* B7 W0 W8 G* F974946 MODEL_INTEGRIT TRANSLATION ibis2signoise returns the error - Delay measurement fixture must contain V for ECL technology m* V* Q( V8 `4 k& [* K/ n
975396 CONCEPT_HDL CONSTRAINT_MGR Constraints are dropped after migrating from 16.3 to 16.5* @% f6 r& b- m* T/ v) F
975633 ALLEGRO_EDITOR GRAPHICS 'dynamic_layer_visibility' option in 3D Viewer when checked or unchecked should not change (until next change): b' n5 m8 {3 m: Z* B
975720 ALLEGRO_EDITOR DRAFTING Datum dimension lines not adjusting to text move( b! Y+ |: W/ j& f' M$ l
975745 ALLEGRO_EDITOR SKILL cdsServIpc different 16.2 vs 16.5 when Allegro exits
1 ~* s/ ^8 e5 R976013 CONCEPT_HDL INFRA Power pin connection of FPGA symbol is missing in netlist./ B, I2 Z- N+ }6 u
976058 CONCEPT_HDL COPY_PROJECT SCM Copy project does not create the con and dcf files in tbl_1 views
8 f# H) \& R/ u8 Q0 D976073 CONCEPT_HDL COPY_PROJECT All the constraint data is lost in the SCM copied design
8 V3 C- i O, |976160 CONCEPT_HDL CREFER Cref fails due to some Caeviews error in the design
! k8 D& X+ }7 y- r) L* R976204 ALLEGRO_EDITOR DRC_CONSTR Application falsely reporting Mechanical Pin Antipad to Shape Spacing DRC J8 c- d) a3 J' t1 y) t) x' b
976448 F2B PACKAGERXL ERROR(SPCOPK-1069): Invalid POWER_GROUP property value
: z2 c4 _+ b$ o; T% ]! }976521 ALLEGRO_EDITOR DRC_CONSTR multi-thread update DRC causes the application to crash5 Z/ p D8 e: C9 d8 e6 \& @) |
976838 SIG_INTEGRITY OTHER Unable to create XNET for highlighted nets on attached database even after assigning proper Signal Models.2 S( _6 n7 ?8 L! k) F! ^
977517 F2B PACKAGERXL Export physical fails after update to 16.5 from 16.3
4 q) D5 Y h" ^! T" M) q5 }977902 ALLEGRO_EDITOR DATABASE generate module is crashing allegro* t; D1 e ], ~' _4 ~ E
978652 ALLEGRO_EDITOR pads_IN PADS_IN fails with ERROR: Finished with errors.% l0 { g4 T; s3 b, q
978744 APD DEGASSING Some shapes will not DeGas on this design* _" L4 x* e% t2 U( _1 t
979940 SIP_LAYOUT OTHER SiP Layout Leadframe autobonding with profile selection6 h) W* Z8 ^$ T: h( \5 R$ W
981699 CAPTURE HELP Start Page still shows Hotfix 14 after installing Hotfix 15' Y1 G# r5 P* q' K+ x& c- [
+ Q& P4 w+ O6 G/ `% VDATE: 02-03-2012 HOTFIX VERSION: 015" G# P- F* n; ?" h- t1 I+ k8 ^! H
===================================================================================================================================
9 s" E/ n" B: v) ]7 dCCRID PRODUCT PRODUCTLEVEL2 TITLE
! I0 U6 d+ {+ D/ o- b+ J===================================================================================================================================( Q, G: _8 m4 j, E$ v
871567 CONSTRAINT_MGR SCHEM_FTB Ability to filter out Single Node Nets from Constraint Manager4 W4 a# U* X6 g0 D. ?1 f3 ?
921436 ALLEGRO_EDITOR MANUFACT Change in 'decimal place' for new dimension changes the already placed dimension; k% R. M* |0 ?% ^
941433 CONCEPT_HDL COPY_PROJECT 16.5 Copy Project should warn if trying to copy a 16.3 design/ T$ u& G, ^2 C
954375 ALLEGRO_EDITOR MANUFACT Change dimension accuracy for few instaces of associative dimensioning! B/ p& V3 p0 p* r2 R) N- P- D
961646 PDN_ANALYSIS EMVIEWER EMViewer Help > About shows wrong version
0 f% L' _3 r" e* @! b" m5 B# d964912 CONCEPT_HDL COPY_PROJECT ASA project crash after using copy project
- ] |+ l) l1 G, s3 O967223 ALLEGRO_EDITOR MANUFACT Bug:Oval slots orientation in one direction only* }% y; u& t, S4 H- P Q2 T T- R
968865 SIP_LAYOUT DIE_ABSTRACT_IF load of die abstract fails due to differences between component and symbol
$ j" E% }5 e' P# w0 y969485 ALLEGRO_EDITOR SHAPE Shape does not update correctly in 16.5
$ N/ ?4 ]+ C& Z6 |' x+ z' i970331 CONSTRAINT_MGR ANALYSIS Impedance worksheet shows a zero value for impedance
, J# P# g# S- i; u; k970600 SIP_LAYOUT SYMB_EDIT_APPMOD Option in Die Editor to be able to "physically swap" pins
% i0 [: k0 N+ {& v970910 F2B PACKAGERXL Our customer has problem with pin color after pxl 16.5.5 {; Y6 g) I. H( h7 q( F
970970 SPECCTRA FANOUT Fanout Vias is placed far away from decaps and does not change the Fanout length even when max_length is reduced." Y; y# J( T; F3 J6 A n
970985 SIP_LAYOUT OTHER Importing a .spd2 database file using NA2 will cause the APD/SiP tool crash
) d8 f; X8 C% N. N5 n9 ?3 T- u971757 CONCEPT_HDL INFRA Crash while Saving/Packaging the Design a2 }/ B. M. ?5 n
971923 ALLEGRO_EDITOR MANUFACT Allow to change decimal accuracy for dimension instances8 J; k/ k7 S( ?0 k2 L
972568 CONSTRAINT_MGR UI_FORMS Tools >Excel missing from CM, C5 m9 n$ z' G$ O* e1 P
972821 CONSTRAINT_MGR CONCEPT_HDL connectivity server warning: Unable to add property WEIGHT) ~8 ^( `6 Q' V0 n0 b$ G
973185 SCM CONSTRAINT_MGR ASA2 block not seeing all instances in a package.5 A! T, ~6 v( d
973211 ALLEGRO_EDITOR INTERFACES IDX Object Type Change not recognized9 @; g8 b% |. a
973214 ALLEGRO_EDITOR INTERFACES IDX import package keepout height value change assigns incorrect value
. V# B8 x5 X% u' p973384 CONCEPT_HDL CHECKPLUS The multiple SIG_NAME has to be occurred an ERROR at the SPB16.5.
4 p0 N2 [$ F, v1 N% b973514 SIG_INTEGRITY OTHER Mapping error when Ecset is updated to constraint manager from extracted net: G. f8 @$ T3 v0 z7 X$ O" @3 o
973950 ALLEGRO_EDITOR SHAPE Update to smooth crashes application0 z+ N* X* H, Q# K/ G1 Z! Q6 m
974533 SIP_LAYOUT OTHER Crashes in Edit > Die Properties and obviously has a setup problem.; L; C% q( [8 @0 ]( B2 L
974809 ALLEGRO_EDITOR SKILL argument available for hiding a property with function axlDBCreatePropDictEntry is not working
# H3 T2 b. T8 Q- F; C976179 INSTALLATION ISR Installation of ISR S014 to 16.5 on windows is breaking the documentation index, [, B5 i! E7 D+ ]$ P8 h3 L3 Q
# `: U- g; U' x1 X, z& H. P% ]% eDATE: 01-20-2012 HOTFIX VERSION: 014
2 V5 i: q2 @% o+ f. S$ U/ q ^===================================================================================================================================
3 z9 g6 S/ e: ?7 FCCRID PRODUCT PRODUCTLEVEL2 TITLE1 i8 h7 A2 p& r3 `7 [5 ?( C
===================================================================================================================================
" `' c5 U, I$ q& r733285 PSPICE SIMULATOR Enhancement:In server-client installation use existing index file from server
4 I$ x9 }) `4 g5 F5 z y. S8 v941020 SIP_LAYOUT OTHER Soldermask enhancement8 f. ~) `( {6 J, Z2 R
946407 CONSTRAINT_MGR TDD When is it safe to open a 16.5 design in 16.3?
+ _) p4 x% p: o6 N* _# b# j8 T953067 CONCEPT_HDL OTHER Variant Editor "Error/Warning messages" form is unusable2 _5 v) S( [ m X( S
954818 CONCEPT_HDL COMP_BROWSER Replace button turns to Add in component browser when a component replace is done on the schematic/ b% d& i/ p. @, e8 Z) Y6 S" T, @
956450 ALLEGRO_EDITOR DRC_CONSTR Analysis always shows analysis failed in uncoupled length in some diffpairs' z$ c. }& d# E d8 `
958259 F2B DESIGNSYNC ds.exe crashes on a big design when accessing the design from network drive+ ]: J8 A9 h" E9 e
958395 ALLEGRO_EDITOR SHAPE shape voids won't merge
" i/ W9 G- r3 S% k2 q5 z% E959212 MODEL_INTEGRIT PARSE Attempting to use "Mark qualified" option on DML File results in dmlcheck and Modelsim wanrings.) Z2 A+ u# {7 c9 q
959940 APD AUTOVOID Void all command gets result as no voids being generated.3 A7 e) R& z2 G: [
960252 PCB_LIBRARIAN CORE Splash screen in PDV prevents showing error message4 @! H* F- ]2 s
961634 PDN_ANALYSIS EMVIEWER Cannot launch PDN EMViewer from withing PCB SI
2 r, j$ N4 J3 ?$ Z: J; l961645 PDN_ANALYSIS EMVIEWER Standalone EMViewer will crash when opening any result file in the form of *.emv file.
. b5 o) z( `3 f961700 ALLEGRO_EDITOR SHAPE dbdoctor reports ERROR(SPMHUT-144): Illegal arc specification# Q" U: E! Z4 B+ T6 R( x
961733 ALLEGRO_EDITOR SKILL Allegro crashes. Appears to have a memory leak.' t+ @! Z2 F8 J' G$ Z. Z2 t7 J$ }
961758 ALLEGRO_EDITOR DRC_CONSTR DFA check produces no DRC when the dfa bounds are not a rectangle." s8 v) @1 O, R
961887 CONCEPT_HDL CONSTRAINT_MGR Match Group created from ECSet cannot be deleted in the same session of CM E* t0 m4 A4 @
962552 APD EDIT_ETCH BUG:APD crashing when we try to slideget information but move works fine
% m. ~5 Z+ P* Q9 r, A4 U) Y/ a962869 CAPTURE STABILITY Capture crashes after RMB click on rotated parallel wires
9 q- S: C& i- v; z- {4 P0 |1 ^963232 CAPTURE MACRO Macros not being played in Windows7
# F! Z+ [9 u. [8 F N" d- \963300 ALLEGRO_EDITOR DATABASE Create > Module crashes in 16.5 but not in 16.3
# [) V* R$ q1 |. ?- N/ N4 d963651 CONSTRAINT_MGR CONCEPT_HDL ECsets are renamed after packaging on linux4 ~$ c* P) W4 y0 H& w
963663 CONSTRAINT_MGR ANALYSIS Q- Why the customized worsheet for Diff pair Impedance not analysing at all for this SIP design3 m2 {/ U/ }7 H4 d# Q
963715 SIG_INTEGRITY OTHER Application only adds the bottom conductor thickness for the via z-axis length
' o2 X4 U: M9 M+ S/ F2 S4 n964068 ALLEGRO_EDITOR INTERACTIV Allegro crash when using move alt sym mirror alt sym...: a9 n) _+ J$ h; D) z& T2 ]
964267 CIS PART_MANAGER Capture become non-responsive, working on Part Manager and creating CIS BOM, for large designs3 [+ M- Y+ |, j& q% D
964597 ADW LRM Issue of LRM license checkout after renewal license by 16.5 (ADW15.5_S23+SPB16.3); e8 A7 i# h: n) E4 C% l, V& U
966148 APD INTERFACES Character Limit for DIE Files (*.die) Import
6 T7 M6 w; @, x8 |: `4 `966416 F2B PACKAGERXL Cannot package this design
) b' } e2 {; r5 } [9 Y' S7 U5 i966421 CONCEPT_HDL CORE DEHDL Crash when applying property on components in duplicated blocks
( I; R' B7 I! g966693 CONCEPT_HDL CORE DEHDL crashes when doing model assignment if CM is open
. _; T: z4 H s0 S966795 ADW ROLLBACK rollback utility does not honor -product option from command line
! F/ U5 @+ p) h: D967089 SIG_INTEGRITY OTHER Matchgroups created by ECSet not deleted when ECset is removed from object.; f- A8 q% |7 ?5 p! v, H
967222 ALLEGRO_EDITOR OTHER PDF export is leaving data off the drawing/ C0 M2 J9 x5 i( E$ t, s! H
967240 SIP_LAYOUT WIREBOND Change default bond fingers selected on multi-site leads during "bond to leads" program
' j! L8 h: @" I967297 ALLEGRO_EDITOR OTHER Dynamic Fillet&Eliminate unused stacked vias cannot be used as the Miniaturization option.4 l, F) I" F+ w2 Y# M/ J1 s
967576 CONCEPT_HDL CREFER Occurrence location property values do not appear in flattened schematic generated by CreferHDL
( J+ W% q$ N$ [$ p6 v968096 ALLEGRO_EDITOR DRC_CONSTR Mechanical Pin to conductor spacing is not followed.
5 \# i; q7 F4 d7 v968222 SIP_LAYOUT DIE_EDITOR die pin loses IC net for a co-design die with multiple ports within IO-cell
) N4 M- l' y0 Y1 B* O7 P5 i968358 CIS PART_MANAGER Capture crash on removing a part from subgroup in part manager
^- l! J/ g, i! |2 d969594 CONCEPT_HDL CORE The dcf file is not updated with schematic changes
- ?$ I. H5 ^1 n2 ^
7 J5 P9 d* f1 _" _& R- k0 HDATE: 12-16-2011 HOTFIX VERSION: 013( J o2 @9 E1 c
===================================================================================================================================
2 a: o3 }9 c8 ^5 D2 Y8 JCCRID PRODUCT PRODUCTLEVEL2 TITLE# d; M+ s2 B0 Z
===================================================================================================================================- [" t3 Q; ?4 e5 _$ ~& Y. K6 S _
875695 SIG_EXPLORER INTERACTIV Enforce Causality check box doesn't work.
" `2 T) b: ~/ c _% Y927148 CAPTURE PROJECT_MANAGER Capture crashes on creating scehmatic folder with name which already exists in design
, n( ]# \8 y8 f938013 CAPTURE NETLIST_OTHER The netlist in RINF Format contained two identical lines for PCB FOOTPRINT
7 @' R/ c' c4 r9 @941409 PSPICE PROBE BUG : Search accuracy wrong in new cursor window
8 i1 x' j+ |( n" o945242 SIG_INTEGRITY SIMULATION Unable to select "shapes" in find filter for 'show parasitic ' command
0 i H7 r' c' @6 e1 U. N8 T4 K946293 CONCEPT_HDL ARCHIVER Archiver hangs if there is a whitespace at the end of the path of cref.dat
6 c) m) M2 y* j0 i; P& r L946770 CONCEPT_HDL CORE 揤iew Design� function is missing in Windows Mode after reseting the menus.& d F. u# C4 q8 q* F3 d
950994 CAPTURE NETGROUPS Problem in expanding the netgroup in Auto Connect to Bus function& o; `% ?9 l* x( e/ P
953530 SIG_INTEGRITY GEOMETRY_EXTRACT Display Parasitics is displaying wrong results for EMS2D Field Solver compared to topology extraction using Probe.
( ], T* _# {# T# k% z- ]# a% ~953713 CONCEPT_HDL PAGE_MGMT Random page replacement/duplication in block& r; |: [4 k2 I1 e! S- Z
953917 CONCEPT_HDL ARCHIVER archcore should handle errors correctly" R1 s) l$ ~! X9 s* S- b
953971 ALLEGRO_EDITOR MANUFACT NC Drill files not generated correctly when using the option "搒eparate files for plated/nonplatedholes�
& J0 w6 N- V# b954400 CAPTURE NETGROUPS BUS members of NetGroup are getting converted to Scalars in Export-Import NetGroup.6 N1 L4 X/ J% p# [' J( t' T
954498 SCM B2F SCM crashes when importing physical& H, z0 Q7 R* A3 r
954623 ALLEGRO_EDITOR EDIT_ETCH Unable to complete connection with Add Connect - related to soldermask to cline check?% Y9 c- I( K4 R- V* U
954894 ALLEGRO_EDITOR MANUFACT Dimensions disappear when opening database in v16.5 from v16.3$ o/ T+ Y* m! X2 m2 O3 }- g
955029 CONCEPT_HDL CORE custom text font size not recognized in symbol view) s( V2 p: {" h& N; \+ k9 V/ T0 d+ a
955133 SIG_INTEGRITY FIELD_SOLVERS The Field solver creates the differential trace model which is reversed T(D1) and T(D2) of bottom side.7 Z! P9 [8 J. T1 y8 d4 v p
955290 CAPTURE DRC Description for UPD0014 missing in the Browse DRC markers window
1 t& p6 n- m# L V$ `/ M' b955299 ALLEGRO_EDITOR DRC_CONSTR drc text to smd pin does not work any more on this database in 16.3 S039) B8 k; l* J9 a# k1 S* F ]
955338 CONCEPT_HDL CHECKPLUS Need to change PART_NAME
/ C7 I/ t/ C% j# ~" C8 G v& ]' W' N6 P955447 SIG_EXPLORER OTHER Model path set in DE HDL Model Assignment not used by SigXP from CM in DE HDL5 Y8 [( D* t* z4 B4 j9 ]
955740 SIG_INTEGRITY GEOMETRY_EXTRACT Crosstalk with Timing Windows does not work correctly
3 v, q9 \3 H3 Y# d% y9 E- @955749 ALLEGRO_EDITOR MANUFACT show element Info shows symbol dimensions on incorrect subclass
5 e& L2 w N. u+ ]% K7 P" I3 q5 ~955912 ALLEGRO_EDITOR OTHER Shapes with voids that are exported to PDF have gray filled area over the void* N+ E; P% e) X. @6 _* C" ~
956129 CONCEPT_HDL INFRA DEHDL uprev hierachical design from 16.2 to 16.5 packaging failure.
. ^1 x" P) @' c- X% A& N# L- d956373 ALLEGRO_EDITOR NC drawing name doesn't display in the log file
$ ?% F5 e' w" E( }1 j! N% i956393 CAPTURE PROJECT_MANAGER "GENERAL" and "TYPE" tabs are missing from " roperties" dialogue box.2 {2 P0 x+ s- L2 M
956448 PSPICE MODELEDITOR Can not generate a DEHDL symbol from Model Editor, because no Capture license found
% H$ z5 v/ X, W9 s y! t) c/ L. l956456 CAPTURE NETLIST_OTHER OrTelesis netlist not transferring user properties defined under combined, c9 C1 ]% M7 F: K
956489 ALLEGRO_EDITOR MANUFACT dimensions lost when symbol with diemnsions attached to symbol origin placed on board# s) t9 |5 A: ~! m( _3 |% T# i
956603 CONCEPT_HDL OTHER Part Manager "has stopped working" after changing a component
1 p% b; F# s7 ]) Z0 U1 l- o956751 ALLEGRO_EDITOR ARTWORK Import Gerber command does not work correctly" y9 D7 w# e7 Z7 a5 ?) K" E( p
956847 PCB_LIBRARIAN METADATA PDV - Partdeveloper symbol to function linkage broken/changed in 16.59 \, @+ y7 d3 t% o* o9 p' f7 a
956987 CAPTURE OTHER Find from "Search toolbar" doesn't gives complete results5 C* S9 I7 [! x' b! i
956996 CONCEPT_HDL INFRA Correction to ERROR(SPCODD-7): Following Primitive instance causes CM to empty
G# K# E0 s& ~3 a" k4 S4 X957009 CAPTURE NETLIST_OTHER Problem getting database property in mentor PADS PCB netlist* h; L4 G" N1 U+ S# h
957137 APD DXF_IF DXF out command dose not work correctly.& \ o" n' o W" J1 {! k7 P
957167 APD GRAPHICS Highlighting for Static shape with display_nohilitefont environment variable.- j, _8 o1 L& g, ^6 y# L! s
957232 SIG_INTEGRITY OTHER Allegro crash during Model Assignment.0 {' E# s3 G3 Q( a& Y
957267 CONCEPT_HDL INFRA Packager Error after Import Design
) Q6 q( {2 q d0 c$ V! G957866 SIP_LAYOUT DATABASE Cavity outline is not getting deleted from symbol file
7 _2 t9 r( M/ A/ c: W958010 ALLEGRO_EDITOR REPORTS Wants the ability to extract "Batch" reports from Partition ".dpf" files.: z0 A$ r: S4 f6 a+ g2 y
958252 ALLEGRO_EDITOR TESTPREP Resequence testprep with the option - Delete probes too close crashes the design
- H1 W6 @) {% r! {! g5 M958253 ALLEGRO_EDITOR REPORTS Shape did not have thermal relief connected to pin but unrouted nets still shows zero.
: k K9 ^& p" l958433 ALLEGRO_EDITOR DRC_CONSTR False embedded component DRCs1 S8 b& [/ a5 I0 I
958753 ALLEGRO_EDITOR SHAPE Dynamic shape is getting corrupted in 16.5: z) I: z/ Y1 F) z& L7 v; h
959011 ALLEGRO_EDITOR OTHER copy problem of via and cline
, ^) i3 ?$ y$ H/ C+ ^959101 ALLEGRO_EDITOR EXTRACT Using extracta with excluding Thermal reliefs
' z+ j3 w9 _' f" D9 ]8 T959253 CONCEPT_HDL INFRA Design will not open
: p2 o8 b: e. U+ Y' d959299 APD MODULES Getting ERROR(SPMHDB-279) when trying to update modules placed on the Top side1 e5 T+ v) i& [9 k" q( {0 y. P
959884 CONCEPT_HDL INFRA Design Uprev/concept2cm crashes with Application Error/Out of Memory Error.8 f6 z! t# H8 ~# ^$ l
959909 ALLEGRO_EDITOR SCHEM_FTB Site level propflow.txt file is ignored property is transferred& n1 M* z; C$ T
960067 SIP_LAYOUT PLATING_BAR Creation of plating bar removes "NODRC_ETCH_OUTSIDE_KEEPIN" property from the clines.3 w E I' O& _' x
960126 SIG_EXPLORER EXTRACTTOP Allegro PCB SI license is used automatically at Topology Extraction of Allegro Physical Viewer.* ~/ v9 }- O& o$ q4 B
960143 SIG_INTEGRITY GEOMETRY_EXTRACT Running simulation in Bus sim happened crash while enable Coulpled Via model to S parameter
7 T4 f2 y- t# l# C5 J961349 CONCEPT_HDL HDLDIRECT Motorola designs have broken connectivity compared to 16.3
6 \; _3 G& z& `# y' m, e961816 ALLEGRO_EDITOR INTERFACES Normal Export > DXF fails and offsets the pins of the BGA symbol) M: R3 f: d) \% V8 ~
962519 SIP_LAYOUT WIREBOND Align option doesn't work for wb_tackpoint fingers! ^8 d5 \% e) q8 `, }$ S$ j
% f5 S3 S b! E0 y" i- d0 q5 ?* LDATE: 11-30-2011 HOTFIX VERSION: 012
5 {8 X5 @4 |1 v9 Q) [===================================================================================================================================0 ~, h' z+ B+ X
CCRID PRODUCT PRODUCTLEVEL2 TITLE( S& q+ |) k$ y+ [5 z- y2 W7 C- g) [
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959581 CAPTURE NETLIST_OTHER PCB Footprint is getting replaced by VALUE in OTHER netlist formats
, d% [$ q9 i) ?$ p4 a5 P1 Y# m) B) Z7 J: e4 l) _. E7 B5 c
DATE: 11-18-2011 HOTFIX VERSION: 011
6 W3 l$ e C/ F( O: ?' u: c===================================================================================================================================
3 _. g) g/ M: o, C0 GCCRID PRODUCT PRODUCTLEVEL2 TITLE& c. C& P7 t0 \9 b2 F: ~
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735439 PCB_LIBRARIAN CORE PDV Moving line-dot pinshapes by arrow keys breaks the pinshape- W1 U* f) O: G1 z
894815 CONCEPT_HDL COMP_BROWSER Why does genlibmetadata command give 'Aborted $PROG' Message?
) |5 V# F( h* U5 r3 S& t# ^7 P$ t V903073 ADW COMPONENT_BROWSE datasheetl_url directive should support a display string for URL
+ d5 Y/ W# G8 N2 i909919 CONCEPT_HDL OTHER Why is the PublishPDF UNIX command line looking for "true" script?$ X2 y6 Y! G) z" D( L+ a+ u: H
911561 CAPTURE CORRUPT_DESIGN Capture crashes on trying to save the design.
% c0 d1 v( n' j5 o5 N8 z+ w9 R919579 CAPTURE PRINT/PLOT/OUTPU Print mode be selected based on schematic mode
2 Z9 n3 T3 y5 U+ v921247 CONCEPT_HDL COMP_BROWSER genlibmetadata.bat file does not have err defined$ _4 C& I% t& j5 c9 X' O+ k3 _
925182 CAPTURE PROJECT_MANAGER ENH: Feature to run update cache on all the parts in design cache at once.
# _ Y! W( V5 S# p; W926858 CONCEPT_HDL CORE Usability- Modify Component dialog forces user to do 'Reset Filters' to see other ppt rows
% {0 u1 A5 c1 j$ H3 ^927657 CAPTURE NETGROUPS Enhancement: Placement of netgroup definitions under design cache list7 z% R) y6 n5 w; K2 u \+ J
934684 ALLEGRO_EDITOR MANUFACT The relation between the linear dimension and the symbol breaks.
) {6 m" L3 m. D+ T7 R3 T9 C; }( \935836 SCM SCHGEN ASA crashes when generating Flat Document Schematic i$ D7 m$ N# ?" `/ z: S
937165 SCM SCHGEN Can't generate Schematic, O; s) l1 u+ _0 L" {' {
937292 CAPTURE GENERAL Memory usage keeps on growing and finally gets exhausted while search4 K- i! t$ z3 _& Z! v% _
937322 CONCEPT_HDL CORE Master.tag file alters the sequence of the files and Genview fails
! \! T) O0 ~4 P" J7 a9 m939135 CONCEPT_HDL CORE Unable to uprev a 16.3 Design to 16.5 with DEHDL-L License% c' _2 {. C9 Z2 W) I. O" y5 U
940373 CAPTURE TCL_INTERFACE Enhancement: TCL command to add nets to Netgroup; W" v( [/ {$ d2 G
940547 TDA CORE ERROR(SPDWSD-69): highspeed cannot be checked in
- x$ {+ T. }& H0 a `940607 SIG_EXPLORER OTHER Inconsistancy in License usage for opening sigxp -orcad
) ~5 J u9 P$ ~* ]. S: y940790 F2B PACKAGERXL User doesn't want to display pin numbers after Export Physical 16.5.* t2 @# l2 w+ w! t
940944 SIG_EXPLORER OTHER Inconsistant license usage while opening Orcad PCB SI using allegro -sq -orcad and allegro -sq7 c1 G2 C! C z0 z7 ]. y% k8 `
941354 CAPTURE NETGROUPS Enhancement: Option to rename the unnamed NetGroups
; i" I7 Y3 L& Q! O8 O+ r% ~941455 ALLEGRO_EDITOR MANUFACT The Dimensioned mechanical symbol when placed in the board does not show all the dimensions.6 R0 T# b) P9 F, ^: j1 a5 `+ Q
941863 ALLEGRO_EDITOR EDIT_ETCH Different behavior of design in v16_3 & v16_5 when add connect is executed on a segment thru script0 |6 x( ~/ c3 B( ?, b& s6 m4 d
941881 CONCEPT_HDL COMP_BROWSER How can I suppress the dialog from universalbrowser -genlibindex?1 @ {% n" l h- z/ T5 [
942474 CAPTURE NETGROUPS NetGroup member type of last added member must be remembered by Capture! D2 n1 I: R8 } k- _; J6 K
942522 CAPTURE GEN_BOM Export in excel check mark doesn't invoked BOM in Excel$ D6 @" ?7 J! E: n6 }
942557 PCB_LIBRARIAN EXPORT_OTHER PDV Export to Capture crash: g6 J. R ]5 X! z
942569 ALLEGRO_EDITOR MANUFACT Dimension move and change text deletes leaderless balloon
* y8 [& O; _! t% K1 w8 _942573 ALLEGRO_EDITOR MANUFACT Balloon type parameter has no effect on leaderless balloon.! y' g" p U. x/ \
942613 CONCEPT_HDL CORE Genview supports only SCHEMATIC/SYMBOL/VERILOG/VHDL views as input type. .xcon not recongnised4 [0 \! T% N$ C2 P
943032 SCM OTHER ASA is not passing the correct reuse_module name to Allegro PCB layout.
" R" ?0 {5 Q, o943401 CAPTURE NETGROUPS Alphabetical ordering of NetGroups in Place NetGroup
+ j# I4 f/ ^, `5 ^944006 ALLEGRO_EDITOR EDIT_ETCH Vias added to shapes behave differently# Q8 A4 S1 I5 J7 H: U" R
944367 CONCEPT_HDL OTHER Too late to do Model Assingment in conceptHDL 16.5# {1 e1 ~* H! V1 @9 ^- I: M
944788 ALLEGRO_EDITOR GRAPHICS Oblong Pad shows unexpected lines
$ Q3 f0 [# b) ~$ F945221 CONSTRAINT_MGR RETAIN_CNS CM Conflict Resolution fails on more complex designs using ECSets and constraints% e5 P7 O: m8 b6 w2 n
946270 ALLEGRO_EDITOR PLACEMENT The Rotation Type was changed to "Absoute" if the "iangle 90" use at placementedit mode of spb16.56 u( Y+ b1 d$ l4 q* H9 X2 R
946350 F2B DESIGNVARI Variant Editor rename function removes all components% D! {: X5 @9 i B
946380 F2B DESIGNVARI Some VARIANTX properties are hard some soft - why?8 p- H( d* {' [% b- K$ O
946419 SIG_INTEGRITY SIMULATION Cannot select component on BoardModel for controller in bus setup form h( W+ ^! Q. ]. ~
946458 SCM SCHGEN Schematic generator adding an unnecessary page8 }. W, g7 V( Q6 z
947667 ALLEGRO_EDITOR PADS_IN Need support for PADS-POWERPCB-V9.3-BASIC
$ W' L% _) S, h; {# @947789 ALLEGRO_EDITOR MENTOR mbs2brd crashes during translation on the attached design.
: v" d' Y/ P* H/ U4 e948110 CONCEPT_HDL CONSTRAINT_MGR Concept HDL craches when opening SigXP from CM
5 S) g, h# a" y5 Q3 v950970 ALLEGRO_EDITOR MANUFACT Unable to generate artwork, dbdoctor fails to fix errors.3 g7 R2 G1 E4 N' Z5 W: Y; p4 O
951901 ALLEGRO_EDITOR EDIT_ETCH In 16.5 add connect to same net is shoved
* o# f) F; z/ O# B* o951919 ALLEGRO_EDITOR OTHER Exported package symbol soldermask and pastemask padstack locations not the same as original6 Y2 G2 b6 U2 @* k# I
951926 CONSTRAINT_MGR OTHER What is MaestroNotifyNotSetReport.txt file?
2 d( B9 J8 k& d# l9 s; F951939 F2B PACKAGERXL Uprev to 16.5 is changing refdes for some pages+ w! x* J. D& _, D
951983 CONCEPT_HDL INFRA Problems converting an Allegro design from 16.3 to 16.5
, u" K% d: H; g952057 SCM PACKAGER Export Physical does not works correctly from SCM* e2 A/ Q- q( s
952217 ALLEGRO_EDITOR GRAPHICS crash when opening 3d viewer in PCB Editor
9 k- E: i* l3 Z7 U952634 CONCEPT_HDL CHECKPLUS Checkplus logical rule fails on a design which packages fine in 16.5" ^$ B/ S' K( G$ r! P* d& G) l
953018 APD REPORTS Shape affects Package Report result.
' r; C0 f+ I8 b3 m953337 ALLEGRO_EDITOR OTHER Allow netname and padstack names to be visible for testpoint vias when viewed in Allegro PDF Publisher.! h) h9 C6 z3 p5 n& O
953827 ALLEGRO_EDITOR EDIT_ETCH Snake Breakout function crashed Allegro2 W; U% I6 x8 `1 F8 S' U* A( D
953918 GRE CORE GRE cannot route second and third row of pad in die symbol.* Q$ f1 T; M- H% @* `
954055 CONCEPT_HDL CREFER Crefer fails with UNC install path
4 n, ?, c' q" `! [3 j T% Q7 Y9 G954920 SIG_INTEGRITY CIRCUIT_BUILDER Each neighbor crosstalk simulation crashes or returns blank report) F% C* X* w/ \8 |
( R/ @3 }1 |2 IDATE: 11-7-2011 HOTFIX VERSION: 010
; ?& }6 I. H+ B' e1 e" N===================================================================================================================================6 r) n/ T( y, a! m; P4 n# p U5 {& b
CCRID PRODUCT PRODUCTLEVEL2 TITLE
6 G* x# L! l2 E N2 h- @6 u4 e; S===================================================================================================================================
4 p8 h) P; S9 Z; F$ F658866 ALLEGRO_EDITOR EDIT_ETCH enhancement option - so that Sliding a via inside a pad does not create a cline
) w$ ~% a/ S+ h. \928624 ALLEGRO_EDITOR GRAPHICS Layer visibility control for 3D Viewer
. Y& M6 }. F% Y5 R. p934991 SPECCTRA LICENSING Specctra_adv option is not working correctly for PA3100 plus PS3500 license in v16.5 tiering profile
3 ?+ Q- _( P# _- v! a- C9 q$ H938073 ALLEGRO_EDITOR PLOTTING Plot Page size A0 and A1 with problem
! ?" U: I* M& L. }7 X0 x8 M938128 ALLEGRO_EDITOR DRC_CONSTR DRC changes when do update DRC.! i2 a6 J. K5 @: w* {7 ~
938648 ALLEGRO_EDITOR GRAPHICS Enh - Requesting a way such that Package keepout appears transparent in 3D Viewer
9 Y. L# Y/ {; w J# X940518 SIP_LAYOUT SYMB_EDIT_APPMOD Swap pins command doesn't complete6 A3 O$ j$ L: j+ r; u
941426 CONCEPT_HDL COPY_PROJECT Copy Project fails - Updating opf view This can't happen!
C- L; V2 `5 V* l; I6 y941499 ALLEGRO_EDITOR DRAFTING BUG imit Tolerance isnot working for Dimensioning7 i, G9 l1 H" h1 L$ _ \
941814 CONCEPT_HDL CREFER CreferHDL crashes during ScheGen7 Z* \& ^, z* _6 `( v
942914 SIG_INTEGRITY OTHER ZAxis delay calculation7 a% q; q( C7 }2 T+ M' ^
943053 ALLEGRO_EDITOR SHAPE Modifying the Board Outline shape will cause the tool to crash* n. w" h1 Z% h6 \, V
945321 SIP_LAYOUT EXPORT_DATA generation of a xml file from cdnsip for shrunken die9 A' w3 h) ~1 ^' M
945350 ALLEGRO_EDITOR SHAPE iPick does not work on shape boundary edit.6 q. d& \1 ]( T) g% j. M5 b
945449 APD SKILL When they create a new menu entry with skill APD crashes with next menu selection.3 @9 W a8 L. B' ~
946390 ALLEGRO_EDITOR DRAFTING refresh_symbol crash when trying to refresh mech sym that has dimensions. a6 c0 B E5 L3 O6 f
946401 APD EXPORT_DATA stream out gdsII results in shorting of PWR/GND nets due to elongated etch8 a" b) x+ Q* `* {3 o6 E- B/ ]
946819 SIP_LAYOUT DEGASSING Shape degass command
% c: W0 E6 f2 Y) ]946869 ALLEGRO_EDITOR OTHER Allegro PDF arc representation needs cleaned up
7 V0 u2 i6 D1 x& ]2 Z+ X947230 ALLEGRO_EDITOR SKILL Skill execution crash Allegro 16.5 but work correctly with Allegro 16.3
; t/ R- s* ?( Q& T6 M947603 ALLEGRO_EDITOR OTHER Component Properties (Default or User Defined) not transferred to PDF file; g+ l. [2 d0 W! T3 u+ P
950995 SIG_INTEGRITY OTHER Netrev fatal error when importing logic. W1 ^, x; d" X$ b# b) U
951123 ALLEGRO_EDITOR INTERFACES IPC fails to output drill hole info in columns 33-37
; @' k4 A2 E! i& W6 w951557 CONCEPT_HDL CORE Cannot create the entity folder for old plumbing symbol
. @4 ?* h# Y) B9 ?" ~
8 c$ h- g9 M7 J3 \' BDATE: 10-26-2011 HOTFIX VERSION: 009
% p) Q& e2 o4 `) s' M n===================================================================================================================================
' J; p& H- L8 z% R) K BCCRID PRODUCT PRODUCTLEVEL2 TITLE# U" W. r: h6 [- F
===================================================================================================================================7 e* y/ ?! ]/ S0 c& W) y$ C
945788 CONCEPT_HDL CORE Some component properties on the parts are incorrectly changed after Import Sheet* ]- \* W' K- x, J; Q4 Z
945789 ADW LRM Some component instances are not updated by LRM even though cache ptf is updated from reference
2 [: O+ _3 k$ j. m; m s# ]' k/ E0 r2 z
DATE: 10-21-2011 HOTFIX VERSION: 008! C v! u5 L* T7 S
===================================================================================================================================4 C8 u$ J, q- M. B) b- f
CCRID PRODUCT PRODUCTLEVEL2 TITLE
+ ^+ }. J" G9 k" I: `===================================================================================================================================! m4 n) z) G5 g4 ^. V1 e6 @5 ]
906827 ALLEGRO_EDITOR DATABASE Logic > Parts logic does not work correctly.' S; F _: c+ P& l% O/ \2 f! N
923346 CONCEPT_HDL CORE Not able to move the reference designators inside hierarchal blocks after uprev to 16.5
; K2 Y4 X) u% ]! b926347 ADW COMPONENT_BROWSE Usability- Libflow Part check in comment should end up in Comments attribute for UCB/Designer to see it" z: j3 T$ z' _2 H: {% o3 W
929348 F2B BOM Warning 007: Invalid output file path name
% s7 R9 \! D3 |% O929777 CONCEPT_HDL OTHER Component Revision Manager gives internal error- b% z3 ]$ p' D9 i6 Q/ v
930783 CONCEPT_HDL CORE Painting with groups with default colors& u, T) X) |7 {% H' Q! Y
936748 ALLEGRO_EDITOR INTERACTIV "Unplace Component" menu inconsistent between General Edit and Placement Edit Mode.
8 ?6 L7 ?* z. F2 `( t6 X938143 ALLEGRO_EDITOR CREATE_SYM Why is this Extra Property 'ECSET_MAPPING_ERROR
/ l- T2 W j- r% ?. N0 Y+ p938281 SIP_RF OTHER export_chips creating bad data when symbol is split and contains V- V+ pins
# j& Y) `, @5 Z& n4 r! x938812 ALLEGRO_EDITOR SYMBOL Cannot create a BSM with this DRA, errors out but does not state a reason.
3 x! H% U2 z3 G+ t3 H& e5 M939075 CAPTURE TCL_INTERFACE Texts are getting garbled in command window
% i& O( y. E# A& p& |2 d( Z939193 F2B PACKAGERXL ERROR(SPCODD-439): Connectivity server is unable to load the design.
/ M- X/ p. E+ j939199 CONCEPT_HDL DOC "Retain electrical constraint on net" mismatch between schematic (YES) and design (NO)
. o& B' W, _7 J4 w( |- U939346 ALLEGRO_EDITOR SHAPE Shape disappears when updating with variable shape_rki_autoclip set.3 U/ K- F2 L- C" M9 \7 i7 p& J
939901 CONCEPT_HDL INFRA NET_SPACING_TYPE shows �?� on lower hierarchy level nets after Upreving to 16.5 version. Z: ], @( Y l% ?
939918 PSPICE PROBE Print > Preview for output file causes Pspice crash.5 R% a8 w2 \! d
940217 CONCEPT_HDL COMP_BROWSER UCB reports 'No Symbol found for the part'
' j0 I# s8 s' u# L; j# j940835 CONCEPT_HDL INFRA Desing package different after uprev to 16.5 where comp instance propeties are lost lost
" x+ M0 J3 i4 Y5 E- W# n1 W941125 ALLEGRO_EDITOR DATABASE Performance advisor doesn't skip non plated slot padstacks6 D% N9 h5 [% M4 ]
941876 SIG_INTEGRITY OTHER Illegal model name cause pxl fail in 16.3# s9 T; J; |4 I# M- v: g
942210 SCM OTHER Is the Project File argument is being correctly passed?
2 H( V& N/ [/ X6 Z6 \6 b- ]' f942274 CAPTURE PROJECT_MANAGER Crash on renaming a Design Cache part in Project Manage after doing replace cache
* ^: R7 K/ [) [* s3 F. c942839 ALLEGRO_EDITOR GRAPHICS Graphics Issue- Pads are not visible
! V+ _) F J5 f2 e943055 ALLEGRO_EDITOR SKILL axlDBCreatePropDictEntry causes application to crash
q% h9 K) ^; R: m4 F) t+ q
$ Z+ _" p. X2 a6 |: @6 W$ ?% A" bDATE: 10-21-2011 HOTFIX VERSION: 007
8 A; {7 `, Q; c! y( {# f( u2 z===================================================================================================================================
) X3 Q; H; }" b8 Z0 f. l0 aCCRID PRODUCT PRODUCTLEVEL2 TITLE
9 A# w% Y$ V7 K; ^. D* K. D===================================================================================================================================
) v1 g. A$ C: P$ n841096 APD WIREBOND Function required which to check wire not in die pad center.
& Q& Y/ n; r( S& Q2 V3 |0 o# H" F903263 CAPTURE SCHEMATIC_EDITOR ENH: Selecting parent netgroup must select the underlying netgroup bits.' r- T$ q2 [. @$ P% @4 v4 b. G
906692 ADW LRM LRM window is always in front when opening a project
& m+ o1 V, [6 l$ |' K/ b912942 APD WIREBOND constraint driven wire bonding
7 Q3 d+ Q5 Z7 p912951 CONCEPT_HDL CONSTRAINT_MGR Need to manage temporary files on Linux systems z1 `" c) w% C' q" F+ c7 r& D
915178 SIP_LAYOUT DIE_STACK_EDITOR Die Pad names changing when updating Die in a design, K& N4 y$ F; n6 B& O- t+ g" g1 f# W
917887 PCB_LIBRARIAN VERIFICATION Part should not be released if the alt_symbols has errors
. X8 d R+ Y2 W _$ G923315 SIG_INTEGRITY GEOMETRY_EXTRACT crosstalk simulation fails with TMP popup failure6 x( P. A. X1 j6 X5 W: V( V
927382 CONCEPT_HDL CHECKPLUS 'Verify Symbol' forces the use of 'Concept_HDL_Studio' license
/ p1 Y; z) T0 A927664 CONCEPT_HDL CONSTRAINT_MGR Internal Error disposeipsp( ?/ J z9 x4 X" E/ r0 [
930152 CAPTURE NETGROUPS Scalar net names when being connected to net group overlap when connections are made one by one0 n4 H9 O5 a+ k# L" g0 t
930180 CIS LINK_DATABASE_PA Visible property position on schematic get reset on "link database part" operation* {5 o- N/ {; E) g+ m- P" z; r
930188 CAPTURE DATABASE Capture 16.5 crashes in being re-invoked.
+ }$ N/ b& y7 T. Q9 S7 \: X930541 CAPTURE NETGROUPS NETGROUP element renaming doesn' renames the associated net ?# w) _. y+ o1 `" _/ G7 m
930866 PDN_ANALYSIS SETUP OrCAD PCB SI Session crashes when we open PDN Analysis with "OrCAD PCB SI" license.
/ D7 `) x4 ? }5 C5 p# z7 k2 f; p0 U930926 ALLEGRO_EDITOR GRAPHICS Via and Holes not visible eventhough set to Visible in Color form7 O( ~% T& w5 U
931274 ALLEGRO_EDITOR DRC_CONSTR Negative Plane Islands waived DRCs reappear after performing update DRC.
+ v" Q( v# g& `+ X" T932091 CONCEPT_HDL CORE Prop attached to SIG_NAME property
- t& w$ H" v, }1 A! L# u" w1 ?932255 ALLEGRO_EDITOR GRAPHICS Change in Zoom level makes arc segment to disappear# {- T% t5 k, J6 F7 y
932292 ADW LRM LRM crashes during Update operation on a customer design
9 o$ }! a- A6 z" o# X932639 SIG_INTEGRITY OTHER Add Connect command hangs for about 14 seconds and then returns.
7 W! t7 N- j b( J# s1 i0 n* Q x932704 APD DEGASSING Shape > Degass never finishes on large GND plane7 f( x& ^( D; b/ M8 p' ] j, f2 W5 Z: f
932871 APD GRAPHICS could not see cursor as infinite" n8 D9 @3 V/ b2 P @9 b
932882 CAPTURE SCHEMATIC_EDITOR Capture crash with FIND command - ISR059 c- V8 _8 ~; i1 d
932969 CONCEPT_HDL CORE ConceptHDL crashes when you save the design in 165 > hotfix #05
1 I4 j J# {5 k933024 CAPTURE NETGROUPS Naming restrictions for NetGroup members/ o+ l8 P5 U* N% P' D; G
933145 F2B PACKAGERXL Add Subdesign list is truncated in Force SubDesign Design Name pulldown
& ^4 N& w6 U3 s+ T7 s* x5 G933214 APD ARTWORK Film area report is larger when fillets are removed
! n$ w2 k2 m8 w2 e8 L933356 CONCEPT_HDL CORE Net prop display size become 0 if it was attached to SIG_NAME prop.
- e" h8 ]- `; S5 a B933532 ALLEGRO_EDITOR COLOR Bad color assign and initialisation during creation of new subclass
! Q2 G* }: g7 a, U) l) Y933549 ALLEGRO_EDITOR OTHER Chart text missing in export PDF file.
5 ?2 U) q1 {3 H {5 R, N* O, j; }934008 ALLEGRO_EDITOR REFRESH refresh symbol updates symbol text to some unexpected values; k& S1 y5 r3 j
934031 ALLEGRO_EDITOR DRC_CONSTR Bug : Update DRC removes Waived status for some DRCs! z2 \# N0 X& u$ h' f- a
934087 CONCEPT_HDL CORE Opening DEHDL and Model Assignment before design loads causes crash3 N( T6 X7 \+ y4 _' g
934396 CAPTURE SCHEMATIC_EDITOR Find operation is not searching power symbols with + or - signs.
3 u' u1 C4 P# z934533 F2B DESIGNVARI The Variant Editor errors are not written to the variants.lst file
5 `& o: z9 m c. H# g# G# {, L* J934811 SIP_LAYOUT UI_FORMS CDNSIP should not hang if contraction value in z-copy command is out-of-bound
3 p9 o6 E; I c- { l934909 SCM UI Require support for running script on loading a design in SCM
: V' L2 i I# _% L935632 CAPTURE SCHEMATIC_EDITOR SHIFT+Mouse wheel scroll(horizontal) of page is not working in Auto Wire Mode.
: Q4 |: f9 @- a" K3 u0 } c935794 ALLEGRO_EDITOR SHAPE BUG:Shape not filled in 16.5 but it does in 16.3) w# t: W; C6 b! t
935988 ALLEGRO_EDITOR INTERFACES When attempting to downrev this 16.5 design to 16.3 the tool will crash4 q) O$ n; m# G$ d
936056 ALLEGRO_EDITOR DRC_CONSTR place_manual crash while moving mirrrored symbol2 J& {% r# @/ A
936098 ALLEGRO_EDITOR SKILL axlDBCreateCloseShape does not work correctly.. N- ~6 f# f1 |
936212 ALLEGRO_EDITOR INTERFACES DXF not created if Blocks created for Symbol and padstack- t" ?. C2 M5 t. O/ L
936797 CONCEPT_HDL COPY_PROJECT Copy Project crash
( B1 e! H9 L' [+ i0 H! Y# `: G+ ]' H936808 ALLEGRO_EDITOR DATABASE Allegro crash replace mechanical symbol
! h5 [$ x$ _7 S" g) p936853 CONCEPT_HDL CONSTRAINT_MGR DEHDL crashes when trying to extract net from CM
& @: a! x* ]- A937087 CIS DESIGN_VARIANT Upreved design becomes very slow in Variant view mode. DELEET THE DESIGN AFTER RESOLVING THE ISSUE
1 O" q0 G9 a& R& d6 @7 Z! L937173 CAPTURE OTHER Wrong license information "UNLICENSED" in Capture >> Help >> About2 ^1 m, z+ j2 F5 b
937290 APD PLATING_BAR Plating Bar checks does not recognize connection made through etchback through shape.% w% {) d, ^; \
937411 ALLEGRO_EDITOR DATABASE downrev_library reading from one directory and writing to another hangs the command.
* A9 N6 m0 U- V938235 SIP_LAYOUT STREAM_IF Die Orientation is not correct after importing a stream file.2 a# t9 ~1 z0 W8 v' |
938273 ALLEGRO_EDITOR OTHER PDF export is is not opening viewer with ads_sdlog variable set7 O; z3 @: U3 k# b8 J, s
' Z" X3 Y: O0 o7 ]DATE: 09-16-2011 HOTFIX VERSION: 006
% {! p+ c% P) |) K0 g2 ]* [( W# p===================================================================================================================================
( ~2 i% T: O6 m1 ^* kCCRID PRODUCT PRODUCTLEVEL2 TITLE
6 ~# A# X# P% |; w& f===================================================================================================================================
9 o( @: l4 z6 O820131 CONCEPT_HDL OTHER Moving symbols to other page will make Allegro components unplaced because logical_path changed.& `/ H* Q3 B+ u( o/ z
863860 CONSTRAINT_MGR SCHEM_FTB CM should display or Local Interface and Global nets to help defining low level constraints9 p& d- u" v" F6 G
919822 TDA CORE Cannot configure LDAP to only list the login name
' ?( r$ y. f( ?1 p922907 ADW TDA 搇ast_callout_file� directive in the BOM section is empty causes tda for show Access Denied error
# P: i H1 [8 r5 [' I0 i924322 ADW COMPONENT_BROWSE Random - No instance properties are added on Add To Design (RMB or double click) from Search Results
4 {: x% b* `. `! w3 N6 k. `924448 F2B DESIGNVARI Design does not complete variant annotation
% m( G8 h$ S4 z+ [+ }$ u- B4 `; ^925584 CONSTRAINT_MGR SCHEM_FTB 16.3 upreved Design passes the SLOT/Function Properties to PCB' g) q: @9 z8 e# L( T; t
927102 ALLEGRO_EDITOR OTHER Question of Conductor Detailed Length Report, Y; U3 M, ~: \, Z: x
927104 F2B DESIGNVARI Tools > Annotate variants crashes when there are ASCII characters in the property values
! Q/ h, _" Q& d9 Y; S. p. b) A' P927142 F2B DESIGNVARI Incorrect pop up asking while executing variant editor from the command line
- H `% y4 v' N i/ j927166 CAPTURE NETLIST_ALLEGRO ENH: Feature like NET_SHORT in Capture Allegro flow which allows user to short 2 or more power nets) \% G* j4 Z. m- b8 f
927410 ALLEGRO_EDITOR DATABASE ERROR(SPMHUT-144): Illegal arc specification error when Run DBDoctor v3 d6 @& ^; G& b& |0 L
927475 CONCEPT_HDL CORE About forcereset command of nconcepthdl
! c1 t, Y, r& N0 \6 n927498 CONCEPT_HDL CORE Pin_Name starting with minus causes incorrect behavior for $PN display
1 n4 {; _& e0 i, {7 Q' p- ^927608 ALLEGRO_EDITOR PADS_IN Import PADs fails with error message: Failed to close the Allegro database
" T: r# _3 @% k, M927637 SCM CONSTRAINT_MGR ASA crashes on change root and also performance is too slow.6 \ D. _! m$ }
928429 SIG_INTEGRITY OTHER Request - Package Wizard to work in PCB SI.
1 g' V/ \1 ?! d+ O. `6 J# F928483 ALLEGRO_EDITOR DRC_CONSTR Running Update DRC removes Via List DRC Error when via is actually not in the list5 z5 J1 B8 f7 Y# L% e
928738 PSPICE PROBE Y-axis grid settings for multiple plots
. }( d! l" U2 _5 [5 d @928748 PSPICE PROBE Cursor width settings not saved: D# w/ I j, p& Z) ~( l# H
928779 CONCEPT_HDL CORE Error (1053) occurs on a copied part in SPB165 release
% ^7 G. R8 \; C4 y1 r; r+ S928838 CONCEPT_HDL CONSTRAINT_MGR ECSets not migrated in 16.5
8 F8 H9 Y: i3 w, ^& Q" d928885 SIG_EXPLORER EXTRACTTOP PCB SI crashes when extracting a net from Probe
- R- P( ~$ X# Y; k8 r929284 CONCEPT_HDL ARCHIVER archive does not create a zip file
& C( f( u1 f( t929542 SIP_LAYOUT DIE_ABSTRACT_IF net issue of multiple ports of co-design die in SiP2 c9 ?$ }) q; r8 L: H# b/ c5 D
929656 ALLEGRO_EDITOR PADS_IN PADS translation fails with Microsoft Visual C++ Runtime Library error, u; d1 z8 L" f8 V$ c
930063 ALLEGRO_EDITOR TESTPREP Test prep crash Allego when it can not create pin escape' ?8 n4 Z( S6 j/ c( f" |, V
930217 CAPTURE NETGROUPS Net aliases doen't gets assigend to bus bits if bus name is checked in NETGROUP.. v* y, A( K$ l* s
930355 SIP_LAYOUT WIREBOND about "wirebond add nonstandard" command
+ z8 {! Q5 Q$ X9 V7 l$ t( ^3 u930607 APD OTHER Layer mapping information is reomved from Layer conversion file upon exporting DXF from board file.
F) O5 E( L+ t# E0 X930646 ALLEGRO_EDITOR DRAFTING Bug - Adding Linear Dimenstion for ISO standard add the Angle information as well# R9 m! n, t0 i2 r/ C4 ]6 K0 h# {
930894 CAPTURE TCL_INTERFACE PDF export doesn't creates property file if some symbols are used in page name/folder name, B9 w8 L* S j: L+ Y& N7 ]
930944 ALLEGRO_EDITOR OTHER Setting variable 'appmode' equal to 'none' is not changing the Application Mode when reinvoked
2 R. q/ U) K) u: V4 r0 a% O930978 ALLEGRO_EDITOR SCHEM_FTB 3rd party netin error - Pin is connected to net <netname> not reconnected no longer happens- A' g0 R: b# B5 _/ j
931248 ALLEGRO_EDITOR DRC_CONSTR Match Group was removed if member nets became xnets.
" F5 T# n3 M- C7 b- c931278 CONCEPT_HDL INFRA $PN gets copied when upreving design from 16.2 to 16.5 version' F$ e) ]( f" w D; \
931349 CONCEPT_HDL COMP_BROWSER DEHDL craches and corrupts connectivity file when using Modify command extensivly.$ j3 m9 K, m. @' [6 w8 g7 k
! q5 O+ E: f( r. ~- Q
DATE: 08-31-2011 HOTFIX VERSION: 005
3 ^7 r- J& U, Z9 M: q& ^===================================================================================================================================" J" T5 p) ?9 e4 ]/ H* x/ _; H Y
CCRID PRODUCT PRODUCTLEVEL2 TITLE
2 Y) t7 h9 L0 @8 k===================================================================================================================================
: G) ~8 L w; `825848 ALLEGRO_EDITOR SHAPE Shape not filled when edges from 2 RKO shapes touch around mouting hole. z! f3 C$ B. d& P
837723 CAPTURE PROPERTY_EDITOR Occurrences of external design not related to current root should not show- v, `8 }, }. b
891079 CONCEPT_HDL CORE DEHDL crashes with large number of commands in Winodws mode( \4 u4 }; O5 p: R; f: k1 U
910908 SIG_EXPLORER OTHER Cannot open top if Tx AMI dll name contain more than 2 dot.# P3 M& i$ z4 \& D
914036 CAPTURE LIBRARY ENH: Option to delete a corrupted part from a library and leaving other parts intact in the library.$ {! z, c% _: y+ o
914679 ALLEGRO_EDITOR INTERACTIV Custom toolbars are not retained when switching between brd to dra and back to brd file using the File > Recent Designs+ N Q# D p' S6 X6 C6 t* K2 n
914870 MODEL_INTEGRIT OTHER mergedml fails to merger 2 DML files from the model integrity
' r' }, N3 m7 _3 S' n3 D0 R915645 ALLEGRO_EDITOR MANUFACT Allow the user to place the cross-section chart at a desired location
" Q$ N7 b5 L; @9 B" w2 v915653 ALLEGRO_EDITOR INTERACTIV unable to delete non-etch shape
6 \6 m/ A9 _1 @, P4 c915711 ALLEGRO_EDITOR MANUFACT dimensioning tolerancing by limit not working
4 b- V) U+ S2 F916321 CAPTURE GEN_BOM letter limitation in include file/ w6 y* X9 a% v; B4 _
916907 CAPTURE SCHEMATICS 揂uto Connect to Bus� should place the wire through non-connectivity objects
/ m) ^+ o4 B n( q920327 CONSTRAINT_MGR ANALYSIS The TotalEtchLength predicate in Constraint Manager does not work for a netclass with a bus.1 B3 e$ q) h# r2 p
920753 ALLEGRO_EDITOR GRAPHICS If I confirm to padshape with zoom-in after install the s002 It was changed to wrong shape., R9 B6 d& q/ |( T* x
921097 ALLEGRO_EDITOR GRAPHICS Padstack seen partail filled when Zoomed in even "static_shapes_fill_solid" is set
0 O1 Q% l- Q! N8 ]* m r* `! S921226 ALLEGRO_EDITOR DRAFTING Unable to select Package Geometry class when dimensioning in the symbol editor.
8 T9 C1 a( ]( Q$ X# _921623 ALLEGRO_EDITOR GRAPHICS Bug : Symbol not visible when zoomed in 16.5 S0028 t" C7 q7 W& @) |6 r
921891 ALLEGRO_EDITOR DRAFTING dimensions are lost after downrev(ing) a SPB 16.5 design with associative dimensions
P% G& g8 g4 ]+ Y* D- }" [921937 ALLEGRO_EDITOR COLOR Padstacks with shape symbol are not showing correctly+ r+ [$ z6 p, j. ]
922066 CONSTRAINT_MGR ANALYSIS Custom measurement Actual not being cleared when layout changes.
4 z8 s/ U' a) G, o+ \3 E0 W922117 PSPICE PROBE Label colors are not correct in Probe/ f0 u& w8 S: [$ i6 k. K' S
922519 ALLEGRO_EDITOR SKILL add_bviaarray command fails for some clines but not all
y% h0 `. O2 N5 s3 u923224 ALLEGRO_EDITOR GRAPHICS Thermal flash Display problem in Allegro v16.5 Hotfix S002; f) n, o) u% q" G: n* _
923286 CAPTURE DRC DRC markers not reported for undefined RefDes
0 K6 W2 U- e, C0 u U7 @5 K2 \923362 ALLEGRO_EDITOR PLOTTING Print to Postscript file not correct in 16.5
. {+ L h4 b% p( `1 b923416 ALLEGRO_EDITOR PAD_EDITOR Pad Designer crash on clicking on the Arrow before Soldermask_top, ?0 B+ {2 x ^" _# K3 e$ ]1 q- k
923507 CONCEPT_HDL CONCEPT-PCBDW The function of Import Design in the SPB16.5 Design Entry HDL (for data of ADW15.5_S23 + SPB16.3): A1 M& o) x$ e( _" H9 a% q5 L9 |
923910 CIS PART_MANAGER Copy & Paste operation from Part Manager copies properties only to first section of the part.! i$ g2 c" g3 Q u" c B( \* |
923913 CAPTURE PROJECT_MANAGER Capture runs slow on attached design0 h: z- T5 Q% k# p C8 W4 }& o( x
923937 CONCEPT_HDL CORE Back annotation time significantly increased with the metadata generation on
4 U R' Y/ `/ I; y# M2 |$ ?# _923949 ALLEGRO_EDITOR INTERFACES Incremental DXF_IN gives 'Invalid subclass' error
9 H% e2 M( q, t7 ^8 k' {924458 SCM OTHER Project > Export > Schematics crashes
2 s2 j/ e$ P, Z8 x' a7 A924621 ALLEGRO_EDITOR SHAPE Dynamic shapes are disappearing upon updating them to smooth.
5 U4 c+ y: \$ G9 W+ F9 |925193 SIG_INTEGRITY FIELD_SOLVERS Diffential Impedance (DiffZ0) values computed in the layer stack-up is incorrect2 K1 k7 J/ }1 `# B# B. ?
925195 ALLEGRO_EDITOR DRC_CONSTR Incorrect pin to shape DRC error
: x9 [0 z- A9 p% L, y925338 CONCEPT_HDL CORE This application has requested the Runtime to terminate it in an unusual way" P4 K7 i3 F, C4 U. f. L
925435 CAPTURE TCL_INTERFACE Capture crashes if 揝ave design as UPPERCASE� option is disabled.! E# u( ~1 Y8 g7 X8 b- o! g o' y
925530 SIG_INTEGRITY OTHER Why the single line impedance value for Top and Bottom layers are different for this design?
' x4 S% ?; O- H3 n925864 ALLEGRO_EDITOR DRAFTING Ability to add dimensioning to different CLASS/SUBCLASS" r! Q' z' ~+ L
925976 ALLEGRO_EDITOR MENTOR mbs2brd fails to import data
# h5 J+ J1 s1 |: C; U* w$ Z* c6 j926409 SIP_LAYOUT DRAFTING Exporting a 16.5 design to 16.3 will cause the leader/dimesion lines to be removed.
) l5 `6 z3 K! x# @: b6 {: o: k926443 CONCEPT_HDL CONSTRAINT_MGR In new 16.3 "035" ISR Concept2cm will crash with error.
% X; k( G* k( w( `" p1 |% B926503 CAPTURE GENERAL Memory leak Capture/Pspice
4 f7 X9 _: ~2 M9 U3 J1 n926553 CONCEPT_HDL CONSTRAINT_MGR CMGR ERROR There is no net in the Cset that has pins matching those in net 1 in the Xnet
$ E, p. C; a: q! P2 b# K2 b$ _926691 ALLEGRO_EDITOR OTHER Crash while Importing Technology File in CM, with Overwrite Constraints.
- D+ f9 \5 n$ u( B) d H, V" O926887 CONSTRAINT_MGR CONCEPT_HDL Pin pairs lost after Export Physical& y3 d5 A1 C7 i- D
927159 CONCEPT_HDL CONSTRAINT_MGR Export Physical fails due to errors in ConCM.log when SIGNAL_MODEL injected property is ''
) J/ g9 Q/ j2 B' H4 L' Q' @. t/ \5 _: q1 T6 n0 [3 J" `
DATE: 08-19-2011 HOTFIX VERSION: 004, ^: x9 y: L( _" Z! [1 y
===================================================================================================================================
B, X& P8 v. s7 Y/ a/ \CCRID PRODUCT PRODUCTLEVEL2 TITLE
$ w7 D* R3 K2 \" ?+ E4 e===================================================================================================================================/ ]( w" E* _' D: W: Y5 P
785417 CONCEPT_HDL COPY_PROJECT copyprojectui crashes with a Windows runtime error
; y% D9 G6 D! j( P9 { Z- D851044 CAPTURE GEN_BOM "Export BOM report to Excel" does not appear in the Standard Bill of Material Window.% A% i8 B4 Z; }" p$ R
868216 PSPICE MODELEDITOR Encryption of subckt names, internal nodes, comments& E1 l1 ]) g- x; j- r5 H
870247 PSPICE SIMULATOR Encrypt a model and simulate it, info about inside nodes being dumped in the probe file& L Q7 X$ `; j9 P
877091 CAPTURE SCHEMATICS Save JPEG, GIF, PNG and other image formats in the database in its compressed form# S- D5 H, d9 Q2 `+ P6 p" Y$ B7 F
894059 CAPTURE OTHER Enhancement: Adding column in edit>browse>parts window+ h/ Q. Q/ M' e7 Q/ O% ~5 D8 d
895902 RF_PCB OTHER Alphanumerical allegro pin numbers are unusable in ADS 2009 Update 1
" S% s6 b! |) X% }895919 RF_PCB OTHER Round trip Allegro to ADS to Allegro requirement
, ?% d) s0 K! |. f903102 ALLEGRO_EDITOR OTHER Zcopy shape command for cline seems not to work correctly.
# x" `1 C8 W0 E5 w, g5 n905562 SIG_INTEGRITY SIGWAVE Noise margin seems not to be measured correctly with Eye Measure function.; [& v" q" U3 ]5 A$ a `
909469 SCM TABLE ASA crashes when opening project B: l1 D1 {. e+ h3 ~' r2 @
909595 APD LOGIC Inconsistency between export die text out and show element after pin swap7 q0 x# j+ ~" y: J, E
911123 CONCEPT_HDL CORE 16.2 Design uprev to 16.5 fails with ERROR SPCOCD-152
6 \ a7 x4 ]+ O+ z911569 CAPTURE EE_INTERSHEET_RE Q: Why is capture assigning incorrect Irefs in attacehd design ?
6 p4 p4 N( A2 k/ H- j! S915657 ALLEGRO_EDITOR OTHER Allegro PDF Publisher Mirror capability) w) h/ v9 d! N( N! @& R
915755 CONCEPT_HDL CONSTRAINT_MGR Cannot view net in SigXP! [0 l. G- x _. R
916062 CAPTURE GENERAL Auto Wire Crashes Capture
( x! o% W7 {2 `( L. p916820 F2B OTHER RF create netlist with problem
X) p! Y; g W( b9 p0 U917967 ALLEGRO_EDITOR REFRESH Update symbol resets refdes location for bottom side components only.5 ]* _5 F$ T3 V. W. s2 S* n
919343 ALLEGRO_EDITOR PLACEMENT Place Manual is crashing the board file" o6 g( |8 z+ z4 u% `9 u
919481 CONCEPT_HDL CHECKPLUS CheckPlus isGlobal function is not working+ w8 M: P5 i7 b' \1 J9 e/ `
919510 CONCEPT_HDL PAGE_MGMT takes 10 min to insert page in DE HDL, K8 a# [+ V( v' ^
919976 APD DATABASE Update Padstack to design crashed APD.
: y) D- \3 i, z X9 g) ~920418 SIP_LAYOUT OTHER SiP enhancement to Auto Assign Pin Use to add ability to change the pin use definition# Z3 O3 J3 u# C
920420 SIP_LAYOUT LOGIC SiP enhancement to Logic Auto Assign Net to display a dialouge Auto Pin Use assignment should be run4 o1 R& ^$ {% F$ H
920712 ALLEGRO_EDITOR ARTWORK Program has encountered a problem ... error when creating artwork
. H) t- C2 ~0 W7 M6 c) i6 m920763 ALLEGRO_EDITOR ARTWORK Soldermask gerber missing thru-hole pins5 f6 k) y9 J- ]9 y5 H
920976 ALLEGRO_EDITOR GRAPHICS Question regarding the difference in the behavior of 3D Viewer w.r.t. height_min4 N& s9 x4 V1 \ R% l5 C# ~
920993 ALLEGRO_EDITOR DRC_CONSTR Minimum Metal Spacing Error is detected on Same Net/ h& Z" O1 R: b0 t
921727 ALLEGRO_EDITOR DRC_CONSTR Pad Boundary causing P/P drc to adjacent symbol.
6 G$ ^, c0 C# ^# V* q9 _& j922579 CONCEPT_HDL CORE Xcon file gets corrupted upon Save of Hierarchical design with Global nets tied to interface nets
) G$ `% f/ ?- {4 ?- |922592 CONCEPT_HDL CORE DE-HDL does not report illegal connection when Global Net tied to interface net using an Port symbol and named
' t- N4 ]+ Y% B: @1 p" |& W5 |922758 ALLEGRO_EDITOR DATABASE Allegro crashes while placing second mechanical symbol with route keepin
* l3 E6 z7 r J: a922839 ALLEGRO_EDITOR DFA The DFA drc display is unstable.
6 m+ T7 Y, r' _( H$ t923293 ALLEGRO_EDITOR INTERFACES File> Export> IDX is failing for this design while creating an empty error log.5 R0 @* E) Y1 A$ i% ?! z$ S4 X7 v
924772 ADW PCBCACHE Import Sheet is not bringing in Parts used in the source pages into target cache ptf$ L! |$ m i/ d' A
* K6 ^# w2 S: O: ^( y* _# CDATE: 08-4-2011 HOTFIX VERSION: 003
7 X" D B' g5 @3 I7 h, X===================================================================================================================================
) G" l" j- O" K5 E; E1 }$ VCCRID PRODUCT PRODUCTLEVEL2 TITLE
4 ]/ X- h* D5 T/ q0 o* c===================================================================================================================================, ]" u- ^) w9 X4 H" w+ Y; w
787414 CAPTURE PROPERTY_EDITOR Part value can抰 be moved on schematic if a part has been copied to a new design and not saved yet.
5 n5 T7 u5 Y4 v$ ~# ~9 q- I903898 PCB_LIBRARIAN GRAPHICAL_EDITOR PDV move symbol graphics and Undo causes corruption in graphics
_* @! |) ]2 }1 R H904287 ALLEGRO_EDITOR ARTWORK some cline with arc is missed, when creating artwork.
$ D" g9 Z% b3 \# l- j904418 CHANNEL_ANALYS SIMULATION channel analysis sim does not give valid result
) |, W; P) f4 P* c905777 SIG_INTEGRITY SIMULATION User gets popup message that halts an analysis until it is acknowledged
9 k5 ~/ _( B9 E& ]0 r7 [# L& H( _906139 SIG_INTEGRITY OTHER Bus sim result were cleared at the next run even if no preference changed.
2 b( [7 M, j: i: z9 x/ s5 j908680 SIG_INTEGRITY OTHER Extra prop delay due to resistance2 R' [+ j# S6 p% ~- s
909583 ALLEGRO_EDITOR SKILL axlPolyOperation AND operation is not working correctly.+ C6 X& r' r5 G, ~6 s/ X/ h
910315 ADW LRM Import Design with ADW causes partmgr and pxl errors
5 ~$ R4 v: p- e910689 CONCEPT_HDL CONSTRAINT_MGR NO_SWAP_COMP warning after uprev to 16.55 Z2 t: W! z; [
911684 CONCEPT_HDL CONSTRAINT_MGR Attribute Definitions are incompatible for attribute 'HEADER'. when attempting to place in 16.5
# X& J: g1 o5 W, g912343 APD OTHER APD crash on trying to modify the padstack' M' k) F3 V8 J- I, l8 e
912384 PCB_LIBRARIAN CORE PDV Symbol Editor often freezes when moving groups objects by arrow keys" S8 K& _# v7 o$ S7 Y8 f: |# s
912853 APD OTHER Fillets lost when open in 16.3.
$ p) w1 Z M7 s( z- y+ p, u913586 ALLEGRO_EDITOR ARTWORK Cannot create the drill figures in this design.% U1 T! E) A2 R# m7 `+ n( I2 r1 ^
914009 ALLEGRO_EDITOR DRC_CONSTR Diff impedance worksheet showing almost zero impedance for differential pair in attached testcase.
9 o) o6 j. b/ D2 ]% J# L0 H& d914110 CONCEPT_HDL OTHER DEHDL 16.5 Uprev overides property values on hierachical blocks
, V8 O4 c Z: j( ]0 b. Z914264 F2B OTHER Cross Probing from DEHDL for global nets present inside block doesn抰 highlight in PCB Editor.
( P* Q# @% y8 M& @' ?914309 CONCEPT_HDL CORE 16.5 DEHDL crash on saving the user design5 q* [% B& k; o$ _
914558 ALLEGRO_EDITOR ARTWORK Gerber6x00 output creates unpainted niche in a shape* w6 m! l( L$ |& i
914633 ALLEGRO_EDITOR ARTWORK Artwork failing in v16.5 while the same design when downrev'd to 16.3 is working fine.- [- E" U$ S; Q$ A
914634 ALLEGRO_EDITOR SKILL IsThrough flag for a padstack is reset1 m! m) n2 k: P8 R
914746 ALLEGRO_EDITOR DRC_CONSTR DRC Update repeats takes longer on each successive pass.) x4 D/ g$ n2 v5 Z/ O9 x
914962 ALLEGRO_EDITOR SHAPE Corruption with Shape filling, L9 E' X3 P# ~8 {2 n9 o
915583 CONCEPT_HDL CORE performance issues in 16.5 compared to 16.3* N; Z5 j M* }4 Y" Y' Q V& N
915630 PCB_LIBRARIAN OTHER Error when running SI Model Interface Comparison using IBIS models9 ^& x0 j! l( {3 G. q5 j1 |, r
915742 CONCEPT_HDL HDLDIRECT I get a newgenasym error and crash when trying to save the symbol, L# q4 a8 o7 y. j
916154 SCM NETLISTER scm crashes when exporting physical database to allegro: P4 {" n, F/ a: t& e9 @9 ^9 E
916448 CAPTURE NETLIST_LAYOUT Capture 16.5 Layout netlist contains errors
8 n R/ n+ x. a1 D. Y- X916462 ALLEGRO_EDITOR DATABASE Edit>Split_plane>create hangs Allgro PCB Editor
@1 N2 l" y* s: L$ E9 P* P! h4 l916469 ALLEGRO_EDITOR REPORTS One Unrouted pin does not show in Unconnected Pins Report! ^' }6 {3 [( C P5 E
916495 ALLEGRO_EDITOR INTERACTIV Pick selects components from invisible (Off ) layer
. T P, ~- }. o916889 CAPTURE NETGROUPS How to change unnamed net group name?
+ | X8 s/ s- O917002 ALLEGRO_EDITOR OTHER Allegro PDF Publisher creates extra circles not available on film
% v: A: a$ v3 e- U+ \917434 APD OTHER Stream out GDSII has more pads in output data.6 A0 b Q5 _! V5 y
917739 CONCEPT_HDL INFRA Global Net tied to port is getting split into 2 nets in 16.5, in 16.3 it is treated as a single net
' V) G6 H, N' e2 g0 ]918187 CONSTRAINT_MGR OTHER Missing acGetTotalEtchLength predicate.
. z+ v$ p# ^7 Q1 i) g4 B918576 CAPTURE DRC Incorrect DRC is reported for visible power pins which are connected to power symbol
7 M) ]6 E9 P9 y* m8 U6 `% F+ h
4 }; h5 ^/ Z5 X$ k7 h: IDATE: 07-24-2011 HOTFIX VERSION: 002+ b' v+ L J7 r4 W) _ @
===================================================================================================================================$ E. W4 m4 G/ B$ I+ @
CCRID PRODUCT PRODUCTLEVEL2 TITLE
, c( Z: F$ n5 w4 m===================================================================================================================================
8 e5 O' r* [8 L q4 H* t5 ~527444 ALLEGRO_EDITOR EDIT_ETCH Slide command needs to be enhanced for same net spacings
8 u K# e- o( b! ~! _1 z& i# K3 `583257 ALLEGRO_EDITOR EDIT_ETCH Add Connect and slide command needs to be enhanced for same net spacings.
: P1 `- F( @! J592956 ALLEGRO_EDITOR EDIT_ETCH Same net traces will not push and/or shove each other.5 s% i* ]2 T' C: n# y
745285 ALLEGRO_EDITOR EDIT_ETCH Requesting a true "shove" in Route > Slide for Same net routing.
/ _4 \9 w3 Z! m" E, a# r773503 CAPTURE OTHER Doing "Mirror Horizontally" creates extra un-connects or extra junction dots in Capture V16.3.3 C3 }" d: I& k( V0 n# `
774270 F2B PACKAGERXL Require to ignore space in Pattern setting to prevent duplicated Refdes.% Q- S6 `* p" Q% I( ?
799984 ALLEGRO_EDITOR INTERACTIV Enhance the Fix command to select just cline segs/ b; B, b3 S+ c, |7 f
809008 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".$ S. `/ Z9 |7 Q
810058 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".
) h9 E8 l( ?: w: g& a0 Z# f0 j821133 ALLEGRO_EDITOR MANUFACT Output artwork for pad data that are suppressed unconnected pads with Gerber 6x00 format5 w1 ?1 R1 v1 ?* z1 E
831710 CAPTURE SCHEMATIC_EDITOR Capture adds extra junctions to design by itself
+ V- |: N9 | [842410 ALLEGRO_EDITOR EDIT_ETCH Ability to slide with "Shove" for "Same Net" segments/vias.- C6 ^) D: x8 j& o# g! w
854971 ALLEGRO_EDITOR INTERACTIV Capability to add cline segment in a temp group$ b. }, L8 n& C4 o7 G4 i$ |
860772 ADW PCBCACHE Save Shopping Cart (pcbcache) is crashing component browser# ~1 `/ T- G7 [/ u2 C, M
867842 CAPTURE PROJECT_MANAGER Capture crash with 'Open File Location"
/ s5 O7 y& f1 G) G/ `868306 CAPTURE CONNECTIVITY mirror vertically removes junction creates extra nets
% {: b& Z8 ]% a* z# Q& i `/ ^882677 EMI RULE_CHECK bypass_plane_split fail if BYPASS_XXXX_EFFECT_DISTANCE" G- E9 d2 L% J
891439 ALLEGRO_EDITOR INTERACTIV moving cline segments& S2 Y; R+ ^( T# k
893544 ALLEGRO_EDITOR INTERFACES IPC-D-356A netlist issue with BB vias.
) `0 e( z `0 o% u5 W) u- O& d0 v893765 ALLEGRO_EDITOR PARTITION Mail command not sending out email on Linux platforms.
! |, ~3 B+ m' g# r( h894390 SIP_LAYOUT EXPORT_DATA Generate all balls in the xml file for export to EDI's readPackage command# T+ y7 i R* B. Q- _7 q9 h
895933 APD DATABASE Update Symbol shifts the center of the Dynamic Fillet and creating DRCs3 ^5 f; \6 @3 o! ?
896598 ALLEGRO_EDITOR PLACEMENT error message is misleading( L1 g7 p) q4 k7 c; F4 R
897196 CIS LINK_DATABASE_PA Schematic Contents are not shown in CIS window while link Dbase part for parts placed from library
' {) R3 A- L' O, J% Q# b/ v$ r+ {898598 ALLEGRO_EDITOR MENTOR Negative planes from Mentor Board Station not being translated.# C4 `$ f$ Q5 f
899556 ALLEGRO_EDITOR ARTWORK Import artwork seems not to work correctly.
& T+ ^8 o+ I0 y* o900501 ALLEGRO_EDITOR PLACEMENT "lace Replicate Apply" is showing lot of DRC's during placement of replicated circuit in 16.5
) H4 C, w0 d5 Y3 L5 ?) Q M901141 CIS EXPLORER Japanese character appear garbled in CIS explorer window.9 ~2 d5 u: [8 }+ Q) b
901666 CAPTURE OTHER Home page of Flowcad-Switzerland and Flowcal-Poland is not preserved on captre restart on start page
R( V+ x9 d6 g( M3 p' M8 _! i902066 ALLEGRO_EDITOR DRC_CONSTR Shape in Region not follow the constrains
% l9 p! j/ C* x/ `* ]% i4 ]0 a' D902349 CAPTURE LIBRARY Capture crashes while closing library3 O- @6 G1 _6 x! X6 M1 O x
902508 F2B PACKAGERXL SPB16.5 Packager-XL consumes much more memory than 16.37 e2 @ \1 y2 I1 J
902841 CAPTURE GENERAL Capture Start page does not show
& \9 c& j, T0 ^4 }902876 F2B PACKAGERXL Packager fails on the design upreved in 16.5
) D+ @2 T' U* a: i- v902959 CONCEPT_HDL HDLDIRECT HDLDirect Error while saving design
% K! O4 c& E) c+ _903171 PSPICE NETLISTER Why Capture is treating hierarchical power ports as floting nets in complex heirarchy designs?4 _* K1 C& `5 A1 l) M/ K0 M2 A
903713 ALLEGRO_EDITOR PARTITION Placement Replication do not work fine in the Design Partition! o# t4 @1 ^% _: h5 e- G1 h
903799 SIP_LAYOUT DIE_EDITOR Disappear die pins after exiting co-design die editor
9 Z6 ~/ m4 S h1 ]- x! D904021 ALLEGRO_EDITOR OTHER Export PDF from SPB 16.5 produces a file not text searchable$ ?* S8 M. {3 m8 V" x: b
904339 CONCEPT_HDL CORE new design crashes using the attached CDS_SITE
9 t2 g7 e1 y6 g4 A( }* ^ R$ h( x904522 F2B PACKAGERXL Part will not package in 16.5 but packages in 16.3" O$ p/ Q& t1 j- K6 e
904764 APD OTHER Enhance Scale Factor of Stream Out to support 4 decimal places
, j/ R; H/ \# X6 o/ N+ H904771 ALLEGRO_EDITOR MANUFACT Pin Number display issue.
* D; A, r7 O* l904853 ALLEGRO_EDITOR GRAPHICS Enhancement for showing Static shape as it was seen in 16.3
. v r9 N6 H. n, x9 l; z905144 CONSTRAINT_MGR ECS_APPLY Min Line Spacing is larger than Primary or Neck Gap less(-) Tolerance but No Warning in CM% q& U) S% Q# R% h6 V3 m v* T
905314 F2B PACKAGERXL Import physical causes csb corruption
/ w4 R [6 V% Z" f5 r905337 CONCEPT_HDL CORE ConceptHDL crashes after Import Design process.
; V6 d3 V- M; ?* O; f905533 ALLEGRO_EDITOR INTERACTIV Pin numbers for components on BOTTOM Side are moved in Preselect mode,when the BOTTOM layer is invisible
. A" C1 g7 M+ S" \; M905796 CONCEPT_HDL CONSTRAINT_MGR Fujitsu CM issue inaccurate concept2cm diff pair issues/ l9 U8 \4 b) a: w! F. d/ r
905811 CAPTURE EE_INTERSHEET_RE interesheet references in the form of grid grid page number instead of page number grid& e |% z1 r+ b
906118 CONCEPT_HDL CONSTRAINT_MGR Cannot open CM if SIGNAL_MODEL value was not assigned in ptf.
* C$ G' s8 z3 u906153 ALLEGRO_EDITOR SCRIPTS Unable to run allegro script in batch mode on the attached board.
5 |6 p' C6 t) @* {906182 APD EXPORT_DATA Modify Board Level Component Output format
) L/ F; p; k1 Q2 l( f906200 ALLEGRO_EDITOR DFA Enh- DFA drc invoked in Batch mode returns false constraint value in Show Element$ e5 n+ X! l- m/ P
906517 PSPICE PROBE PSpice new cursor window shows incorrect result.
4 k( C9 ]* V7 K% O% G/ O& N ]906627 ADW COMPONENT_BROWSE ppt options are not read if ucb is launched from FM. works fine if launched from dehdl." j& ?- {% V: Y5 r; J8 v
906647 SIG_INTEGRITY LIBRARY lib_dist creates a signoise.log in current directory (with backup files like ,1 ,2 etc.) on each run
( i% b$ y, X$ p8 \0 w906673 F2B PACKAGERXL Ignore the signal model validity check during packaging" z7 c2 G$ i# X- Y' @: L- B5 U
906688 ADW LRM A copy of source design gets created in worklib of target design after 'Import Design'
( s2 D' i) j/ E2 V906750 ALLEGRO_EDITOR PARTITION Importing design partition removes the testpoint reference designation
! ?( w! t2 S! s' [906874 PSPICE NETLISTER Error less than 2 connections for unconnected hierarchical pin2 u/ r4 u3 A7 Q8 @
907095 F2B OTHER Part Manager does not show Error as Undefined when directive ptf_mismatch_exclude_inj_prop is used
3 @% u; K; f) O& V907424 ALLEGRO_EDITOR GRAPHICS Allegro add option for pre 16.5 shape display
( {+ Q# Y. {, s907490 CAPTURE NETLIST_LAYOUT 16.5 Layout netlist is not correct. It differs form 16.3 layout netlist.
" r& m" D. g8 `; o% m) n907884 SIP_LAYOUT MANUFACTURING Need to add an "NC" pin text option for "Manufacturing Documentation Display Pin Text" l t4 k8 y. f# J0 d
907885 SIG_INTEGRITY OTHER Matchgroup targets lost when importing netlist to Allegro layout in HF312 @( k8 ^+ f; T$ U* Y' j: K
907929 CAPTURE TCL_SAMPLE TCL command to delete a property from parts in a library is not working correctly/ R. J, h6 V! v2 D z- v
907933 SIG_INTEGRITY OTHER Single line impedence not working in OrCad PCB Professional
7 y. d0 ~4 I% f( D$ U907963 CONCEPT_HDL CORE Design uprev issue when moving from 16.2 to 16.54 T; R4 d' T; t% {, n+ a
908000 SIG_INTEGRITY OTHER Inconsistence z-axis delay reported on Tpoint when define at via location.) h& N$ G& ]; _4 {% j
908057 CONCEPT_HDL CORE DE HDL crash with the cut and paste of a signal name
# X g4 N- w: `& w908060 CONCEPT_HDL CORE CTRL+LMB Option not working correctly in 16.3
( {8 [- J; S7 p/ a& b [908210 CAPTURE CONNECTIVITY Connection is being lost while dragging a component' T6 |1 o2 u$ U$ X
908241 CAPTURE DRC DRC error column is blank in DRC markers window in 16.5
- z: I" u; [7 S" Y% |5 e& [) n& u908339 RF_PCB BE_IFF_IMPORT mechanical holes VIAFC are not at the right place7 ], i( ]; `" r5 S- U7 \
908534 SIP_LAYOUT SYMB_EDIT_APPMOD issues with symbol editor and copying pin arrays2 m: ?# s. g3 n) k2 \
908535 F2B DESIGNVARI When I try to view my variant file the variant editor crashes) \3 p# J" m- |/ v1 u6 x
908595 APD 3D_VIEWER cadence Design 3D viewer" screen pops up and is all black because the colors have all converted to b
: o6 I2 K* w5 ` o908849 CAPTURE ANNOTATE Getting crash while annotating the attached design
; ]- _2 E M- A908874 CONCEPT_HDL CORE Part Manager - No Part Found error when using CCR# 775788 feature9 c5 ^) J' H' s" R4 a
909077 CONCEPT_HDL CORE After packaging pin numbers remains invisible even when $PN5 T) H# E6 c" {$ S
909104 ALLEGRO_EDITOR SYMBOL Warning message needs to be modified. It does not save the symbol and also not tell the actual problem.
* {' D5 `3 Y* b! H* U1 Q! k- ?909417 ALLEGRO_EDITOR REPORTS "report -v upc" returns 'Segmentation fault' on Linux5 a1 n% f7 D- X# K9 P! B* n
909635 SIP_LAYOUT DIE_STACK_EDITOR Add Interposer crashes in SiP Layout0 d) {2 ~. X* L: b+ Q
909749 ALLEGRO_EDITOR MANUFACT Allegro Crash during dimensioning% E9 D. O; j# O$ u r2 j
909760 SIP_LAYOUT MANUFACTURING Create bond finger solder mask doesn't follow the mask opening as defined in the padstack2 U7 ^( t' F1 g; p! x: w
909861 F2B PACKAGERXL NetAssembler broken within the latest 16.30.031
$ p2 n" b [1 t$ p$ _910006 CONCEPT_HDL INFRA Motorola design fails to uprev from 16.3 to 16.5, xcon file is getting corrupted.
4 p# V5 K- s+ R8 k. [5 J3 w# t910141 CAPTURE NETGROUPS Modify NetGroup definition does not update Offpage Connector8 C% r* b) D' G& ?2 g
910340 ADW LRM Import design in schematic, only 1 page import, the entire block is getting imported./ \* s0 f2 M$ F" ^+ J+ S
910678 SIG_INTEGRITY OTHER The Analyze> Model Assignment> Auto setup is not creating/assigning models to discrete components in 16.57 v% l) G3 U9 {8 w
910713 F2B DESIGNVARI Variant Editor crashes when you click web link under Physical Part Filter window.9 b5 s3 ^8 E" }/ t5 ?# T
910936 F2B PACKAGERXL ConceptHDL subdesign net name is inconsistent4 C$ y7 j" Y: I$ C
911530 ALLEGRO_EDITOR SYMBOL Package Symbol Wizard does not create symbol with the name given
' o( ]2 c1 E! a! x8 }911631 CONCEPT_HDL CORE DEHDL crashes when opening a design
# L4 K1 z$ A7 G' W# h# l4 O912001 ALLEGRO_EDITOR OTHER option_licenses entries are made in allegro.ini even when not set as default2 r9 ]. J/ J" R7 w) }8 z
912459 F2B BOM BOMHDL crashes before getting to a menu6 I J2 H' ^: |+ C8 J) w8 B
913359 APD MANUFACTURING Package Report shows incorrect data
$ _0 s) ^. D, t; i
# Z) N7 ?, Y7 T$ U! K9 T J, y( kDATE: 06-24-2011 HOTFIX VERSION: 001
0 W2 M/ |3 @ l===================================================================================================================================
+ Q% w* q& c: zCCRID PRODUCT PRODUCTLEVEL2 TITLE; n: C3 U; {9 c. ?1 t3 a7 O
===================================================================================================================================' \7 Z% P j" p& Y
293005 ALLEGRO_EDITOR DATABASE Allegro crash when attempting to move mech. symbol
) ^5 y0 |4 ]" P2 N( j298289 CIS EXPLORER CIS querry gives wrong results- _5 U: G- n. e9 W9 [. T2 u/ T& S
366939 ALLEGRO_EDITOR OTHER Cannot attach refdes on silk subclass with add text
3 p/ Y; X, i$ ^( G* }432200 ALLEGRO_EDITOR MANUFACT Fillets with an arc are required for Flexi designs" j5 h* U2 @+ N5 n* X6 h- V9 C
443447 APD SHAPE Shapes not following the acute angle trim control setting.4 O+ y% l7 H% L# v
473308 PSPICE AA_SENS Passing variables to lower level blocks using subparam+ Q( ?: `) { a7 x: z0 P0 P
517556 PSPICE AA_SENS Advanced Analysis does not support variables being passed down the hierarchy
+ K5 _, i }) a4 Z$ \6 J! d9 v548143 ALLEGRO_EDITOR SHAPE Dynamic shpe on Etch TOP will not void properly.$ E2 I6 }% F- V3 ]0 E
606959 ADW COMPONENT_BROWSE Key properties with blank values are not getting read in shooping cart' E- ~& A( T9 [' q' c+ \" H, V
616466 ALLEGRO_EDITOR SHAPE Solid shapes are not getting filled4 D" U( f: z) f' \4 o4 n
641358 SIP_LAYOUT DIE_STACK_EDITOR Request for Via and Multi Layer Pin support for DIE stack Area (blue region)
3 X- \5 e/ f, L, d. P644122 SIP_LAYOUT OTHER SiP Layout - xsection - ERROR Adjacent conductive layers are not allowed, but these are diestack layers not conductor* C W$ \8 `9 d* b( s9 |3 s
645816 ALLEGRO_EDITOR SHAPE Slide a cline all removes gnd shapes on board
( Y- C, ^- o2 e% ?2 M725355 ALLEGRO_EDITOR SHAPE User can not voided Logo correctly.. \- P2 @) a P" E1 V0 o
763569 CONCEPT_HDL CORE Display status of Hide/Show unconnected pins icon in DE HDL UI
8 E& v' x& w1 j770021 CAPTURE BACKANNOTATE Changing pin group property after pin swap resets pin numbers" d1 i7 q% b% o+ C1 o# }8 o
792126 CAPTURE PROPERTY_EDITOR Attempt to change display for occ prop resets
% S8 ]/ d" G$ Y/ k2 M5 [* s799014 CONCEPT_HDL CONSTRAINT_MGR concept2cm errors not shown in export physical after hier_write' z; g+ ^& o3 L! t
803147 CIS LINK_DATABASE_PA Link DB part should not change RefDes of multi package part. r6 b) k' R( G, x% P3 }, O
804240 PSPICE DEHDL Problem in simulation result for a multi-section split part.1 ^. }( { c; C: h/ B
809118 CAPTURE NETLISTS ENH to compare two schematic Capture designs6 g* t- N& O2 ~% S, D" |3 w
816568 ALLEGRO_EDITOR SHAPE shape disappears when update to smooth.. State no etch
; P- r) R1 B; }* z6 _830053 CAPTURE STABILITY DXF export fails if schematic folder name as /# v. U# R% [! @- i( x" R% P0 k
832108 ALLEGRO_EDITOR SHAPE Shape void incorrectly.
( E! @( Q" C1 A$ t' p ]833542 CONCEPT_HDL CORE PDF publisher font is NOT WYSIWIG with respect to what seen in DE HDL3 F! `6 R* v% U# s6 y2 l
835777 CIS DERIVE_NEW_DB_PA For XLS, donot display table as worksheetName$worksheetName to avoid 8012 error
: _5 ]* L1 ? M) N( O/ s837640 CIS GEN_BOM date format of CIS BOM has broken macros of 16.2 in 16.3 version6 f4 V+ o3 r4 g% A- T
844074 APD SPECCTRA_IF Export Router fails with memory errors.
9 D4 E! m+ U- P3 }. U851595 CONCEPT_HDL CORE Pin numbers overlap on the pin and increase in size
5 Y O& r4 h: `+ T4 E' C) ]852832 CAPTURE BACKANNOTATE Why is Capture crashing with Mentor back annotation?
. T7 d( f4 U" o7 B855015 ALLEGRO_EDITOR OTHER The rats are NOT connecting to the ends of the clines like they should be.
. ]$ S- k+ s/ ]3 t+ o! u3 Y859883 CAPTURE NETLISTS ENH to compare two schematic Capture designs
+ _8 L2 u; j3 K; o& a$ H! B! ` I866009 SIG_INTEGRITY OTHER Net with Pull-up/down should not be used for Diff-pair.+ t# a, m. C5 S( ~- y
866830 SCM REPORTS Multiple lines added as separator between title block and report header instead of single line
4 b, M. B4 ]9 e! F4 ~9 a866833 SCM REPORTS Extra indentation is left in the left side of the report when the Line Numbers are set to OFF
. S% l0 }; j# v0 o# V' a868618 SCM IMPORTS Block re-import does not update the docsch and sch view8 v# _6 k7 x: X0 q* p [. r, B
873402 SIP_LAYOUT LOGIC pin swap for co-design die in SiP3 T( P3 E F9 S2 l
874010 SIG_INTEGRITY OTHER PCB SI crashes when the Xnet is extracted with VARIANT_TO_IGNORE property.
# Y0 l0 Q9 A# a! ]0 S4 U* Z874400 ALLEGRO_EDITOR INTERACTIV Flip mode issue with move command
% K6 b2 _* I5 p% F5 Y874966 ALLEGRO_EDITOR INTERFACES Placed mechanical component do not get Ref Des or part number in IDF file9 |2 N! P- q; d& f: A ?, V
875709 ALLEGRO_EDITOR REPORTS Film area report generated incorrect data at l1
+ x* S, V6 a* ^& S8 w' g6 X( ^876275 CONCEPT_HDL CONSTRAINT_MGR Constraint Manager not retaining target net: d0 z2 @ `6 C7 `. Y( q F9 ^6 |
879361 SCM UI SCM crashes when opening project
% t- a4 V7 R/ c% a879496 CONCEPT_HDL OTHER Customer wants to have the tabulation� key as separator in HDL BOM.) |& R1 ?3 X0 l3 n* `
879514 PSPICE AA_MC Monte Carlo to handle equation as comp VALUE.
5 f, g1 x# _5 T7 g" z! f881845 ALLEGRO_EDITOR SHAPE Delete island deletes complete shape
1 q0 H; Q1 k% @2 y882413 PDN_ANALYSIS PCB_PI PDN Analysis should support routed power nets
1 K( D6 X% Q; @882427 PDN_ANALYSIS PCB_PI PDN Analysis target impedance should have a variable multiplier, H' k/ u% Y+ I0 K
882567 SIG_INTEGRITY OTHER PCB SI crash if boolean type prop was specified to VARIANT env.
( j5 A' W" {5 W0 P$ Q! \+ `882644 ALLEGRO_EDITOR PLACEMENT PCB Place Replicate Function automatically match Enhancement
. a0 N D2 x4 I3 T+ O1 M( `; ~883164 ALLEGRO_EDITOR INTERACTIV Vias marked fanout moves away from position when moving component
" E0 p) U( H3 w" a. ^* K# r883224 SIG_INTEGRITY SIMULATION crash while reflection simulation from Constraint Manager$ e7 `8 p3 c" s2 [4 j+ U
883760 PCB_LIBRARIAN METADATA Incorrectly formatted revision.dat file in the metadata folder
' P3 J0 _; _! R9 W: X2 J% Z; x885391 SIG_INTEGRITY SIMULATION RLGC data sampling algorithm and w-element interpolation., \; q) c) O- L
885849 ALLEGRO_EDITOR MANUFACT Silkscreen Audit cannot find Solder mask for the text string5 C5 K/ ?8 o. b0 Y
885996 SIG_INTEGRITY OTHER The effect of sn_maxwidthlimit user preference is not seen in cross section impedance calculations
. q# _ I! b5 s8 O$ w& @9 v+ g n886090 ALLEGRO_EDITOR INTERACTIV Add Arc w/Radius does not snap to grid' P Q5 ]" b) y- _% j) e2 ~
887180 CAPTURE SCHEMATIC_EDITOR Signals Navigation window doesnt get updated for Buses2 \% y9 y! U3 f/ {6 B
887442 APD SHAPE Copper pour of Dynamic shapes on Top layer which contains many existing signal traces fails.. {* t' B0 O( _
887578 SCM AUTO_UI Component Replace pops-up the DSPANE-204 Message) d- A: M7 {! Y. e
887926 SIG_INTEGRITY GEOMETRY_EXTRACT Field solution failed if diff trace on bottom doesn't have reference plane.
# y: j) E; w t+ v2 ~: G4 p888414 SIG_EXPLORER OTHER View Trace Parameter display the thickness of dielectric incorrectly.
: H( Y) Y# X- z4 @- n8 G888600 CONCEPT_HDL CREFER Cross References not added to Schegen schematic, m! c/ J4 l9 j; K8 h2 N- J: |5 s
888679 SIP_LAYOUT SHAPE Can't create the Dynamic shape on layer M1_sig without unwanted horizontal openings appearing.
$ v, S; `$ P! W0 }& ~/ V888804 ALLEGRO_EDITOR OTHER Fillet will become static shape after import from partition board.! A x$ k+ V8 c3 x, k6 K! k+ J ^
888945 CONCEPT_HDL OTHER unplaced component after placing module
G2 |$ n) o) f889222 ALLEGRO_EDITOR SHAPE Allegro freezes/hangs when adding shape as Polygon with OpenGL ON.; j. c1 }; B2 s U3 t1 V& b. q# t0 T
889365 SIG_INTEGRITY GEOMETRY_EXTRACT top/bottom trace impedances extracted to sigxp are wrong in 16.3
' ^) e$ s6 C8 q! n# N889404 ALLEGRO_EDITOR OTHER Incorrect pad size for Top conductor padstack written to column 59-62.
0 m, ~) J! z/ W8 ^889426 CONCEPT_HDL CHECKPLUS CheckPlus does not find single node net
! E E% h2 @" X. G/ c" A/ _ u889636 ALLEGRO_EDITOR MANUFACT Incorrect spelling of "Visibility" in "Film Control" tab in the Artwork Control Form
$ R) T) {. k E* ]( R0 h! r3 ?' |891235 F2B PACKAGERXL Packager crashes without creating a pxl.log file) U+ Z5 O/ k$ k& f% L
891292 ALLEGRO_EDITOR SHAPE arc routing causes weird undesireable shape fill performance4 P2 q w9 e5 X+ M
891856 ALLEGRO_EDITOR EDIT_ETCH crash when sliding diff pairs/ y. h4 p4 w. k' _
892375 ALLEGRO_EDITOR PLACEMENT Place Replicate Update disband other groups, irrespective Fixed property added or not.
0 q/ N% M4 E" `* U892455 ALLEGRO_EDITOR SYMBOL Why the overlapping pins are not reported with DRC?
% u1 I' o+ @- x: ]. y1 X& q892541 SIG_EXPLORER OTHER Export/Import layerstack through the technology file is changing the layer thickness
7 e' q/ ~4 h9 }! z3 o; e7 p892766 APD WIREBOND Excuting Finger moving cannot push aside finger to move with together by shove all mode( b s" Y# V3 T- B3 t
892907 ALLEGRO_EDITOR DRC_CONSTR DRC not reported for etch_turn_under_pin violations
8 C% Z$ }5 q6 H6 ?892963 ALLEGRO_EDITOR SKILL Bad shape boundary created after axlPolyOperation 'OR
5 O% o# f7 c% U* [892964 SIP_LAYOUT LOGIC Request that Edit Parts List use Dashes "-".
% \4 _; b' Z- j" ?: Y( n' s893295 APD WIREBOND Why move wirebond command does not shove wirebonds? This result in drcs.
1 C$ o7 R& \1 H' p( C5 @893706 CONSTRAINT_MGR OTHER On line DRC hangs on partitioned board
J5 A# m; d' D |893743 APD EDIT_ETCH Route behavior when spanning pads not as expected.% e/ k* o n4 @6 ^
893783 SIP_LAYOUT OTHER Padstack Design Editing update File menu with a Update to Design and Close instead of 2 operation
' g1 K6 z' y8 b+ y; W894456 ALLEGRO_EDITOR REPORTS Request Net names be added to Propagation delay lines of the DRC report.
: |% @" e8 U% h: u5 r1 a894499 SIG_INTEGRITY LIBRARY Tool crashes when moving a cline or selecting the Info icon with OpenGL on.1 f$ j. s/ Q- z
894582 APD SHAPE When making a dynamic xhatch Via shapes surrounding are abnormal.. P3 N" }. Y: L9 [# t" i/ s
895542 SIP_LAYOUT WIREBOND SIP design crashing when moving bond finger using blur mode BLUR_BONDFINGER_PRESRV_CON/ q) x* l+ X$ t( J! ]# E
895591 ALLEGRO_EDITOR PCAD_IN Importing PCAD file fails to get to the point where we can map layers# c, F+ L4 Y' x" e' G
895757 APD ARTWORK Import Gerber command could not be imported Gerber data
2 C7 y& j' c( `' p895964 CONCEPT_HDL CHECKPLUS The CheckPlus command getFileSubstrings is not working correctly
/ C. W$ G# ~9 @: c- v) |- ]+ l896428 SCM UI Changed Ref Des value not maintained in DEHDL block when part is replaced
0 Z2 C7 |2 M7 t3 d2 m5 o& Q896655 CAPTURE EDIF Import/Export Design of Hierarcy design with OrCAD Capture3 }% }: l5 E( V
896846 CAPTURE IMPORT/EXPORT Import edif2cap and capture is crashing
" [7 t6 z- j8 D. p$ ]+ ]897155 ALLEGRO_EDITOR REPORTS Copper coverage in L2 and L7 looks like the same but film area report had large gap., F+ ]9 j% B" G( H2 P) K
897654 CAPTURE EE_INTERSHEET_RE Capture crashes on adding intersheet refernces in abbreviated format on attached design.
8 H6 \& H! t8 l" k, T* s899344 RF_PCB BE_IFF_EXPORT dlibx2iff does not provide the component boundary drawing/ l+ \" n* I1 }, h* S% H
899629 CONSTRAINT_MGR OTHER ECset for Total Etch Lenght is not present in OrCAD Prof8 y9 o( ]! g# X, h
900175 CONCEPT_HDL CONSTRAINT_MGR Few Xnets are lost from Match Group after packaging and importing the netlist to board file.% N; H2 W9 F* B" Y& ?
900481 CONCEPT_HDL CORE Genview creates a larger symbol without taking the no. of pin in consideration
, |' S" D' P1 H) l" l6 O3 l6 P: A900813 ALLEGRO_EDITOR DRC_CONSTR With rotated pads, pad (pin - via) soldermask spacing DRC is unreasonable.
3 d- D9 y$ T5 V, A7 f0 h- c900905 PSPICE STABILITY Simsrvr crash and RPC Server unavailable error while running simulation." R' _ {2 W( V
901783 CONCEPT_HDL CORE CDS_PART_NAME is annotated on the schematic canvas after running back annotation in 16.5# @5 I g* W# E9 W' @2 W
901909 APD EXPORT_DATA The "package_pin_delay_length.rpt" with Z-axis delay turned on seems wrong9 s2 q4 P: y3 C3 a; T3 A1 ~( F
901987 CONCEPT_HDL OTHER SPB16.5 zoom fit does not center the page while ploting the schematic page
# \3 B8 z6 f! N: j7 o. h0 y902133 CIS OTHER The visible part property value are being shown very distant from part graphics on schematic
% c) Y- ?9 R9 `% W4 p$ ]" L902166 SPECCTRA ROUTE Specctra crashes when reading in "bestsave.w" file
# Q: n4 E" m0 B- q. k902170 ALLEGRO_EDITOR DATABASE Diffpair Issues with OrCad PCB Designer Professional, i0 O6 O- X( a/ E6 D5 Y# K
902177 CONSTRAINT_MGR CONCEPT_HDL Option to view the layer thickness in CM worksheet through worksheet customization
?4 X! d/ O! w! l7 b902463 ALLEGRO_EDITOR INTERACTIV APD crashes when we click ( show element ) on certain components/ n6 k5 F; D. a) R+ B5 D
902621 CONCEPT_HDL OTHER Design Differences (vdd) Crashes4 u" I; L( h' C, k3 O3 u! k
902909 APD WIREBOND die to die wirebond crash
; e/ D0 i2 k5 M& M1 y; s; Q& `1 f/ {902933 ALLEGRO_EDITOR PADS_IN Pads_in fails while reading PADS ASCII file body: p2 x; S0 T% t$ j5 t8 w
903284 PDN_ANALYSIS PCB_STATICIRDROP IRDrop voltage gradients are plotted outside of the PCB outline
. X' T8 i* j' f6 }903680 CONSTRAINT_MGR ECS_APPLY Constraint Manager not passing all hiearchical member objects to a custom measurement.3 W0 c( Z- m8 r/ H3 [
904403 ALLEGRO_EDITOR DATABASE Allegro crashes when refreshing module |
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发表于 2012-2-21 14:58
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