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DATE: 02-17-2012 HOTFIX VERSION: 016
; {: H% f1 J7 \) s1 p1 m; h, k6 z9 q# x===================================================================================================================================4 Z3 F4 f% R5 U: U7 t0 t1 B
CCRID PRODUCT PRODUCTLEVEL2 TITLE& f e% M0 c4 j) v3 [' J8 h
===================================================================================================================================
! e% L; a9 V( k5 U% b# J3 J- R840105 PCB_LIBRARIAN USABILITY PTF subtype is getting changed when Save As option is used in PDV; b1 U3 M2 w) Q7 w) O: J8 W
873075 Pspice PROBE Decibel of FFT results are incorrect.
0 ~: z4 o# i9 O7 a6 }" u938744 ADW COMPONENT_BROWSE Need ability to customize shopping cart columns to include any Part property# [- ?7 F% r2 ~, k+ }# X* j
943003 SCM REPORTS The dsreportgen command fails with network located project
; t2 l' Q' K! _. B: o5 @) `961530 allegro_EDITOR INTERACTIV The problem of Display measure command0 S I/ o' i! a" d0 r9 Z
962157 concept_HDL CORE Where is the setting for enabling the Enable PSpice Simulator menu?
& D+ c. D+ Y# o! e( w% P7 k1 u962206 CONSTRAINT_MGR CONCEPT_HDL Import physical not passing all constraints from the board to frontend: X8 [# |0 J; |* U" h$ i
968205 PSPICE DEHDL_NETLISTER Change SPLIT_INST property to PSICE_SPLIT_INST for Quad Switch type of design.6 ]8 u( t8 L; N3 M4 n
968509 PCB_LIBRARIAN METADATA Incorrect pinlist.txt was generated if DIFF_PAIR_PINS_POS/NEG was set.
3 D* o8 J- ]' n$ q% z969450 LAYOUT TRANSLATORS orcad Layout to Allegro Translator crashes& z6 V7 {% E" D; k9 p. c
969997 CONSTRAINT_MGR CONCEPT_HDL ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance pro~
N( c! s4 |2 s5 V) W1 |5 _971193 CONSTRAINT_MGR UI_FORMS Copy and pasting a formula causes the application to crash on windows.8 _' t% A) q$ d, P
971601 CONSTRAINT_MGR CONCEPT_HDL ERROR(SPCOPK-1053) and WARNING(SPCODD-66) because of directory structure4 o" b5 [& O- }# z; R2 X1 C
973398 CONCEPT_HDL OTHER It should be not packaged with error while working the packaging process if the design has a ERROR
* U: ]" z' X* ` Q \973859 PSPICE ENCRYPTION Pspice crashes with encrypted model
H+ ]6 O6 I2 b973938 PCB_LIBRARIAN VERIFICATION pc.db is missing
" G/ U2 s& n, e# q* v5 j# ~$ M974540 CONCEPT_HDL CORE Graphics updates are real slow
# @7 j+ ]' ^, o0 j- }: l974791 F2B DESIGNVARI Variants are not back-annotating to schematic and turning to ?- m, u6 x" ^" y4 s6 |) C: H9 Q
974818 ALLEGRO_EDITOR NC Backdrilling produces 0 plunges yet no errors reported." d& Q1 w& l* w( t
974945 ALLEGRO_EDITOR skill Why is axlPolyOperation is giving different result and not working" r' e6 y& N9 H$ N
974946 MODEL_INTEGRIT TRANSLATION ibis2signoise returns the error - Delay measurement fixture must contain V for ECL technology
9 a @ E8 g# y975396 CONCEPT_HDL CONSTRAINT_MGR Constraints are dropped after migrating from 16.3 to 16.50 X+ t8 P( V: Y! J7 h( F. \: ~* |4 B
975633 ALLEGRO_EDITOR GRAPHICS 'dynamic_layer_visibility' option in 3D Viewer when checked or unchecked should not change (until next change)7 ?) ~* m* S. h. |# O, R
975720 ALLEGRO_EDITOR DRAFTING Datum dimension lines not adjusting to text move& T6 I5 _8 \& Z' Z" w O$ f. |' O8 |
975745 ALLEGRO_EDITOR SKILL cdsServIpc different 16.2 vs 16.5 when Allegro exits
2 p: d) J, Y$ x6 e4 o3 l0 y976013 CONCEPT_HDL INFRA Power pin connection of FPGA symbol is missing in netlist.
* P9 ~, }! m! Y* o976058 CONCEPT_HDL COPY_PROJECT SCM Copy project does not create the con and dcf files in tbl_1 views8 y$ z( ?: L7 I; b0 k; ~$ P
976073 CONCEPT_HDL COPY_PROJECT All the constraint data is lost in the SCM copied design
1 J" C0 f6 `+ c, W976160 CONCEPT_HDL CREFER Cref fails due to some Caeviews error in the design G) r S; x- X; g7 G
976204 ALLEGRO_EDITOR DRC_CONSTR Application falsely reporting Mechanical Pin Antipad to Shape Spacing DRC
! M) u9 Q# e, W5 `" i976448 F2B PACKAGERXL ERROR(SPCOPK-1069): Invalid POWER_GROUP property value$ Q4 g& ]9 i! [. U2 Y. P( \# A
976521 ALLEGRO_EDITOR DRC_CONSTR multi-thread update DRC causes the application to crash
8 R) ?8 C. n6 i1 k9 a% {976838 SIG_INTEGRITY OTHER Unable to create XNET for highlighted nets on attached database even after assigning proper Signal Models.' I4 M0 k4 ?+ I! n
977517 F2B PACKAGERXL Export physical fails after update to 16.5 from 16.3
; ^$ |3 v% w( m* \3 u* A0 B+ T$ a977902 ALLEGRO_EDITOR DATABASE generate module is crashing allegro# C0 @; D6 R" {8 N2 h! T3 j. C
978652 ALLEGRO_EDITOR pads_IN PADS_IN fails with ERROR: Finished with errors.$ y7 _8 Y; u1 k @5 T2 o
978744 APD DEGASSING Some shapes will not DeGas on this design0 a9 `; I% Q! ]
979940 SIP_LAYOUT OTHER SiP Layout Leadframe autobonding with profile selection
1 T- Y {4 C9 t% B, t981699 CAPTURE HELP Start Page still shows Hotfix 14 after installing Hotfix 15
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# g4 M. \9 I5 yDATE: 02-03-2012 HOTFIX VERSION: 0150 C' w- Z, c# I/ a) j. ?2 {! j! g
===================================================================================================================================7 W" {3 }" I3 @% T9 H- e
CCRID PRODUCT PRODUCTLEVEL2 TITLE0 y) K A; |2 N, g' L
===================================================================================================================================
8 k5 Q/ k/ Q t, \6 Y3 j871567 CONSTRAINT_MGR SCHEM_FTB Ability to filter out Single Node Nets from Constraint Manager, Z6 k' S' F$ R0 x+ O' C8 n
921436 ALLEGRO_EDITOR MANUFACT Change in 'decimal place' for new dimension changes the already placed dimension/ A5 B2 O2 L$ h4 s, l
941433 CONCEPT_HDL COPY_PROJECT 16.5 Copy Project should warn if trying to copy a 16.3 design+ O8 ^/ L. l3 {( \
954375 ALLEGRO_EDITOR MANUFACT Change dimension accuracy for few instaces of associative dimensioning
, W2 E! B. w% D, D2 D961646 PDN_ANALYSIS EMVIEWER EMViewer Help > About shows wrong version& J6 `& w# r6 w& Y
964912 CONCEPT_HDL COPY_PROJECT ASA project crash after using copy project
5 M& I# C% O: ~2 d$ U3 S$ R967223 ALLEGRO_EDITOR MANUFACT Bug:Oval slots orientation in one direction only
, [0 c7 Z1 }( l' ^. X968865 SIP_LAYOUT DIE_ABSTRACT_IF load of die abstract fails due to differences between component and symbol
2 ]; g, m+ |' {: D7 b) ^969485 ALLEGRO_EDITOR SHAPE Shape does not update correctly in 16.5
$ F$ D" ?: _6 M% y0 N- J) I0 P: {4 {970331 CONSTRAINT_MGR ANALYSIS Impedance worksheet shows a zero value for impedance+ A, p% g# N7 |9 |+ g: G! n
970600 SIP_LAYOUT SYMB_EDIT_APPMOD Option in Die Editor to be able to "physically swap" pins. H5 I# P5 B: N
970910 F2B PACKAGERXL Our customer has problem with pin color after pxl 16.5.
0 \8 G6 p1 o3 Q" [2 s c- G970970 SPECCTRA FANOUT Fanout Vias is placed far away from decaps and does not change the Fanout length even when max_length is reduced.8 ^+ D' o& [- F$ U
970985 SIP_LAYOUT OTHER Importing a .spd2 database file using NA2 will cause the APD/SiP tool crash
4 x; r! L4 v8 ]' z2 @) p3 V% N971757 CONCEPT_HDL INFRA Crash while Saving/Packaging the Design( ^# m1 e% A$ Q3 @
971923 ALLEGRO_EDITOR MANUFACT Allow to change decimal accuracy for dimension instances
6 ^6 I1 {5 ]0 m; P. f' W X' n& v972568 CONSTRAINT_MGR UI_FORMS Tools >Excel missing from CM
$ b& C6 D0 f q( V7 ~, |# i9 k5 ]/ F972821 CONSTRAINT_MGR CONCEPT_HDL connectivity server warning: Unable to add property WEIGHT( x" m" ~ |$ w v. Q
973185 SCM CONSTRAINT_MGR ASA2 block not seeing all instances in a package.
7 s' u: `$ A/ H) T' l- X973211 ALLEGRO_EDITOR INTERFACES IDX Object Type Change not recognized
7 X2 J' B8 ~( H& R/ o5 V973214 ALLEGRO_EDITOR INTERFACES IDX import package keepout height value change assigns incorrect value
8 V$ A2 ^. F7 \- X. M- b973384 CONCEPT_HDL CHECKPLUS The multiple SIG_NAME has to be occurred an ERROR at the SPB16.5." M2 z- i, o: Y$ h
973514 SIG_INTEGRITY OTHER Mapping error when Ecset is updated to constraint manager from extracted net
$ z9 n8 S. ]% f# K973950 ALLEGRO_EDITOR SHAPE Update to smooth crashes application7 o! ]' v1 j* T$ J7 T3 G" c9 v/ w% k
974533 SIP_LAYOUT OTHER Crashes in Edit > Die Properties and obviously has a setup problem.- |( d4 [( U& \ l
974809 ALLEGRO_EDITOR SKILL argument available for hiding a property with function axlDBCreatePropDictEntry is not working
' S- e, w1 F* X9 J! n9 ^6 @5 L6 r/ n; ~976179 INSTALLATION ISR Installation of ISR S014 to 16.5 on windows is breaking the documentation index
8 c7 o% O! r+ ?
" f8 D8 u" R! l- XDATE: 01-20-2012 HOTFIX VERSION: 014
7 a; t0 {/ \& Q. E9 w===================================================================================================================================
1 ]; z$ e; F( a+ ~' @CCRID PRODUCT PRODUCTLEVEL2 TITLE4 n+ d' a; D5 P) D
===================================================================================================================================
( R) g) D+ W) S$ a" }733285 PSPICE SIMULATOR Enhancement:In server-client installation use existing index file from server- P7 R/ D# J: D
941020 SIP_LAYOUT OTHER Soldermask enhancement3 p! @3 G0 i$ D0 Y# ~' B
946407 CONSTRAINT_MGR TDD When is it safe to open a 16.5 design in 16.3?
4 \6 E6 R5 k4 m9 X5 Q% S953067 CONCEPT_HDL OTHER Variant Editor "Error/Warning messages" form is unusable6 T2 P/ v1 u3 T9 B+ O7 I
954818 CONCEPT_HDL COMP_BROWSER Replace button turns to Add in component browser when a component replace is done on the schematic8 R& V2 I- s; J, X
956450 ALLEGRO_EDITOR DRC_CONSTR Analysis always shows analysis failed in uncoupled length in some diffpairs0 O/ P) b4 p4 [! K
958259 F2B DESIGNSYNC ds.exe crashes on a big design when accessing the design from network drive
' \$ W( M: j& O8 |. y5 b- z958395 ALLEGRO_EDITOR SHAPE shape voids won't merge: j7 I5 H! p! b2 b: F( B5 Q
959212 MODEL_INTEGRIT PARSE Attempting to use "Mark qualified" option on DML File results in dmlcheck and Modelsim wanrings.
6 } O3 O9 f4 d6 b959940 APD AUTOVOID Void all command gets result as no voids being generated.
- s8 ^! p4 Q" `, Y4 x960252 PCB_LIBRARIAN CORE Splash screen in PDV prevents showing error message2 g3 V# ~, U6 J4 W+ r
961634 PDN_ANALYSIS EMVIEWER Cannot launch PDN EMViewer from withing PCB SI! | e( v* Q. T; @1 {+ q
961645 PDN_ANALYSIS EMVIEWER Standalone EMViewer will crash when opening any result file in the form of *.emv file.& v7 b# s8 G9 y _+ F6 p6 s* \
961700 ALLEGRO_EDITOR SHAPE dbdoctor reports ERROR(SPMHUT-144): Illegal arc specification+ L# o" A) Q- [ x3 C
961733 ALLEGRO_EDITOR SKILL Allegro crashes. Appears to have a memory leak.
s' l$ s4 Q" V8 p! `961758 ALLEGRO_EDITOR DRC_CONSTR DFA check produces no DRC when the dfa bounds are not a rectangle.
8 {3 U7 j+ M0 u961887 CONCEPT_HDL CONSTRAINT_MGR Match Group created from ECSet cannot be deleted in the same session of CM
) ~* a6 s) D, t$ C) M962552 APD EDIT_ETCH BUG:APD crashing when we try to slideget information but move works fine& c/ o! P- r; J; Q$ l
962869 CAPTURE STABILITY Capture crashes after RMB click on rotated parallel wires
& d3 [/ U! K! }3 |$ V0 v! R' w/ M$ R# E963232 CAPTURE MACRO Macros not being played in Windows7/ o% @" ]* ~6 @9 K
963300 ALLEGRO_EDITOR DATABASE Create > Module crashes in 16.5 but not in 16.3: c( I: d$ V" [& W3 m
963651 CONSTRAINT_MGR CONCEPT_HDL ECsets are renamed after packaging on linux/ D. W/ ~% X8 p: W6 `
963663 CONSTRAINT_MGR ANALYSIS Q- Why the customized worsheet for Diff pair Impedance not analysing at all for this SIP design4 j, j3 k2 X3 ]) x* s p9 L2 L
963715 SIG_INTEGRITY OTHER Application only adds the bottom conductor thickness for the via z-axis length
% K9 q2 j! m5 q/ h7 Y9 F4 C964068 ALLEGRO_EDITOR INTERACTIV Allegro crash when using move alt sym mirror alt sym...
6 A. Q v* s4 ^1 s. U% G/ i F' O; P2 c964267 CIS PART_MANAGER Capture become non-responsive, working on Part Manager and creating CIS BOM, for large designs
* }- g$ N' H0 Z! X4 c964597 ADW LRM Issue of LRM license checkout after renewal license by 16.5 (ADW15.5_S23+SPB16.3)7 q1 {' Z) w' `7 S
966148 APD INTERFACES Character Limit for DIE Files (*.die) Import/ R# h& T9 O) e; W4 W2 z
966416 F2B PACKAGERXL Cannot package this design$ E; E+ n# y1 T2 b% \# h" \
966421 CONCEPT_HDL CORE DEHDL Crash when applying property on components in duplicated blocks
: B4 D5 g$ b' X" [3 e/ n966693 CONCEPT_HDL CORE DEHDL crashes when doing model assignment if CM is open
7 I0 v2 f: N$ F966795 ADW ROLLBACK rollback utility does not honor -product option from command line' H, \' j E- @; T5 E! ]5 W/ w% q
967089 SIG_INTEGRITY OTHER Matchgroups created by ECSet not deleted when ECset is removed from object.7 a% T) \% q! L+ D5 B7 Z
967222 ALLEGRO_EDITOR OTHER PDF export is leaving data off the drawing
) h0 p9 T$ e- O% e- S/ ]* h/ ]" F967240 SIP_LAYOUT WIREBOND Change default bond fingers selected on multi-site leads during "bond to leads" program- T, b( @* k2 U/ K3 V6 X" N" N
967297 ALLEGRO_EDITOR OTHER Dynamic Fillet&Eliminate unused stacked vias cannot be used as the Miniaturization option.( C0 w+ g' P( Y
967576 CONCEPT_HDL CREFER Occurrence location property values do not appear in flattened schematic generated by CreferHDL
3 N: G V1 s" @6 f" E: X/ c, I968096 ALLEGRO_EDITOR DRC_CONSTR Mechanical Pin to conductor spacing is not followed.
8 o- e( v* n5 w! a5 W3 f$ L968222 SIP_LAYOUT DIE_EDITOR die pin loses IC net for a co-design die with multiple ports within IO-cell, T/ t' K5 h& D$ [ C9 x2 I' f
968358 CIS PART_MANAGER Capture crash on removing a part from subgroup in part manager
$ Z% r4 Q: I0 z( q: D969594 CONCEPT_HDL CORE The dcf file is not updated with schematic changes' h- c0 r% [, z+ D" W% i
r+ x+ R9 v: iDATE: 12-16-2011 HOTFIX VERSION: 013% _4 c; f+ m1 c/ \! X6 R! u
===================================================================================================================================
' {% v2 q9 q- Z, [* k6 nCCRID PRODUCT PRODUCTLEVEL2 TITLE
6 h" l3 B1 K$ w& d===================================================================================================================================
4 B0 q- {% U$ I q' g875695 SIG_EXPLORER INTERACTIV Enforce Causality check box doesn't work.3 G7 } U2 @$ u; c* I
927148 CAPTURE PROJECT_MANAGER Capture crashes on creating scehmatic folder with name which already exists in design9 |7 i2 R9 A& l& N3 s* n3 h4 z0 {! e& u
938013 CAPTURE NETLIST_OTHER The netlist in RINF Format contained two identical lines for PCB FOOTPRINT+ w( R M% A7 y) _5 e* t0 e8 `
941409 PSPICE PROBE BUG : Search accuracy wrong in new cursor window4 |' ~. y4 R" b6 {
945242 SIG_INTEGRITY SIMULATION Unable to select "shapes" in find filter for 'show parasitic ' command
: A. }- G3 s+ q1 k1 _; ]( i& X946293 CONCEPT_HDL ARCHIVER Archiver hangs if there is a whitespace at the end of the path of cref.dat0 J; u% c; J; e- l- ]
946770 CONCEPT_HDL CORE 揤iew Design� function is missing in Windows Mode after reseting the menus.9 x) @/ R6 a! y2 w _; T
950994 CAPTURE NETGROUPS Problem in expanding the netgroup in Auto Connect to Bus function
5 ^0 X# u$ R% r/ P, c+ n7 ^953530 SIG_INTEGRITY GEOMETRY_EXTRACT Display Parasitics is displaying wrong results for EMS2D Field Solver compared to topology extraction using Probe.
8 }7 g( I L: D D! x953713 CONCEPT_HDL PAGE_MGMT Random page replacement/duplication in block! A/ l7 u" |* [! y$ @4 C! t
953917 CONCEPT_HDL ARCHIVER archcore should handle errors correctly
9 \* O- S: Y3 r4 q953971 ALLEGRO_EDITOR MANUFACT NC Drill files not generated correctly when using the option "搒eparate files for plated/nonplatedholes�
- R! R, ?/ g# m, A% p3 ^954400 CAPTURE NETGROUPS BUS members of NetGroup are getting converted to Scalars in Export-Import NetGroup.
% [- w0 N/ w# I1 h" w954498 SCM B2F SCM crashes when importing physical7 X3 E/ ?. b) F7 e
954623 ALLEGRO_EDITOR EDIT_ETCH Unable to complete connection with Add Connect - related to soldermask to cline check?
( G' f" h- t# J954894 ALLEGRO_EDITOR MANUFACT Dimensions disappear when opening database in v16.5 from v16.3
0 z2 d! u! n' }0 N0 y955029 CONCEPT_HDL CORE custom text font size not recognized in symbol view
6 I8 X1 |2 `) x! |; n% u955133 SIG_INTEGRITY FIELD_SOLVERS The Field solver creates the differential trace model which is reversed T(D1) and T(D2) of bottom side.
" M) ?. _& I. A7 R1 k955290 CAPTURE DRC Description for UPD0014 missing in the Browse DRC markers window
/ ?$ P" O) I9 M955299 ALLEGRO_EDITOR DRC_CONSTR drc text to smd pin does not work any more on this database in 16.3 S039- [$ ?0 \/ S) l6 H7 Z
955338 CONCEPT_HDL CHECKPLUS Need to change PART_NAME
* B Q6 x( t* ~9 M. `" L8 d955447 SIG_EXPLORER OTHER Model path set in DE HDL Model Assignment not used by SigXP from CM in DE HDL- H1 P, B) s* Q1 L r h9 e/ u
955740 SIG_INTEGRITY GEOMETRY_EXTRACT Crosstalk with Timing Windows does not work correctly0 Y% d* i: X4 K; M' ^
955749 ALLEGRO_EDITOR MANUFACT show element Info shows symbol dimensions on incorrect subclass' y% s! {" ]) v/ h$ X! {
955912 ALLEGRO_EDITOR OTHER Shapes with voids that are exported to PDF have gray filled area over the void5 X9 v+ [+ J0 j: h& C" ~' N: [* K
956129 CONCEPT_HDL INFRA DEHDL uprev hierachical design from 16.2 to 16.5 packaging failure.: U, L" I$ q/ R+ U4 _5 D8 S; U( {% b
956373 ALLEGRO_EDITOR NC drawing name doesn't display in the log file3 Y3 e6 X# @0 K1 b" H' V
956393 CAPTURE PROJECT_MANAGER "GENERAL" and "TYPE" tabs are missing from " roperties" dialogue box.
* g, v& B6 Y. y, E1 i" o! h: [2 G+ {956448 PSPICE MODELEDITOR Can not generate a DEHDL symbol from Model Editor, because no Capture license found0 }3 N) R6 n6 B
956456 CAPTURE NETLIST_OTHER OrTelesis netlist not transferring user properties defined under combined% I6 p" \9 R |3 X
956489 ALLEGRO_EDITOR MANUFACT dimensions lost when symbol with diemnsions attached to symbol origin placed on board% Q. B; R" C6 Q7 g2 G
956603 CONCEPT_HDL OTHER Part Manager "has stopped working" after changing a component2 ]5 g! Z( I5 y0 X# D1 \
956751 ALLEGRO_EDITOR ARTWORK Import Gerber command does not work correctly9 a- S: }2 p* B. ~1 S. ~ m
956847 PCB_LIBRARIAN METADATA PDV - Partdeveloper symbol to function linkage broken/changed in 16.5
# A1 z3 O, U( y956987 CAPTURE OTHER Find from "Search toolbar" doesn't gives complete results3 I" m# H) C& p0 r: r
956996 CONCEPT_HDL INFRA Correction to ERROR(SPCODD-7): Following Primitive instance causes CM to empty
, `2 L1 x. L3 Y% j: d4 H) }+ T! l957009 CAPTURE NETLIST_OTHER Problem getting database property in mentor PADS PCB netlist
, d% ^. x1 Q4 S# [: ], a0 N/ q% |957137 APD DXF_IF DXF out command dose not work correctly.
, s9 v+ x: [6 q( \/ M" `2 `957167 APD GRAPHICS Highlighting for Static shape with display_nohilitefont environment variable.
% V. S* G! u# ^3 K% `957232 SIG_INTEGRITY OTHER Allegro crash during Model Assignment.; t: ^9 \5 n! l0 Q) f8 A
957267 CONCEPT_HDL INFRA Packager Error after Import Design* V3 X$ f3 n- h
957866 SIP_LAYOUT DATABASE Cavity outline is not getting deleted from symbol file
1 p$ u: p) k9 _2 i8 Z9 @958010 ALLEGRO_EDITOR REPORTS Wants the ability to extract "Batch" reports from Partition ".dpf" files.; b0 P& |1 l1 O" {0 R4 X/ \
958252 ALLEGRO_EDITOR TESTPREP Resequence testprep with the option - Delete probes too close crashes the design
# j; X" }! E* e4 D1 v. @958253 ALLEGRO_EDITOR REPORTS Shape did not have thermal relief connected to pin but unrouted nets still shows zero.2 z; T" w2 n9 _9 Z. X& ~
958433 ALLEGRO_EDITOR DRC_CONSTR False embedded component DRCs
7 ^3 a3 t# h% Y. Z/ ?8 b958753 ALLEGRO_EDITOR SHAPE Dynamic shape is getting corrupted in 16.5
' q( A3 f, m9 e" s1 a) L8 `959011 ALLEGRO_EDITOR OTHER copy problem of via and cline8 J/ }- f% P8 ~, p6 w6 F
959101 ALLEGRO_EDITOR EXTRACT Using extracta with excluding Thermal reliefs& L' r3 b# q+ B2 B
959253 CONCEPT_HDL INFRA Design will not open
# u$ a* x) ?7 p" q959299 APD MODULES Getting ERROR(SPMHDB-279) when trying to update modules placed on the Top side/ v5 h$ M- n. J3 x) Q# i
959884 CONCEPT_HDL INFRA Design Uprev/concept2cm crashes with Application Error/Out of Memory Error.
% h& R0 z7 H% _8 U- {959909 ALLEGRO_EDITOR SCHEM_FTB Site level propflow.txt file is ignored property is transferred
% Z) s$ _) |6 t( j2 `5 }960067 SIP_LAYOUT PLATING_BAR Creation of plating bar removes "NODRC_ETCH_OUTSIDE_KEEPIN" property from the clines.
3 v6 u0 C9 S- i/ n. n# `960126 SIG_EXPLORER EXTRACTTOP Allegro PCB SI license is used automatically at Topology Extraction of Allegro Physical Viewer.
9 ^4 {. e @$ c+ K/ c1 @/ j, s960143 SIG_INTEGRITY GEOMETRY_EXTRACT Running simulation in Bus sim happened crash while enable Coulpled Via model to S parameter
5 L. H+ A; W5 U5 ^' J, K961349 CONCEPT_HDL HDLDIRECT Motorola designs have broken connectivity compared to 16.3
9 q! O0 \ o. y, X+ f9 X961816 ALLEGRO_EDITOR INTERFACES Normal Export > DXF fails and offsets the pins of the BGA symbol
4 ^' G1 h# V- L962519 SIP_LAYOUT WIREBOND Align option doesn't work for wb_tackpoint fingers, p9 v. l4 U1 Q& R( n' H3 M+ T
& {+ x* L" s/ O% gDATE: 11-30-2011 HOTFIX VERSION: 012: a& }/ P1 v/ J2 w6 n; Y
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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959581 CAPTURE NETLIST_OTHER PCB Footprint is getting replaced by VALUE in OTHER netlist formats
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DATE: 11-18-2011 HOTFIX VERSION: 011
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CCRID PRODUCT PRODUCTLEVEL2 TITLE: `+ H2 J* Q7 V J$ a
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735439 PCB_LIBRARIAN CORE PDV Moving line-dot pinshapes by arrow keys breaks the pinshape8 g( s7 w" @) a$ v$ @: t
894815 CONCEPT_HDL COMP_BROWSER Why does genlibmetadata command give 'Aborted $PROG' Message?% ]0 p& d& n, P- [3 q* y- m' m
903073 ADW COMPONENT_BROWSE datasheetl_url directive should support a display string for URL
8 N) P% w3 A W p909919 CONCEPT_HDL OTHER Why is the PublishPDF UNIX command line looking for "true" script?
$ E& n2 e) {( }! i k& I911561 CAPTURE CORRUPT_DESIGN Capture crashes on trying to save the design.
! C% A7 i" e. \0 }2 R919579 CAPTURE PRINT/PLOT/OUTPU Print mode be selected based on schematic mode/ ]* T% \7 A. I- ]2 ^
921247 CONCEPT_HDL COMP_BROWSER genlibmetadata.bat file does not have err defined+ f, X7 n9 F" U( F$ `2 s
925182 CAPTURE PROJECT_MANAGER ENH: Feature to run update cache on all the parts in design cache at once.
4 i! c& t5 F( O; D926858 CONCEPT_HDL CORE Usability- Modify Component dialog forces user to do 'Reset Filters' to see other ppt rows2 o! d5 r9 P4 g* W. N5 k+ X
927657 CAPTURE NETGROUPS Enhancement: Placement of netgroup definitions under design cache list
! _/ ^: X; d* _934684 ALLEGRO_EDITOR MANUFACT The relation between the linear dimension and the symbol breaks.4 K; }" h) d; K$ e; ]9 B7 T
935836 SCM SCHGEN ASA crashes when generating Flat Document Schematic
6 L# _4 Q) J# K" I2 I937165 SCM SCHGEN Can't generate Schematic
/ S5 l9 B, P, z, I \4 y% [* D( m& f937292 CAPTURE GENERAL Memory usage keeps on growing and finally gets exhausted while search
/ R9 _6 e" P% m. n1 T' n937322 CONCEPT_HDL CORE Master.tag file alters the sequence of the files and Genview fails
( Z9 P+ v+ q$ M' r, R3 q$ I! x939135 CONCEPT_HDL CORE Unable to uprev a 16.3 Design to 16.5 with DEHDL-L License1 ?5 w! z! a6 P6 X1 D. w
940373 CAPTURE TCL_INTERFACE Enhancement: TCL command to add nets to Netgroup
8 K% Y6 a: s }+ u- ~2 V940547 TDA CORE ERROR(SPDWSD-69): highspeed cannot be checked in$ P/ g3 |6 k6 }* k) h Q! ~
940607 SIG_EXPLORER OTHER Inconsistancy in License usage for opening sigxp -orcad, R$ I; n! H4 w8 p* r$ l, u
940790 F2B PACKAGERXL User doesn't want to display pin numbers after Export Physical 16.5.
+ P* {/ R4 u, ~6 j3 P940944 SIG_EXPLORER OTHER Inconsistant license usage while opening Orcad PCB SI using allegro -sq -orcad and allegro -sq
6 t% }6 N) V8 X& U4 x* I+ ^941354 CAPTURE NETGROUPS Enhancement: Option to rename the unnamed NetGroups* K8 p4 X' C3 W/ ]: F- s: i
941455 ALLEGRO_EDITOR MANUFACT The Dimensioned mechanical symbol when placed in the board does not show all the dimensions.$ h* p5 L* B: c5 j2 O; K9 e/ B
941863 ALLEGRO_EDITOR EDIT_ETCH Different behavior of design in v16_3 & v16_5 when add connect is executed on a segment thru script" C b3 c" x$ K- t) Z) M% g: M
941881 CONCEPT_HDL COMP_BROWSER How can I suppress the dialog from universalbrowser -genlibindex?" X) A: k$ N/ K% o# [8 U1 C2 s
942474 CAPTURE NETGROUPS NetGroup member type of last added member must be remembered by Capture
q+ F7 R4 [4 p# t1 {942522 CAPTURE GEN_BOM Export in excel check mark doesn't invoked BOM in Excel' T. o$ I- [8 R; v
942557 PCB_LIBRARIAN EXPORT_OTHER PDV Export to Capture crash5 m5 C5 ` s( m+ V$ u6 R& m' V
942569 ALLEGRO_EDITOR MANUFACT Dimension move and change text deletes leaderless balloon
e4 b/ \& p9 I$ n6 z) z, N! b942573 ALLEGRO_EDITOR MANUFACT Balloon type parameter has no effect on leaderless balloon. e, E3 k: B6 t7 s* y
942613 CONCEPT_HDL CORE Genview supports only SCHEMATIC/SYMBOL/VERILOG/VHDL views as input type. .xcon not recongnised
/ k5 p& s+ b$ S& `943032 SCM OTHER ASA is not passing the correct reuse_module name to Allegro PCB layout.
& e, H: _& U9 Z! ~/ m943401 CAPTURE NETGROUPS Alphabetical ordering of NetGroups in Place NetGroup' t, t. b6 M+ z5 @, ~ |' u$ V$ @
944006 ALLEGRO_EDITOR EDIT_ETCH Vias added to shapes behave differently
! k, @, c& d" m9 u) X5 U, J% R944367 CONCEPT_HDL OTHER Too late to do Model Assingment in conceptHDL 16.5
: A3 @/ n2 T6 q8 G5 h" w% v+ X944788 ALLEGRO_EDITOR GRAPHICS Oblong Pad shows unexpected lines
6 R8 D5 V' }8 U: p( K% x945221 CONSTRAINT_MGR RETAIN_CNS CM Conflict Resolution fails on more complex designs using ECSets and constraints
7 m2 o4 E( S2 I. f5 s. f% p+ X8 i946270 ALLEGRO_EDITOR PLACEMENT The Rotation Type was changed to "Absoute" if the "iangle 90" use at placementedit mode of spb16.5
1 e7 ~% h. d: |5 E946350 F2B DESIGNVARI Variant Editor rename function removes all components
4 S+ Y5 H( R* `' P5 A" q# l5 D$ V5 a946380 F2B DESIGNVARI Some VARIANTX properties are hard some soft - why?4 G& o7 H9 h, K7 O ~6 q* \
946419 SIG_INTEGRITY SIMULATION Cannot select component on BoardModel for controller in bus setup form6 o; v2 C- W% g/ G( G5 c M" R$ {( R/ ^
946458 SCM SCHGEN Schematic generator adding an unnecessary page- j! \8 x. D( J; S# j2 \
947667 ALLEGRO_EDITOR PADS_IN Need support for PADS-POWERPCB-V9.3-BASIC/ K. \ R3 d: ^/ w8 M4 n
947789 ALLEGRO_EDITOR MENTOR mbs2brd crashes during translation on the attached design.
7 Y' l$ @/ n9 G1 A! \1 P* x& c948110 CONCEPT_HDL CONSTRAINT_MGR Concept HDL craches when opening SigXP from CM. _- v% X8 T- n; a9 ]" g
950970 ALLEGRO_EDITOR MANUFACT Unable to generate artwork, dbdoctor fails to fix errors.: I# l' G; o; a5 n: ?
951901 ALLEGRO_EDITOR EDIT_ETCH In 16.5 add connect to same net is shoved- j& O! A+ R! B& `9 c) W$ m( ~
951919 ALLEGRO_EDITOR OTHER Exported package symbol soldermask and pastemask padstack locations not the same as original
- J* }! `% D4 Z7 a6 Y+ H) A951926 CONSTRAINT_MGR OTHER What is MaestroNotifyNotSetReport.txt file?
9 b7 Z# r6 S6 i5 N T# U( X5 Z951939 F2B PACKAGERXL Uprev to 16.5 is changing refdes for some pages
q8 f: b# [) V; H% K: ~1 h: p951983 CONCEPT_HDL INFRA Problems converting an Allegro design from 16.3 to 16.5
; Y6 l& L" e+ K$ [ W; Z- m) r9 S952057 SCM PACKAGER Export Physical does not works correctly from SCM$ P/ t2 i! A& M8 _9 J8 v
952217 ALLEGRO_EDITOR GRAPHICS crash when opening 3d viewer in PCB Editor) p& D; C5 `" [( `1 B7 W
952634 CONCEPT_HDL CHECKPLUS Checkplus logical rule fails on a design which packages fine in 16.5
. m1 w/ ?/ e4 t4 F953018 APD REPORTS Shape affects Package Report result.9 f) A" o' N! Q; b5 |& ]
953337 ALLEGRO_EDITOR OTHER Allow netname and padstack names to be visible for testpoint vias when viewed in Allegro PDF Publisher.
2 Z7 E! e6 r1 |8 c( r9 Z) Q) j953827 ALLEGRO_EDITOR EDIT_ETCH Snake Breakout function crashed Allegro
% P7 ]4 [: z6 g0 ~953918 GRE CORE GRE cannot route second and third row of pad in die symbol.
6 a3 U8 g' t+ h954055 CONCEPT_HDL CREFER Crefer fails with UNC install path
]4 o/ t# b7 ?# S$ | M954920 SIG_INTEGRITY CIRCUIT_BUILDER Each neighbor crosstalk simulation crashes or returns blank report
$ H/ j6 T! j4 W2 X2 E3 H2 u2 h$ v- }' c$ j: [4 j
DATE: 11-7-2011 HOTFIX VERSION: 010) q/ g' x5 w! E/ V. _
===================================================================================================================================
% _4 g3 I4 V2 L( P! R( S- wCCRID PRODUCT PRODUCTLEVEL2 TITLE9 I2 T% @/ ?1 T3 H6 E
===================================================================================================================================
6 I9 Q; D; X9 `+ H658866 ALLEGRO_EDITOR EDIT_ETCH enhancement option - so that Sliding a via inside a pad does not create a cline: s5 h, o" q. w4 G$ V* j' {
928624 ALLEGRO_EDITOR GRAPHICS Layer visibility control for 3D Viewer3 s6 u [" Y/ `* D, V/ ^0 l
934991 SPECCTRA LICENSING Specctra_adv option is not working correctly for PA3100 plus PS3500 license in v16.5 tiering profile
+ @% L% A' R2 j9 Y5 D938073 ALLEGRO_EDITOR PLOTTING Plot Page size A0 and A1 with problem* ]! ]" @$ {2 E2 g# a
938128 ALLEGRO_EDITOR DRC_CONSTR DRC changes when do update DRC. p" t+ m7 Z% @
938648 ALLEGRO_EDITOR GRAPHICS Enh - Requesting a way such that Package keepout appears transparent in 3D Viewer
- m# P. w1 S8 l: i8 Z940518 SIP_LAYOUT SYMB_EDIT_APPMOD Swap pins command doesn't complete# y/ F+ d. b5 R0 E) h# J
941426 CONCEPT_HDL COPY_PROJECT Copy Project fails - Updating opf view This can't happen!
( l% O5 t1 H- v941499 ALLEGRO_EDITOR DRAFTING BUG imit Tolerance isnot working for Dimensioning/ [% E3 j7 w9 M9 i9 Y' p J
941814 CONCEPT_HDL CREFER CreferHDL crashes during ScheGen
2 {5 p6 }3 R$ Y* Q942914 SIG_INTEGRITY OTHER ZAxis delay calculation% q+ h9 F! x+ y
943053 ALLEGRO_EDITOR SHAPE Modifying the Board Outline shape will cause the tool to crash6 D8 w8 V: Q2 A% w, T" Z
945321 SIP_LAYOUT EXPORT_DATA generation of a xml file from cdnsip for shrunken die9 ]6 o" u6 e' R+ J
945350 ALLEGRO_EDITOR SHAPE iPick does not work on shape boundary edit.
, _; z% u2 j. U' r6 J; W, C945449 APD SKILL When they create a new menu entry with skill APD crashes with next menu selection.
2 H* t9 X& o; d" c9 e; w946390 ALLEGRO_EDITOR DRAFTING refresh_symbol crash when trying to refresh mech sym that has dimensions5 ~9 [, W( N. B7 c4 [0 {
946401 APD EXPORT_DATA stream out gdsII results in shorting of PWR/GND nets due to elongated etch
- R1 k3 {+ v7 M7 a. ~946819 SIP_LAYOUT DEGASSING Shape degass command3 q' c- a0 o, b$ h; ^
946869 ALLEGRO_EDITOR OTHER Allegro PDF arc representation needs cleaned up
2 H1 p" \. X; @6 ~947230 ALLEGRO_EDITOR SKILL Skill execution crash Allegro 16.5 but work correctly with Allegro 16.3; ~' x1 C% v7 y( v( j( P/ ?
947603 ALLEGRO_EDITOR OTHER Component Properties (Default or User Defined) not transferred to PDF file
$ b' ?+ |& C7 G! N950995 SIG_INTEGRITY OTHER Netrev fatal error when importing logic" ?5 s) w, f; k/ ^ \+ n1 K, z
951123 ALLEGRO_EDITOR INTERFACES IPC fails to output drill hole info in columns 33-37! I. B, Y, D( T) S
951557 CONCEPT_HDL CORE Cannot create the entity folder for old plumbing symbol
1 ~; Q9 O" n8 L! V0 n" Q; x/ \) E* z0 b
DATE: 10-26-2011 HOTFIX VERSION: 009, ]) y: @- z5 _7 {2 |" _: O, @
===================================================================================================================================" ~! y; U6 ~* \2 {2 _+ ?
CCRID PRODUCT PRODUCTLEVEL2 TITLE0 [' d* m' S. H. p
===================================================================================================================================
- e: N9 g/ k& `' f$ T7 E945788 CONCEPT_HDL CORE Some component properties on the parts are incorrectly changed after Import Sheet% T& l" Z% E. ?& U; c9 E
945789 ADW LRM Some component instances are not updated by LRM even though cache ptf is updated from reference
/ d5 D( c" r/ N: ?% H* `1 P9 d5 A- ~) [: j/ Q2 }$ ?
DATE: 10-21-2011 HOTFIX VERSION: 0086 F; b& Q! S1 j" p1 Z" G, j% L1 f
===================================================================================================================================( f7 N' H9 _$ B# t% ?# I
CCRID PRODUCT PRODUCTLEVEL2 TITLE
: o. {. K( m5 X5 ]& {===================================================================================================================================
; }7 b. M# o" \/ M S906827 ALLEGRO_EDITOR DATABASE Logic > Parts logic does not work correctly.
, L5 _2 F5 G- F, L. p# p% x923346 CONCEPT_HDL CORE Not able to move the reference designators inside hierarchal blocks after uprev to 16.5
$ N$ O! Z; E+ B0 z' c" \0 z5 q926347 ADW COMPONENT_BROWSE Usability- Libflow Part check in comment should end up in Comments attribute for UCB/Designer to see it) K8 ~: m% E, r- Y
929348 F2B BOM Warning 007: Invalid output file path name+ R- _: e! t9 R8 B
929777 CONCEPT_HDL OTHER Component Revision Manager gives internal error* r$ D1 E3 ^0 `5 O0 |
930783 CONCEPT_HDL CORE Painting with groups with default colors
, d v L) |" u0 ^936748 ALLEGRO_EDITOR INTERACTIV "Unplace Component" menu inconsistent between General Edit and Placement Edit Mode.- h @3 x9 W7 |$ _
938143 ALLEGRO_EDITOR CREATE_SYM Why is this Extra Property 'ECSET_MAPPING_ERROR
- s& V) L3 r4 k6 ^938281 SIP_RF OTHER export_chips creating bad data when symbol is split and contains V- V+ pins
: n' _: W, Z' v$ r% Y/ v: E938812 ALLEGRO_EDITOR SYMBOL Cannot create a BSM with this DRA, errors out but does not state a reason.
7 Y7 M J' b$ ^5 A/ Q939075 CAPTURE TCL_INTERFACE Texts are getting garbled in command window) E& W: G; V# v3 G/ E+ T
939193 F2B PACKAGERXL ERROR(SPCODD-439): Connectivity server is unable to load the design.! l0 ^/ Q* h& Q
939199 CONCEPT_HDL DOC "Retain electrical constraint on net" mismatch between schematic (YES) and design (NO)
; @8 L/ h% g" P* S& L6 `( Q f939346 ALLEGRO_EDITOR SHAPE Shape disappears when updating with variable shape_rki_autoclip set.
0 C7 d T% B: a C( ^2 x G939901 CONCEPT_HDL INFRA NET_SPACING_TYPE shows �?� on lower hierarchy level nets after Upreving to 16.5 version.
; P: g+ y7 ?; g3 N) Z939918 PSPICE PROBE Print > Preview for output file causes Pspice crash.
$ q! L. H( l0 \" k940217 CONCEPT_HDL COMP_BROWSER UCB reports 'No Symbol found for the part'6 K& F' [6 ], w
940835 CONCEPT_HDL INFRA Desing package different after uprev to 16.5 where comp instance propeties are lost lost. Q) K/ {3 O# I$ w% [
941125 ALLEGRO_EDITOR DATABASE Performance advisor doesn't skip non plated slot padstacks8 h4 M) J! r9 Z2 b0 v
941876 SIG_INTEGRITY OTHER Illegal model name cause pxl fail in 16.3! N* Z; e, L+ I" y5 j5 F: D5 e# Z
942210 SCM OTHER Is the Project File argument is being correctly passed?( `& _+ h& ~' u' l j7 Y! W
942274 CAPTURE PROJECT_MANAGER Crash on renaming a Design Cache part in Project Manage after doing replace cache
% X5 R% m4 o0 q# A# l' Y$ n: q1 y5 o/ x9 j942839 ALLEGRO_EDITOR GRAPHICS Graphics Issue- Pads are not visible
" Z! n' c8 y; L$ f943055 ALLEGRO_EDITOR SKILL axlDBCreatePropDictEntry causes application to crash( r% T: f$ A3 M) P) t; v3 A
/ x3 M) w/ W. D5 I @
DATE: 10-21-2011 HOTFIX VERSION: 007
9 F, V, ?6 x" S$ p% r! U5 w===================================================================================================================================- \1 D2 }6 Z5 {& n B
CCRID PRODUCT PRODUCTLEVEL2 TITLE
6 _( t% d c0 l. g===================================================================================================================================
3 A, X( n7 E0 N841096 APD WIREBOND Function required which to check wire not in die pad center.
( P5 s' I& Y' ]- h903263 CAPTURE SCHEMATIC_EDITOR ENH: Selecting parent netgroup must select the underlying netgroup bits.
8 w% M) c$ w% o906692 ADW LRM LRM window is always in front when opening a project/ w) r+ M" b& I* t
912942 APD WIREBOND constraint driven wire bonding
- C$ D1 \, `. M7 y% u$ X912951 CONCEPT_HDL CONSTRAINT_MGR Need to manage temporary files on Linux systems
+ e. Z# M6 V+ X6 \) G% M* x1 h# q2 U915178 SIP_LAYOUT DIE_STACK_EDITOR Die Pad names changing when updating Die in a design% F9 h# [; ]% G7 O. m8 s" J( x
917887 PCB_LIBRARIAN VERIFICATION Part should not be released if the alt_symbols has errors
2 G4 s- y. K% W7 V923315 SIG_INTEGRITY GEOMETRY_EXTRACT crosstalk simulation fails with TMP popup failure1 {/ o) `8 y2 B! b) D
927382 CONCEPT_HDL CHECKPLUS 'Verify Symbol' forces the use of 'Concept_HDL_Studio' license' b2 D/ p+ a' d* V8 T
927664 CONCEPT_HDL CONSTRAINT_MGR Internal Error disposeipsp
3 ^1 o3 O+ ]9 l: Q+ @930152 CAPTURE NETGROUPS Scalar net names when being connected to net group overlap when connections are made one by one9 J8 D) }8 c, ]# ]8 Y' u' M( f
930180 CIS LINK_DATABASE_PA Visible property position on schematic get reset on "link database part" operation, H+ |( [5 a4 Y# x% j( p) c# d6 |
930188 CAPTURE DATABASE Capture 16.5 crashes in being re-invoked.2 O$ a/ f q. R( b: Y7 K; H! [3 o
930541 CAPTURE NETGROUPS NETGROUP element renaming doesn' renames the associated net ?
, H" h B1 m3 L% V930866 PDN_ANALYSIS SETUP OrCAD PCB SI Session crashes when we open PDN Analysis with "OrCAD PCB SI" license.% u+ ]3 l) V0 b/ {: x4 \
930926 ALLEGRO_EDITOR GRAPHICS Via and Holes not visible eventhough set to Visible in Color form
U$ {" I V+ ^' U$ b+ H' C5 W" a% O931274 ALLEGRO_EDITOR DRC_CONSTR Negative Plane Islands waived DRCs reappear after performing update DRC.& u O- x% m4 H t4 s4 M0 O
932091 CONCEPT_HDL CORE Prop attached to SIG_NAME property5 P% z! m' P( q: g
932255 ALLEGRO_EDITOR GRAPHICS Change in Zoom level makes arc segment to disappear q. o0 K/ x* J, o$ I% o5 D' e9 r
932292 ADW LRM LRM crashes during Update operation on a customer design
5 [$ h# ?" X6 ?9 o& K. Y932639 SIG_INTEGRITY OTHER Add Connect command hangs for about 14 seconds and then returns.
- d/ U# M3 `/ R; ]932704 APD DEGASSING Shape > Degass never finishes on large GND plane( P4 q, M. U# `
932871 APD GRAPHICS could not see cursor as infinite/ n2 q" k a2 ~2 E5 \" e
932882 CAPTURE SCHEMATIC_EDITOR Capture crash with FIND command - ISR05
1 V: Y! f- u2 E# o932969 CONCEPT_HDL CORE ConceptHDL crashes when you save the design in 165 > hotfix #05
0 p) y2 H* Y$ B933024 CAPTURE NETGROUPS Naming restrictions for NetGroup members0 ]( @9 k' q9 {' y7 s0 U+ I
933145 F2B PACKAGERXL Add Subdesign list is truncated in Force SubDesign Design Name pulldown* b' O( p) ], |) Q: E
933214 APD ARTWORK Film area report is larger when fillets are removed ?9 _% n7 r- D
933356 CONCEPT_HDL CORE Net prop display size become 0 if it was attached to SIG_NAME prop.5 U5 V, e& @" |
933532 ALLEGRO_EDITOR COLOR Bad color assign and initialisation during creation of new subclass, k, E% m3 {% j/ x) L, P) l
933549 ALLEGRO_EDITOR OTHER Chart text missing in export PDF file.
& T, E% Y( n2 f* h% k# [7 r934008 ALLEGRO_EDITOR REFRESH refresh symbol updates symbol text to some unexpected values5 F1 ^" |+ b. r, @
934031 ALLEGRO_EDITOR DRC_CONSTR Bug : Update DRC removes Waived status for some DRCs2 b# k" t8 H8 R4 a- d; v# g. g1 f8 p
934087 CONCEPT_HDL CORE Opening DEHDL and Model Assignment before design loads causes crash
% T* S8 l9 w$ ?3 {/ f934396 CAPTURE SCHEMATIC_EDITOR Find operation is not searching power symbols with + or - signs.3 L L0 L8 R6 o& p/ g4 A
934533 F2B DESIGNVARI The Variant Editor errors are not written to the variants.lst file
: B$ \% P* B* t934811 SIP_LAYOUT UI_FORMS CDNSIP should not hang if contraction value in z-copy command is out-of-bound/ b) @: }8 H3 w% f
934909 SCM UI Require support for running script on loading a design in SCM
- J; n R9 h8 W( [& O, B+ {$ x; d935632 CAPTURE SCHEMATIC_EDITOR SHIFT+Mouse wheel scroll(horizontal) of page is not working in Auto Wire Mode.+ P# j+ k0 z) k2 L$ A# H3 L, i, p% \) _
935794 ALLEGRO_EDITOR SHAPE BUG:Shape not filled in 16.5 but it does in 16.3
4 k, n2 w: b" {# E. I1 v8 {& _935988 ALLEGRO_EDITOR INTERFACES When attempting to downrev this 16.5 design to 16.3 the tool will crash/ F+ l+ I/ Y6 a0 a. I
936056 ALLEGRO_EDITOR DRC_CONSTR place_manual crash while moving mirrrored symbol
9 L6 g/ |* C' `7 u936098 ALLEGRO_EDITOR SKILL axlDBCreateCloseShape does not work correctly.2 v. c) S2 _7 a9 z$ D0 b ~
936212 ALLEGRO_EDITOR INTERFACES DXF not created if Blocks created for Symbol and padstack* C5 T5 J! T% K S/ j* M; c
936797 CONCEPT_HDL COPY_PROJECT Copy Project crash
; q; l, b$ I6 Z7 u# J; s, Z) g; Y936808 ALLEGRO_EDITOR DATABASE Allegro crash replace mechanical symbol* |4 E) f, `8 Q! ]* Z' e1 X9 K! _
936853 CONCEPT_HDL CONSTRAINT_MGR DEHDL crashes when trying to extract net from CM {, [4 ?$ E6 i8 k( F7 f+ j
937087 CIS DESIGN_VARIANT Upreved design becomes very slow in Variant view mode. DELEET THE DESIGN AFTER RESOLVING THE ISSUE
+ B! j+ t, Z3 O% a, D' Q: d937173 CAPTURE OTHER Wrong license information "UNLICENSED" in Capture >> Help >> About8 Y2 D, O. V' O- \, `
937290 APD PLATING_BAR Plating Bar checks does not recognize connection made through etchback through shape.3 ?" R6 {+ O8 |9 W% \6 r/ H/ F
937411 ALLEGRO_EDITOR DATABASE downrev_library reading from one directory and writing to another hangs the command.$ Y' N1 Q( i5 n0 v
938235 SIP_LAYOUT STREAM_IF Die Orientation is not correct after importing a stream file. N0 m+ G( s' X' h8 U
938273 ALLEGRO_EDITOR OTHER PDF export is is not opening viewer with ads_sdlog variable set0 f) e. x! q7 b4 k2 P( I' L' r0 n
, W& h: q, K# f0 ?! ^0 G9 O
DATE: 09-16-2011 HOTFIX VERSION: 006
" o( |: n; q) |: ?6 v3 P. a, [+ s===================================================================================================================================) ^% d5 ^- q/ X" A
CCRID PRODUCT PRODUCTLEVEL2 TITLE
; d# } h! U% Q3 w; P' D2 S===================================================================================================================================: ^0 p* E n9 P3 [5 g7 d
820131 CONCEPT_HDL OTHER Moving symbols to other page will make Allegro components unplaced because logical_path changed.; W0 Q# e [; S* B
863860 CONSTRAINT_MGR SCHEM_FTB CM should display or Local Interface and Global nets to help defining low level constraints! I/ Q2 S {' @) P- y0 N& R ?
919822 TDA CORE Cannot configure LDAP to only list the login name
( D5 }3 a* X" ]) O3 i4 [2 @922907 ADW TDA 搇ast_callout_file� directive in the BOM section is empty causes tda for show Access Denied error
3 E9 L% z7 x4 ?1 |6 ^* F" C924322 ADW COMPONENT_BROWSE Random - No instance properties are added on Add To Design (RMB or double click) from Search Results5 g# k+ r( a& t7 [9 d4 U* l
924448 F2B DESIGNVARI Design does not complete variant annotation
: J+ x! W1 \3 Z& {7 ^& M2 I% P" t; }925584 CONSTRAINT_MGR SCHEM_FTB 16.3 upreved Design passes the SLOT/Function Properties to PCB
2 c, _$ }% Z% @# U927102 ALLEGRO_EDITOR OTHER Question of Conductor Detailed Length Report
4 r3 Q" G% ?/ z: q927104 F2B DESIGNVARI Tools > Annotate variants crashes when there are ASCII characters in the property values1 `4 G" L+ l; w$ L9 N1 b
927142 F2B DESIGNVARI Incorrect pop up asking while executing variant editor from the command line9 z5 T7 H4 K8 p. } W
927166 CAPTURE NETLIST_ALLEGRO ENH: Feature like NET_SHORT in Capture Allegro flow which allows user to short 2 or more power nets* W1 n$ y: Y9 z: _$ h! l4 v
927410 ALLEGRO_EDITOR DATABASE ERROR(SPMHUT-144): Illegal arc specification error when Run DBDoctor
% _ @- a$ v( G3 ^1 k9 Z927475 CONCEPT_HDL CORE About forcereset command of nconcepthdl
( f0 @$ m8 G* h" j+ J# n927498 CONCEPT_HDL CORE Pin_Name starting with minus causes incorrect behavior for $PN display
5 {! s2 \, r5 T+ \927608 ALLEGRO_EDITOR PADS_IN Import PADs fails with error message: Failed to close the Allegro database
: ^4 e/ U9 S( s" A9 L) c0 \* b+ V L1 k927637 SCM CONSTRAINT_MGR ASA crashes on change root and also performance is too slow.
# ]3 K5 k/ Y4 V0 d* y. ~928429 SIG_INTEGRITY OTHER Request - Package Wizard to work in PCB SI.
6 y8 T4 J5 p: w928483 ALLEGRO_EDITOR DRC_CONSTR Running Update DRC removes Via List DRC Error when via is actually not in the list
0 g4 {- i) F# {/ ^; N3 t3 q928738 PSPICE PROBE Y-axis grid settings for multiple plots" L) M. l6 j" X. B! T( K
928748 PSPICE PROBE Cursor width settings not saved
+ }' y2 q6 \8 r5 l: P9 d2 D3 e928779 CONCEPT_HDL CORE Error (1053) occurs on a copied part in SPB165 release
" w+ `: D) E: @" q- T. Q928838 CONCEPT_HDL CONSTRAINT_MGR ECSets not migrated in 16.5
, G- h1 r# K# V! X' R% e$ f928885 SIG_EXPLORER EXTRACTTOP PCB SI crashes when extracting a net from Probe
; l2 \6 i' K6 C$ O" D929284 CONCEPT_HDL ARCHIVER archive does not create a zip file5 h1 v& k0 g/ `; `) }
929542 SIP_LAYOUT DIE_ABSTRACT_IF net issue of multiple ports of co-design die in SiP
/ ]. t( x* k6 n) h929656 ALLEGRO_EDITOR PADS_IN PADS translation fails with Microsoft Visual C++ Runtime Library error# Y* Q n2 j1 x4 r' O
930063 ALLEGRO_EDITOR TESTPREP Test prep crash Allego when it can not create pin escape
( R8 g& A p: k: s930217 CAPTURE NETGROUPS Net aliases doen't gets assigend to bus bits if bus name is checked in NETGROUP.
1 y: S) }4 l% ~! B- {- }930355 SIP_LAYOUT WIREBOND about "wirebond add nonstandard" command
# A0 H/ e$ J J' U7 [, V5 a930607 APD OTHER Layer mapping information is reomved from Layer conversion file upon exporting DXF from board file.
) J! n" c- H: F) A1 i0 Q930646 ALLEGRO_EDITOR DRAFTING Bug - Adding Linear Dimenstion for ISO standard add the Angle information as well) S! }2 w/ I1 i) B+ n' I5 j
930894 CAPTURE TCL_INTERFACE PDF export doesn't creates property file if some symbols are used in page name/folder name
0 T! K' u% T* l) Z( e930944 ALLEGRO_EDITOR OTHER Setting variable 'appmode' equal to 'none' is not changing the Application Mode when reinvoked
' P- M7 t( D/ T& a. y: _4 U930978 ALLEGRO_EDITOR SCHEM_FTB 3rd party netin error - Pin is connected to net <netname> not reconnected no longer happens; M6 A! n! r5 J" s. ^/ r' k
931248 ALLEGRO_EDITOR DRC_CONSTR Match Group was removed if member nets became xnets.4 F3 @% W2 ]/ i& h8 b
931278 CONCEPT_HDL INFRA $PN gets copied when upreving design from 16.2 to 16.5 version/ p) I2 Q/ t) N; `. m. U/ o
931349 CONCEPT_HDL COMP_BROWSER DEHDL craches and corrupts connectivity file when using Modify command extensivly.
# c0 ~5 _) H& k6 w
- M& n# f4 b+ u3 G% F5 S/ \DATE: 08-31-2011 HOTFIX VERSION: 005
- M5 }2 B( y* p8 o2 ?; P, z7 o===================================================================================================================================
3 S. I6 D. T G2 P" @6 y" `! nCCRID PRODUCT PRODUCTLEVEL2 TITLE4 ^0 ]! e$ V M% S: Z7 C$ p
===================================================================================================================================, m/ m6 ^2 A+ k/ [. j9 Z. Y
825848 ALLEGRO_EDITOR SHAPE Shape not filled when edges from 2 RKO shapes touch around mouting hole
+ o$ |, t0 S& G' O# O, z837723 CAPTURE PROPERTY_EDITOR Occurrences of external design not related to current root should not show
- t# u2 p$ z9 G; H e8 b' R891079 CONCEPT_HDL CORE DEHDL crashes with large number of commands in Winodws mode- r; Q, P" \+ J5 a3 S! u) ?) Q$ Z
910908 SIG_EXPLORER OTHER Cannot open top if Tx AMI dll name contain more than 2 dot.8 e* M* [5 u8 n, V* K, C
914036 CAPTURE LIBRARY ENH: Option to delete a corrupted part from a library and leaving other parts intact in the library.
( }8 I4 a9 z7 _" F0 k- a) y2 n914679 ALLEGRO_EDITOR INTERACTIV Custom toolbars are not retained when switching between brd to dra and back to brd file using the File > Recent Designs
" p* ~# h4 @! Q. N914870 MODEL_INTEGRIT OTHER mergedml fails to merger 2 DML files from the model integrity$ Z& u- L; Z, y) T' t4 q1 f
915645 ALLEGRO_EDITOR MANUFACT Allow the user to place the cross-section chart at a desired location
* U; O2 b' J2 m- C3 ]915653 ALLEGRO_EDITOR INTERACTIV unable to delete non-etch shape
# {9 n8 K B' M6 N" g! H915711 ALLEGRO_EDITOR MANUFACT dimensioning tolerancing by limit not working
9 N* T7 w$ f' |1 e916321 CAPTURE GEN_BOM letter limitation in include file- q- T5 G( _( X
916907 CAPTURE SCHEMATICS 揂uto Connect to Bus� should place the wire through non-connectivity objects% d4 {% {4 ?; S a- k% A
920327 CONSTRAINT_MGR ANALYSIS The TotalEtchLength predicate in Constraint Manager does not work for a netclass with a bus.
; K' P! v- C2 r920753 ALLEGRO_EDITOR GRAPHICS If I confirm to padshape with zoom-in after install the s002 It was changed to wrong shape.
X0 P6 T& G- P: i921097 ALLEGRO_EDITOR GRAPHICS Padstack seen partail filled when Zoomed in even "static_shapes_fill_solid" is set+ D& Z, X! |, ?0 d/ P
921226 ALLEGRO_EDITOR DRAFTING Unable to select Package Geometry class when dimensioning in the symbol editor.
0 i, Y2 e( h: a* `# X921623 ALLEGRO_EDITOR GRAPHICS Bug : Symbol not visible when zoomed in 16.5 S002
, w# F" N* \9 d q921891 ALLEGRO_EDITOR DRAFTING dimensions are lost after downrev(ing) a SPB 16.5 design with associative dimensions
" G7 W) Y9 q4 _" j& V921937 ALLEGRO_EDITOR COLOR Padstacks with shape symbol are not showing correctly
" Z) m' C) c% ^ x$ O; J922066 CONSTRAINT_MGR ANALYSIS Custom measurement Actual not being cleared when layout changes.
) V5 F/ a! z* F, H, j; R! ]922117 PSPICE PROBE Label colors are not correct in Probe/ [6 H: t. U' \( j6 J/ a
922519 ALLEGRO_EDITOR SKILL add_bviaarray command fails for some clines but not all
0 W* F3 r0 Q8 o& o1 U9 l8 |923224 ALLEGRO_EDITOR GRAPHICS Thermal flash Display problem in Allegro v16.5 Hotfix S002
& c+ Y, B, s& A6 U7 H+ x! `6 q923286 CAPTURE DRC DRC markers not reported for undefined RefDes# n* a# d9 g8 y- F8 ]
923362 ALLEGRO_EDITOR PLOTTING Print to Postscript file not correct in 16.5" r: r: I% h- k6 p# Y. p1 T+ S
923416 ALLEGRO_EDITOR PAD_EDITOR Pad Designer crash on clicking on the Arrow before Soldermask_top% R) k/ F6 ]% L$ s3 o' A
923507 CONCEPT_HDL CONCEPT-PCBDW The function of Import Design in the SPB16.5 Design Entry HDL (for data of ADW15.5_S23 + SPB16.3)
! R A, W4 Y7 B0 y9 C5 \923910 CIS PART_MANAGER Copy & Paste operation from Part Manager copies properties only to first section of the part.3 p( A: J, S! I
923913 CAPTURE PROJECT_MANAGER Capture runs slow on attached design
4 n6 v# Z) c3 p4 c923937 CONCEPT_HDL CORE Back annotation time significantly increased with the metadata generation on
8 T! E8 i& \- l923949 ALLEGRO_EDITOR INTERFACES Incremental DXF_IN gives 'Invalid subclass' error
+ o! M+ n0 p* g4 Y924458 SCM OTHER Project > Export > Schematics crashes
1 m, q% @ N) h4 [1 Y924621 ALLEGRO_EDITOR SHAPE Dynamic shapes are disappearing upon updating them to smooth. O4 S2 ~& S% ^# ], I: O( I
925193 SIG_INTEGRITY FIELD_SOLVERS Diffential Impedance (DiffZ0) values computed in the layer stack-up is incorrect
# B7 ]: |3 ?+ B( [( f$ j$ f925195 ALLEGRO_EDITOR DRC_CONSTR Incorrect pin to shape DRC error0 X! I1 b, Z9 s" M* ]/ w
925338 CONCEPT_HDL CORE This application has requested the Runtime to terminate it in an unusual way
8 Y. I" p0 K$ q/ ~1 E925435 CAPTURE TCL_INTERFACE Capture crashes if 揝ave design as UPPERCASE� option is disabled.
R* ~& _- C$ w# \2 V925530 SIG_INTEGRITY OTHER Why the single line impedance value for Top and Bottom layers are different for this design?
: P% ^, W) I; X- i$ g9 C0 i' m925864 ALLEGRO_EDITOR DRAFTING Ability to add dimensioning to different CLASS/SUBCLASS
; N4 b0 b; Q6 w) v( G* \5 H925976 ALLEGRO_EDITOR MENTOR mbs2brd fails to import data
1 z: |7 w5 P4 l+ v9 u926409 SIP_LAYOUT DRAFTING Exporting a 16.5 design to 16.3 will cause the leader/dimesion lines to be removed.9 R% H+ s2 O# @* L- z
926443 CONCEPT_HDL CONSTRAINT_MGR In new 16.3 "035" ISR Concept2cm will crash with error.0 z M# S2 @( E; ~, ?6 k
926503 CAPTURE GENERAL Memory leak Capture/Pspice+ @4 b* W1 f4 ^- A9 I9 j" u
926553 CONCEPT_HDL CONSTRAINT_MGR CMGR ERROR There is no net in the Cset that has pins matching those in net 1 in the Xnet
# I, h% x0 E/ B926691 ALLEGRO_EDITOR OTHER Crash while Importing Technology File in CM, with Overwrite Constraints.
& K9 V7 K! E# U& ]* y/ J926887 CONSTRAINT_MGR CONCEPT_HDL Pin pairs lost after Export Physical4 ]1 {" k( b0 D" O8 j7 x
927159 CONCEPT_HDL CONSTRAINT_MGR Export Physical fails due to errors in ConCM.log when SIGNAL_MODEL injected property is ''
3 H4 u4 \( f, U% s* M9 Y4 ~8 G* d, T: x5 A' ]. u, L8 v% }
DATE: 08-19-2011 HOTFIX VERSION: 004
' o1 P8 P8 i' O/ c===================================================================================================================================) F4 _" E3 `& a" Z
CCRID PRODUCT PRODUCTLEVEL2 TITLE. s# b N2 r, n
===================================================================================================================================$ z& Y% v& h) p" g/ F( k# @
785417 CONCEPT_HDL COPY_PROJECT copyprojectui crashes with a Windows runtime error% m2 b& c& G" H. `+ t
851044 CAPTURE GEN_BOM "Export BOM report to Excel" does not appear in the Standard Bill of Material Window.* K& u# v+ F3 l0 { M
868216 PSPICE MODELEDITOR Encryption of subckt names, internal nodes, comments
6 q; E& G2 U) b- j870247 PSPICE SIMULATOR Encrypt a model and simulate it, info about inside nodes being dumped in the probe file1 ]+ R, X7 ^) S8 ~& W& X6 P
877091 CAPTURE SCHEMATICS Save JPEG, GIF, PNG and other image formats in the database in its compressed form) [& M4 e( |$ K' f
894059 CAPTURE OTHER Enhancement: Adding column in edit>browse>parts window- ]( w3 f# o, s; a3 |4 v9 m
895902 RF_PCB OTHER Alphanumerical allegro pin numbers are unusable in ADS 2009 Update 1/ i8 o" ]0 I: v# c
895919 RF_PCB OTHER Round trip Allegro to ADS to Allegro requirement
9 n5 B* p- V: M( l+ @903102 ALLEGRO_EDITOR OTHER Zcopy shape command for cline seems not to work correctly.
8 c9 b j) ?' Z# K) l905562 SIG_INTEGRITY SIGWAVE Noise margin seems not to be measured correctly with Eye Measure function.3 o; Y! v: {+ Z5 m
909469 SCM TABLE ASA crashes when opening project5 G/ a& U! g( C) M, \3 P
909595 APD LOGIC Inconsistency between export die text out and show element after pin swap" g b; `$ A+ Z( C2 z
911123 CONCEPT_HDL CORE 16.2 Design uprev to 16.5 fails with ERROR SPCOCD-152& Z/ L: v |3 K1 H. n
911569 CAPTURE EE_INTERSHEET_RE Q: Why is capture assigning incorrect Irefs in attacehd design ?. _$ ~4 q' \* g4 b
915657 ALLEGRO_EDITOR OTHER Allegro PDF Publisher Mirror capability; \& @+ P% v3 Z1 @
915755 CONCEPT_HDL CONSTRAINT_MGR Cannot view net in SigXP( O$ d. o- x6 Z! P# i
916062 CAPTURE GENERAL Auto Wire Crashes Capture+ ?- I; l- q, N/ |, d+ u) {" w; \: n
916820 F2B OTHER RF create netlist with problem, q5 m: e- m# {: |0 v. i
917967 ALLEGRO_EDITOR REFRESH Update symbol resets refdes location for bottom side components only.
: D2 W) I; B; {+ s2 l& i3 a919343 ALLEGRO_EDITOR PLACEMENT Place Manual is crashing the board file1 K& h$ ?/ v2 H2 o. u
919481 CONCEPT_HDL CHECKPLUS CheckPlus isGlobal function is not working# ]! |! r7 [6 F7 U
919510 CONCEPT_HDL PAGE_MGMT takes 10 min to insert page in DE HDL
7 N3 r" D: K2 {4 g919976 APD DATABASE Update Padstack to design crashed APD." G" V( j" w7 V. [+ y; O
920418 SIP_LAYOUT OTHER SiP enhancement to Auto Assign Pin Use to add ability to change the pin use definition
9 b( W+ T6 v/ r9 M6 b920420 SIP_LAYOUT LOGIC SiP enhancement to Logic Auto Assign Net to display a dialouge Auto Pin Use assignment should be run7 Q: H- s4 ~/ k( f7 g, I8 I% v" m
920712 ALLEGRO_EDITOR ARTWORK Program has encountered a problem ... error when creating artwork
2 z4 H% v R: j' S) D/ R% i920763 ALLEGRO_EDITOR ARTWORK Soldermask gerber missing thru-hole pins
- V0 j1 ?' W( q b9 H% L4 U) e+ Y920976 ALLEGRO_EDITOR GRAPHICS Question regarding the difference in the behavior of 3D Viewer w.r.t. height_min
9 S9 K$ Z6 b9 r# ^920993 ALLEGRO_EDITOR DRC_CONSTR Minimum Metal Spacing Error is detected on Same Net
& m$ V" u& q, d/ Z O) J; m921727 ALLEGRO_EDITOR DRC_CONSTR Pad Boundary causing P/P drc to adjacent symbol.& F+ ^* N0 h3 w; P% V- |' Z
922579 CONCEPT_HDL CORE Xcon file gets corrupted upon Save of Hierarchical design with Global nets tied to interface nets
2 Q# U3 G8 g! `' M922592 CONCEPT_HDL CORE DE-HDL does not report illegal connection when Global Net tied to interface net using an Port symbol and named5 h8 ~, ]/ x5 D- T* ?: A, y
922758 ALLEGRO_EDITOR DATABASE Allegro crashes while placing second mechanical symbol with route keepin3 `, F6 a) o7 _2 }/ E7 ~* J
922839 ALLEGRO_EDITOR DFA The DFA drc display is unstable.' k: W& D! o @% d' p2 A& c
923293 ALLEGRO_EDITOR INTERFACES File> Export> IDX is failing for this design while creating an empty error log.
. [ ?, \1 D+ o924772 ADW PCBCACHE Import Sheet is not bringing in Parts used in the source pages into target cache ptf+ {# R0 s; f; H/ \5 B9 R, a
! H, T* P5 w T7 I0 @" z; wDATE: 08-4-2011 HOTFIX VERSION: 003
+ y: U; E3 j$ G7 \) v% i& J: N" X===================================================================================================================================8 `2 U: D( P, R
CCRID PRODUCT PRODUCTLEVEL2 TITLE
( F9 o Q: x+ z7 _===================================================================================================================================
8 C: P! o! Q! l; H+ ^) m( h787414 CAPTURE PROPERTY_EDITOR Part value can抰 be moved on schematic if a part has been copied to a new design and not saved yet.
# v2 o, G7 X' K* z903898 PCB_LIBRARIAN GRAPHICAL_EDITOR PDV move symbol graphics and Undo causes corruption in graphics
1 Z- W+ K$ j) z, j8 A. n+ p9 W' I904287 ALLEGRO_EDITOR ARTWORK some cline with arc is missed, when creating artwork." s5 ^; l& `) b) y; ~4 Q0 \2 p. E0 h
904418 CHANNEL_ANALYS SIMULATION channel analysis sim does not give valid result# d0 [3 c0 x2 Y5 A' ^1 I3 ^
905777 SIG_INTEGRITY SIMULATION User gets popup message that halts an analysis until it is acknowledged8 Z; M3 ]. U& P& Q! V
906139 SIG_INTEGRITY OTHER Bus sim result were cleared at the next run even if no preference changed.
5 U( X' \8 V$ |0 q8 d908680 SIG_INTEGRITY OTHER Extra prop delay due to resistance
1 c5 P: u' G- U& H909583 ALLEGRO_EDITOR SKILL axlPolyOperation AND operation is not working correctly.% v! U3 t: ?7 j$ o% q" [# x
910315 ADW LRM Import Design with ADW causes partmgr and pxl errors( M' T6 d* p! f- F' N2 T* n: {
910689 CONCEPT_HDL CONSTRAINT_MGR NO_SWAP_COMP warning after uprev to 16.58 N$ j- K k& Z
911684 CONCEPT_HDL CONSTRAINT_MGR Attribute Definitions are incompatible for attribute 'HEADER'. when attempting to place in 16.5
2 K5 J: f: `- \912343 APD OTHER APD crash on trying to modify the padstack8 b0 ?. i3 ~1 P/ J2 l
912384 PCB_LIBRARIAN CORE PDV Symbol Editor often freezes when moving groups objects by arrow keys0 k! O# Z5 s `8 S
912853 APD OTHER Fillets lost when open in 16.3.
$ y3 y5 z+ b/ F, `913586 ALLEGRO_EDITOR ARTWORK Cannot create the drill figures in this design.! x" B5 i- j% e8 q* H5 W& z
914009 ALLEGRO_EDITOR DRC_CONSTR Diff impedance worksheet showing almost zero impedance for differential pair in attached testcase.
" V( Z u9 Y0 y% t914110 CONCEPT_HDL OTHER DEHDL 16.5 Uprev overides property values on hierachical blocks' K! F/ Z% A) J; q/ @) G
914264 F2B OTHER Cross Probing from DEHDL for global nets present inside block doesn抰 highlight in PCB Editor.: r6 p. }6 V+ S8 N: } e' V7 J1 `
914309 CONCEPT_HDL CORE 16.5 DEHDL crash on saving the user design7 m; c& ^! p$ T7 o
914558 ALLEGRO_EDITOR ARTWORK Gerber6x00 output creates unpainted niche in a shape4 t5 e( ?# r) ^ T4 F% f9 M
914633 ALLEGRO_EDITOR ARTWORK Artwork failing in v16.5 while the same design when downrev'd to 16.3 is working fine.
! r8 e4 l" d9 x; g914634 ALLEGRO_EDITOR SKILL IsThrough flag for a padstack is reset* M+ r. l3 G* _; O( M' C
914746 ALLEGRO_EDITOR DRC_CONSTR DRC Update repeats takes longer on each successive pass.
) l3 x) ]; a- N# I+ H$ i, t914962 ALLEGRO_EDITOR SHAPE Corruption with Shape filling2 C; x5 l8 w# o* z v9 \3 R
915583 CONCEPT_HDL CORE performance issues in 16.5 compared to 16.3
' }! w4 k2 E9 Y: R- v9 c! Q915630 PCB_LIBRARIAN OTHER Error when running SI Model Interface Comparison using IBIS models
: Q' `; E# k% D. q" ~5 V- y915742 CONCEPT_HDL HDLDIRECT I get a newgenasym error and crash when trying to save the symbol, {' r8 ~$ B7 ~7 E, U+ X+ ~8 h
916154 SCM NETLISTER scm crashes when exporting physical database to allegro5 z$ y) [% t6 g
916448 CAPTURE NETLIST_LAYOUT Capture 16.5 Layout netlist contains errors0 e( I* _' @: K) i: l
916462 ALLEGRO_EDITOR DATABASE Edit>Split_plane>create hangs Allgro PCB Editor: V" A1 }3 o: ^: r3 c
916469 ALLEGRO_EDITOR REPORTS One Unrouted pin does not show in Unconnected Pins Report" |4 Z" k% K$ g2 E7 b6 b0 K$ s
916495 ALLEGRO_EDITOR INTERACTIV Pick selects components from invisible (Off ) layer+ Y) L; {4 W* ]$ J
916889 CAPTURE NETGROUPS How to change unnamed net group name?& Q/ Q3 u H2 ]3 z: a
917002 ALLEGRO_EDITOR OTHER Allegro PDF Publisher creates extra circles not available on film
" B V* A7 x) @% F- s917434 APD OTHER Stream out GDSII has more pads in output data.8 g; G U9 g: i [1 d. t+ |! f" O: _: Q
917739 CONCEPT_HDL INFRA Global Net tied to port is getting split into 2 nets in 16.5, in 16.3 it is treated as a single net( Y9 X' @' `- T" j
918187 CONSTRAINT_MGR OTHER Missing acGetTotalEtchLength predicate. T' x) r) i1 a5 }8 \& |
918576 CAPTURE DRC Incorrect DRC is reported for visible power pins which are connected to power symbol
( s6 P% x G) B: [ S" o; [2 c+ g/ f3 W' M3 a8 H' ^- S+ Z
DATE: 07-24-2011 HOTFIX VERSION: 002' g+ W- p+ _! t6 l. V7 h! L d
===================================================================================================================================
( x y' K+ S5 g1 O* \+ [( U4 {CCRID PRODUCT PRODUCTLEVEL2 TITLE
6 o: ~) f, I& u0 Z- M! C===================================================================================================================================
1 I" x3 F. p* v$ p e) [$ z6 {527444 ALLEGRO_EDITOR EDIT_ETCH Slide command needs to be enhanced for same net spacings
; w9 E, ]. w7 q0 h583257 ALLEGRO_EDITOR EDIT_ETCH Add Connect and slide command needs to be enhanced for same net spacings.+ k9 W+ ^/ A) j. m- `7 E4 M1 F
592956 ALLEGRO_EDITOR EDIT_ETCH Same net traces will not push and/or shove each other.; M* D/ e& t7 D6 G3 L( h/ t
745285 ALLEGRO_EDITOR EDIT_ETCH Requesting a true "shove" in Route > Slide for Same net routing.
) Z2 K5 Y% w9 L3 h/ v5 A2 T773503 CAPTURE OTHER Doing "Mirror Horizontally" creates extra un-connects or extra junction dots in Capture V16.3.: L4 M3 S# Z( M, v
774270 F2B PACKAGERXL Require to ignore space in Pattern setting to prevent duplicated Refdes., g; F; W: A' h: Y) Q) g8 X% F+ t
799984 ALLEGRO_EDITOR INTERACTIV Enhance the Fix command to select just cline segs8 B$ q$ U$ n: f0 E0 e0 w5 O
809008 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".4 _% x& A2 O4 q# A: W* h9 y
810058 CAPTURE SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".# }6 E0 o: D0 z4 i9 L0 x% w1 [ s
821133 ALLEGRO_EDITOR MANUFACT Output artwork for pad data that are suppressed unconnected pads with Gerber 6x00 format" P0 }. a* u8 F' A% s4 @
831710 CAPTURE SCHEMATIC_EDITOR Capture adds extra junctions to design by itself
) ]% c; v6 o; w6 Y3 p/ X ?6 s/ |842410 ALLEGRO_EDITOR EDIT_ETCH Ability to slide with "Shove" for "Same Net" segments/vias.- Y! Q; J- k/ ~( h* r
854971 ALLEGRO_EDITOR INTERACTIV Capability to add cline segment in a temp group
" O! z, m+ N( i& n860772 ADW PCBCACHE Save Shopping Cart (pcbcache) is crashing component browser& e( G. _% Z3 s+ T( t1 x) ], k
867842 CAPTURE PROJECT_MANAGER Capture crash with 'Open File Location"
" n' k# H# W2 R8 i: W" S+ D868306 CAPTURE CONNECTIVITY mirror vertically removes junction creates extra nets, K/ S0 ~+ E6 v4 ]6 `) x: y* i
882677 EMI RULE_CHECK bypass_plane_split fail if BYPASS_XXXX_EFFECT_DISTANCE( x+ x8 d9 o* M1 L2 b# t" M t
891439 ALLEGRO_EDITOR INTERACTIV moving cline segments
' e8 r, `$ r. V893544 ALLEGRO_EDITOR INTERFACES IPC-D-356A netlist issue with BB vias.! S& i- S, }0 y7 B. D9 u
893765 ALLEGRO_EDITOR PARTITION Mail command not sending out email on Linux platforms.
- W. D, _/ n) \$ S' \: U894390 SIP_LAYOUT EXPORT_DATA Generate all balls in the xml file for export to EDI's readPackage command
! Y) x4 Q6 s9 d( [+ n: o$ n895933 APD DATABASE Update Symbol shifts the center of the Dynamic Fillet and creating DRCs- B' A0 L1 {0 e/ j7 R$ I: d) [5 y
896598 ALLEGRO_EDITOR PLACEMENT error message is misleading2 Y# t2 R0 n7 Y2 o6 `# {' E; Z
897196 CIS LINK_DATABASE_PA Schematic Contents are not shown in CIS window while link Dbase part for parts placed from library
+ F. v: o5 z6 H% K" p" V5 |898598 ALLEGRO_EDITOR MENTOR Negative planes from Mentor Board Station not being translated.
9 y; L& s( t- ~7 g899556 ALLEGRO_EDITOR ARTWORK Import artwork seems not to work correctly.4 p/ S" O2 ]4 Q [
900501 ALLEGRO_EDITOR PLACEMENT "lace Replicate Apply" is showing lot of DRC's during placement of replicated circuit in 16.5
1 K3 M- K+ `: f) o901141 CIS EXPLORER Japanese character appear garbled in CIS explorer window.3 a% J% G$ X' O4 Z! ]5 r
901666 CAPTURE OTHER Home page of Flowcad-Switzerland and Flowcal-Poland is not preserved on captre restart on start page0 h/ z6 x- m) ~! W8 ~
902066 ALLEGRO_EDITOR DRC_CONSTR Shape in Region not follow the constrains
( W0 }. @: b6 p- h: K902349 CAPTURE LIBRARY Capture crashes while closing library
/ o( j/ ^7 k [+ W5 {902508 F2B PACKAGERXL SPB16.5 Packager-XL consumes much more memory than 16.3
* W+ A, w* c9 q0 Q8 D* c- `902841 CAPTURE GENERAL Capture Start page does not show
# r5 I6 J# ?0 B902876 F2B PACKAGERXL Packager fails on the design upreved in 16.5" Z' b. b1 k1 w, Y2 t
902959 CONCEPT_HDL HDLDIRECT HDLDirect Error while saving design
9 M: S1 i9 K3 y% X; s7 d903171 PSPICE NETLISTER Why Capture is treating hierarchical power ports as floting nets in complex heirarchy designs?" B; H. a: H7 ^0 W7 \
903713 ALLEGRO_EDITOR PARTITION Placement Replication do not work fine in the Design Partition9 n( ]4 @. A: y# c
903799 SIP_LAYOUT DIE_EDITOR Disappear die pins after exiting co-design die editor# m9 O0 x j, S1 p, a1 o' O3 a1 G" c
904021 ALLEGRO_EDITOR OTHER Export PDF from SPB 16.5 produces a file not text searchable
8 l4 c. T- Q1 z0 F3 K4 a904339 CONCEPT_HDL CORE new design crashes using the attached CDS_SITE
; q7 ~6 p( Q3 ?' J904522 F2B PACKAGERXL Part will not package in 16.5 but packages in 16.3
4 K( Q' N' Q- u& D4 k904764 APD OTHER Enhance Scale Factor of Stream Out to support 4 decimal places
1 O# X% [' L' _' P904771 ALLEGRO_EDITOR MANUFACT Pin Number display issue.
* ]9 K3 W, j, f+ a904853 ALLEGRO_EDITOR GRAPHICS Enhancement for showing Static shape as it was seen in 16.33 f( J1 Z/ S8 F5 M$ g
905144 CONSTRAINT_MGR ECS_APPLY Min Line Spacing is larger than Primary or Neck Gap less(-) Tolerance but No Warning in CM
, `9 ?, i1 d. R9 w5 G905314 F2B PACKAGERXL Import physical causes csb corruption. T) l: L3 H: N* ]( _" l) `; a
905337 CONCEPT_HDL CORE ConceptHDL crashes after Import Design process.
+ N7 C9 m- c) `; t( ^" f3 x- k" u905533 ALLEGRO_EDITOR INTERACTIV Pin numbers for components on BOTTOM Side are moved in Preselect mode,when the BOTTOM layer is invisible) ?) e1 ]. f3 ]# f3 o+ y
905796 CONCEPT_HDL CONSTRAINT_MGR Fujitsu CM issue inaccurate concept2cm diff pair issues9 l. V1 b' i8 w
905811 CAPTURE EE_INTERSHEET_RE interesheet references in the form of grid grid page number instead of page number grid; E& y: a6 j" d# R9 d Q
906118 CONCEPT_HDL CONSTRAINT_MGR Cannot open CM if SIGNAL_MODEL value was not assigned in ptf.
, q Y, p: L6 k906153 ALLEGRO_EDITOR SCRIPTS Unable to run allegro script in batch mode on the attached board.
% s4 \* k# `% Y4 L* z) M( d906182 APD EXPORT_DATA Modify Board Level Component Output format9 y$ }9 k1 l( W7 S% l" S
906200 ALLEGRO_EDITOR DFA Enh- DFA drc invoked in Batch mode returns false constraint value in Show Element2 r. I: i0 W( S! P
906517 PSPICE PROBE PSpice new cursor window shows incorrect result.- C$ Z- w6 ? P2 l8 o
906627 ADW COMPONENT_BROWSE ppt options are not read if ucb is launched from FM. works fine if launched from dehdl.5 G. g: u/ }1 b' a3 Q a/ M6 h1 x+ @1 d
906647 SIG_INTEGRITY LIBRARY lib_dist creates a signoise.log in current directory (with backup files like ,1 ,2 etc.) on each run
) @ W; E1 J% C& Q. I" r906673 F2B PACKAGERXL Ignore the signal model validity check during packaging x$ y9 u# I" f# K' n& W. B
906688 ADW LRM A copy of source design gets created in worklib of target design after 'Import Design'* W$ A1 }( b, _
906750 ALLEGRO_EDITOR PARTITION Importing design partition removes the testpoint reference designation
) p* I N6 s2 z! y906874 PSPICE NETLISTER Error less than 2 connections for unconnected hierarchical pin
/ f L( m1 ~9 x907095 F2B OTHER Part Manager does not show Error as Undefined when directive ptf_mismatch_exclude_inj_prop is used
2 r# r2 u8 |- a6 j# X907424 ALLEGRO_EDITOR GRAPHICS Allegro add option for pre 16.5 shape display* X: q0 R0 E0 o/ A. i
907490 CAPTURE NETLIST_LAYOUT 16.5 Layout netlist is not correct. It differs form 16.3 layout netlist.% `/ A5 X7 u9 K8 }. r2 S
907884 SIP_LAYOUT MANUFACTURING Need to add an "NC" pin text option for "Manufacturing Documentation Display Pin Text"& ^8 ~# v) ?! @0 c8 l% Y
907885 SIG_INTEGRITY OTHER Matchgroup targets lost when importing netlist to Allegro layout in HF318 y& H. E9 j6 F
907929 CAPTURE TCL_SAMPLE TCL command to delete a property from parts in a library is not working correctly8 X& Y- y5 w N
907933 SIG_INTEGRITY OTHER Single line impedence not working in OrCad PCB Professional
3 n5 E% [5 _& R0 B907963 CONCEPT_HDL CORE Design uprev issue when moving from 16.2 to 16.5
4 p9 |$ ]2 T4 C* b% K908000 SIG_INTEGRITY OTHER Inconsistence z-axis delay reported on Tpoint when define at via location.% ]% \6 m7 I. [
908057 CONCEPT_HDL CORE DE HDL crash with the cut and paste of a signal name5 L0 ? S R4 d' U5 j" L' r) H
908060 CONCEPT_HDL CORE CTRL+LMB Option not working correctly in 16.3
' S' M0 v& w# N( m4 {) E908210 CAPTURE CONNECTIVITY Connection is being lost while dragging a component
# `$ Z0 q( Q8 p9 }4 W6 A/ c f908241 CAPTURE DRC DRC error column is blank in DRC markers window in 16.5
m0 g0 _" b7 p7 |) |1 g2 G, Q908339 RF_PCB BE_IFF_IMPORT mechanical holes VIAFC are not at the right place* ~( d$ C* H/ M* j9 @9 s( C
908534 SIP_LAYOUT SYMB_EDIT_APPMOD issues with symbol editor and copying pin arrays
% I4 Y, [* B: s! V+ o9 [( T6 V908535 F2B DESIGNVARI When I try to view my variant file the variant editor crashes& F. z( A" b7 J
908595 APD 3D_VIEWER cadence Design 3D viewer" screen pops up and is all black because the colors have all converted to b
p6 r4 n. X: M7 P) g5 J" K( I8 K908849 CAPTURE ANNOTATE Getting crash while annotating the attached design
* f( o9 j! U! H. T5 \- h, ^- _: f( S908874 CONCEPT_HDL CORE Part Manager - No Part Found error when using CCR# 775788 feature
. f( d, K) L7 D. N+ E1 T9 H. ?& e909077 CONCEPT_HDL CORE After packaging pin numbers remains invisible even when $PN$ \+ E, j% G* x" a1 U k- W
909104 ALLEGRO_EDITOR SYMBOL Warning message needs to be modified. It does not save the symbol and also not tell the actual problem.
7 P( v% @& \6 Z; [909417 ALLEGRO_EDITOR REPORTS "report -v upc" returns 'Segmentation fault' on Linux7 f0 S% `7 q' m! P3 Z: u3 V* D
909635 SIP_LAYOUT DIE_STACK_EDITOR Add Interposer crashes in SiP Layout
& M4 \' C3 N# N* N4 @909749 ALLEGRO_EDITOR MANUFACT Allegro Crash during dimensioning4 H1 m% }+ I# c8 Q
909760 SIP_LAYOUT MANUFACTURING Create bond finger solder mask doesn't follow the mask opening as defined in the padstack
' r% H$ a8 B) q+ ]- ]4 S909861 F2B PACKAGERXL NetAssembler broken within the latest 16.30.031
' r: U2 s/ v% Q) ~) m5 q910006 CONCEPT_HDL INFRA Motorola design fails to uprev from 16.3 to 16.5, xcon file is getting corrupted.4 L8 j3 o6 h( A% M* D9 R
910141 CAPTURE NETGROUPS Modify NetGroup definition does not update Offpage Connector
5 A) @( e8 Y2 w- N910340 ADW LRM Import design in schematic, only 1 page import, the entire block is getting imported.
5 W0 g8 r& J9 A# p" a$ m# O910678 SIG_INTEGRITY OTHER The Analyze> Model Assignment> Auto setup is not creating/assigning models to discrete components in 16.5
# d0 J# S, J5 Z! B910713 F2B DESIGNVARI Variant Editor crashes when you click web link under Physical Part Filter window., ^! B6 z: V5 V. }% J0 v) g6 Y
910936 F2B PACKAGERXL ConceptHDL subdesign net name is inconsistent
& M: z7 k: G, R% H! ~911530 ALLEGRO_EDITOR SYMBOL Package Symbol Wizard does not create symbol with the name given
% B- G( Z% P6 d G, ?' A2 |911631 CONCEPT_HDL CORE DEHDL crashes when opening a design+ T# U3 ]* ]$ ]9 Q( M8 R7 p
912001 ALLEGRO_EDITOR OTHER option_licenses entries are made in allegro.ini even when not set as default
3 C; N2 b# V$ l( o' d# b. q912459 F2B BOM BOMHDL crashes before getting to a menu
3 E$ O0 V1 C6 i2 m7 i) g) u913359 APD MANUFACTURING Package Report shows incorrect data
, J& O% Z$ ]& U' C; G$ @
9 U( q) G0 p/ G! b# ^4 D% UDATE: 06-24-2011 HOTFIX VERSION: 001# |1 }- B/ q6 ~( R( F
===================================================================================================================================
% W! }, g6 P C. c; A( S/ \9 ?! zCCRID PRODUCT PRODUCTLEVEL2 TITLE
, E; c& i7 Q0 k+ K===================================================================================================================================; H5 o) u. Y$ B; ?- d7 ?- {
293005 ALLEGRO_EDITOR DATABASE Allegro crash when attempting to move mech. symbol1 l4 e& L. V4 v9 p: @! `
298289 CIS EXPLORER CIS querry gives wrong results/ A, Z) _$ Y* g8 Y' m
366939 ALLEGRO_EDITOR OTHER Cannot attach refdes on silk subclass with add text
' n9 [" d5 D1 a) f% S. I4 U! f432200 ALLEGRO_EDITOR MANUFACT Fillets with an arc are required for Flexi designs3 E& |6 ~7 `! N& }8 |$ m; O
443447 APD SHAPE Shapes not following the acute angle trim control setting.6 A* H' C- k: y, V+ \& u; \
473308 PSPICE AA_SENS Passing variables to lower level blocks using subparam! W" M! W( ^. S% G. q# ]& J
517556 PSPICE AA_SENS Advanced Analysis does not support variables being passed down the hierarchy1 O9 Q( C" U& h7 ?5 m% P' Y
548143 ALLEGRO_EDITOR SHAPE Dynamic shpe on Etch TOP will not void properly.. Y" t; Q5 B- A- w
606959 ADW COMPONENT_BROWSE Key properties with blank values are not getting read in shooping cart# n; d' ^0 m' C1 U8 Q9 }
616466 ALLEGRO_EDITOR SHAPE Solid shapes are not getting filled# _( W2 ^/ V! {# |, f; |" r o
641358 SIP_LAYOUT DIE_STACK_EDITOR Request for Via and Multi Layer Pin support for DIE stack Area (blue region), M& w9 \* L' [; ?
644122 SIP_LAYOUT OTHER SiP Layout - xsection - ERROR Adjacent conductive layers are not allowed, but these are diestack layers not conductor/ y- r( _4 Y* x8 t3 w# o" {, U
645816 ALLEGRO_EDITOR SHAPE Slide a cline all removes gnd shapes on board3 e+ {+ L2 }# m z% {
725355 ALLEGRO_EDITOR SHAPE User can not voided Logo correctly.2 Z6 U/ s& e- y/ w5 i# Z- S( U+ D
763569 CONCEPT_HDL CORE Display status of Hide/Show unconnected pins icon in DE HDL UI
0 |- s( q( K2 b1 s9 q6 E& X770021 CAPTURE BACKANNOTATE Changing pin group property after pin swap resets pin numbers
- f, T/ O" h2 V: [& _ `792126 CAPTURE PROPERTY_EDITOR Attempt to change display for occ prop resets; I8 K, f# z; s: Z5 z
799014 CONCEPT_HDL CONSTRAINT_MGR concept2cm errors not shown in export physical after hier_write
: O& P) O- p+ g4 q1 z803147 CIS LINK_DATABASE_PA Link DB part should not change RefDes of multi package part) t& F8 x$ L+ F! P+ {" @
804240 PSPICE DEHDL Problem in simulation result for a multi-section split part.
1 C( q1 j9 b% R0 V' a809118 CAPTURE NETLISTS ENH to compare two schematic Capture designs5 ?) m' }8 h5 T
816568 ALLEGRO_EDITOR SHAPE shape disappears when update to smooth.. State no etch
6 {/ R m, x7 g7 D e0 N& O4 y0 b830053 CAPTURE STABILITY DXF export fails if schematic folder name as /* o6 z6 n' l* c: j; m, }% `
832108 ALLEGRO_EDITOR SHAPE Shape void incorrectly.. y& |* s2 s8 |( a) Q$ E$ a
833542 CONCEPT_HDL CORE PDF publisher font is NOT WYSIWIG with respect to what seen in DE HDL. b; R- v1 [* E$ j' A
835777 CIS DERIVE_NEW_DB_PA For XLS, donot display table as worksheetName$worksheetName to avoid 8012 error4 h7 n2 l u, \4 Q- l8 \9 ]
837640 CIS GEN_BOM date format of CIS BOM has broken macros of 16.2 in 16.3 version
: D" S" ]2 D' E- ] o4 U844074 APD SPECCTRA_IF Export Router fails with memory errors. T+ U) w" R+ d) S; ~* n9 E
851595 CONCEPT_HDL CORE Pin numbers overlap on the pin and increase in size
" n3 X3 W7 Q i4 ?# {! [. v9 U, I0 d- X852832 CAPTURE BACKANNOTATE Why is Capture crashing with Mentor back annotation?. u$ O7 P, ?; Y# E+ g: n( ~' L) a
855015 ALLEGRO_EDITOR OTHER The rats are NOT connecting to the ends of the clines like they should be.
9 w5 [. F; s) w& U& E1 j4 J; v/ f859883 CAPTURE NETLISTS ENH to compare two schematic Capture designs3 J% Z) R& `& t$ q7 Z* \
866009 SIG_INTEGRITY OTHER Net with Pull-up/down should not be used for Diff-pair.
& _2 }5 h+ T: R& w2 G) f( t3 M' c866830 SCM REPORTS Multiple lines added as separator between title block and report header instead of single line/ `. _2 R' t% {9 H8 V2 `( B: o
866833 SCM REPORTS Extra indentation is left in the left side of the report when the Line Numbers are set to OFF
7 E: b! C1 Q8 n5 L868618 SCM IMPORTS Block re-import does not update the docsch and sch view' G [; j K9 ~
873402 SIP_LAYOUT LOGIC pin swap for co-design die in SiP
( I' ` P/ P2 Z% z4 R F874010 SIG_INTEGRITY OTHER PCB SI crashes when the Xnet is extracted with VARIANT_TO_IGNORE property.
. K5 u' m1 m9 U: ]874400 ALLEGRO_EDITOR INTERACTIV Flip mode issue with move command3 E/ Z% d1 J1 _+ s# J: C
874966 ALLEGRO_EDITOR INTERFACES Placed mechanical component do not get Ref Des or part number in IDF file4 r9 b% ^" f# F
875709 ALLEGRO_EDITOR REPORTS Film area report generated incorrect data at l1
; }- D8 `& O$ a- o; J) Y876275 CONCEPT_HDL CONSTRAINT_MGR Constraint Manager not retaining target net) M) Z M% W8 t3 K( ~+ o2 }7 t4 D; f
879361 SCM UI SCM crashes when opening project- L0 A2 b* V6 I J& Y P% ?/ ?
879496 CONCEPT_HDL OTHER Customer wants to have the tabulation� key as separator in HDL BOM.
& }% e# C3 {6 R) c3 t879514 PSPICE AA_MC Monte Carlo to handle equation as comp VALUE. X; w9 ^3 @) D3 i2 q
881845 ALLEGRO_EDITOR SHAPE Delete island deletes complete shape r( V1 M) A2 k- }
882413 PDN_ANALYSIS PCB_PI PDN Analysis should support routed power nets
# W4 J* S; j5 z0 Y9 p8 l882427 PDN_ANALYSIS PCB_PI PDN Analysis target impedance should have a variable multiplier
4 C7 A% r. d$ z4 c882567 SIG_INTEGRITY OTHER PCB SI crash if boolean type prop was specified to VARIANT env.
L u4 a: n, k6 F$ a882644 ALLEGRO_EDITOR PLACEMENT PCB Place Replicate Function automatically match Enhancement5 m1 j2 R1 T0 n* h. _4 G
883164 ALLEGRO_EDITOR INTERACTIV Vias marked fanout moves away from position when moving component
* T4 @; |- r5 O) c* a883224 SIG_INTEGRITY SIMULATION crash while reflection simulation from Constraint Manager) W1 M# y! b, T- r( _: X6 A7 G2 f! l
883760 PCB_LIBRARIAN METADATA Incorrectly formatted revision.dat file in the metadata folder
2 G( U" k8 {- l) d8 f, X885391 SIG_INTEGRITY SIMULATION RLGC data sampling algorithm and w-element interpolation.
8 s1 b( l2 R/ i885849 ALLEGRO_EDITOR MANUFACT Silkscreen Audit cannot find Solder mask for the text string/ ]5 p5 V$ A3 j2 `
885996 SIG_INTEGRITY OTHER The effect of sn_maxwidthlimit user preference is not seen in cross section impedance calculations
% {# s. g( o# X886090 ALLEGRO_EDITOR INTERACTIV Add Arc w/Radius does not snap to grid4 y u- ^" `8 L& {+ p5 l
887180 CAPTURE SCHEMATIC_EDITOR Signals Navigation window doesnt get updated for Buses
$ E3 q5 @, _! W9 b887442 APD SHAPE Copper pour of Dynamic shapes on Top layer which contains many existing signal traces fails.6 F0 f2 s1 p- O2 \) o
887578 SCM AUTO_UI Component Replace pops-up the DSPANE-204 Message. t% ^" l8 E& P, f8 ~& U
887926 SIG_INTEGRITY GEOMETRY_EXTRACT Field solution failed if diff trace on bottom doesn't have reference plane.0 R4 \& R9 Q) `: `
888414 SIG_EXPLORER OTHER View Trace Parameter display the thickness of dielectric incorrectly.
, ?. N5 M1 k% Y888600 CONCEPT_HDL CREFER Cross References not added to Schegen schematic
1 s/ i, O8 G& t/ n; y888679 SIP_LAYOUT SHAPE Can't create the Dynamic shape on layer M1_sig without unwanted horizontal openings appearing.
" ]. @0 C2 g# w1 z% u' E4 E7 ^) p888804 ALLEGRO_EDITOR OTHER Fillet will become static shape after import from partition board.% L; A4 A$ i/ Q5 P' a1 k
888945 CONCEPT_HDL OTHER unplaced component after placing module
# b# X# E' F4 i; t! O889222 ALLEGRO_EDITOR SHAPE Allegro freezes/hangs when adding shape as Polygon with OpenGL ON.
2 T2 q( C- A8 G& F% B# f& C889365 SIG_INTEGRITY GEOMETRY_EXTRACT top/bottom trace impedances extracted to sigxp are wrong in 16.3/ L* C1 r$ N5 C; g% \% G! ~% f
889404 ALLEGRO_EDITOR OTHER Incorrect pad size for Top conductor padstack written to column 59-62.
/ R: I6 u7 S# ~% W889426 CONCEPT_HDL CHECKPLUS CheckPlus does not find single node net
5 i) F8 c* Q/ y" @. X889636 ALLEGRO_EDITOR MANUFACT Incorrect spelling of "Visibility" in "Film Control" tab in the Artwork Control Form: U+ L- C8 J1 [) N+ f8 A
891235 F2B PACKAGERXL Packager crashes without creating a pxl.log file5 _( L; b' ?/ c* d6 t0 p
891292 ALLEGRO_EDITOR SHAPE arc routing causes weird undesireable shape fill performance
9 H5 l' v% N3 x891856 ALLEGRO_EDITOR EDIT_ETCH crash when sliding diff pairs
. w, v9 b+ M$ g0 }5 Q2 ]( T892375 ALLEGRO_EDITOR PLACEMENT Place Replicate Update disband other groups, irrespective Fixed property added or not.; S- k' ]* ^ T/ f+ c6 M
892455 ALLEGRO_EDITOR SYMBOL Why the overlapping pins are not reported with DRC?
' o) P6 G0 }) ~; L892541 SIG_EXPLORER OTHER Export/Import layerstack through the technology file is changing the layer thickness
. F. _1 I) @5 L$ R# s892766 APD WIREBOND Excuting Finger moving cannot push aside finger to move with together by shove all mode) t; a8 K) \) S8 p E1 q
892907 ALLEGRO_EDITOR DRC_CONSTR DRC not reported for etch_turn_under_pin violations
5 H0 d- p6 u! S% b892963 ALLEGRO_EDITOR SKILL Bad shape boundary created after axlPolyOperation 'OR& U+ Z: ^0 A) \! L/ I
892964 SIP_LAYOUT LOGIC Request that Edit Parts List use Dashes "-".2 R5 n6 ]; b2 j
893295 APD WIREBOND Why move wirebond command does not shove wirebonds? This result in drcs.) U W5 D* Z; D" Z( z. ~
893706 CONSTRAINT_MGR OTHER On line DRC hangs on partitioned board
N( `) w( [- y b. B893743 APD EDIT_ETCH Route behavior when spanning pads not as expected.4 K$ G$ x$ t1 { K( ?5 D. ]) R
893783 SIP_LAYOUT OTHER Padstack Design Editing update File menu with a Update to Design and Close instead of 2 operation
1 g* E9 S; ?% {. o894456 ALLEGRO_EDITOR REPORTS Request Net names be added to Propagation delay lines of the DRC report.' }. Z0 N2 B( t7 y& B, t
894499 SIG_INTEGRITY LIBRARY Tool crashes when moving a cline or selecting the Info icon with OpenGL on.
V. v% B: ^" s2 E4 F894582 APD SHAPE When making a dynamic xhatch Via shapes surrounding are abnormal.0 {- G4 u: @- p& x5 G
895542 SIP_LAYOUT WIREBOND SIP design crashing when moving bond finger using blur mode BLUR_BONDFINGER_PRESRV_CON
& J" L1 l* i( q$ y3 U/ b895591 ALLEGRO_EDITOR PCAD_IN Importing PCAD file fails to get to the point where we can map layers2 T" Z- u- C4 K! C2 m
895757 APD ARTWORK Import Gerber command could not be imported Gerber data
. i% y: {! |! H+ P3 ^895964 CONCEPT_HDL CHECKPLUS The CheckPlus command getFileSubstrings is not working correctly" c% r# k0 d( J
896428 SCM UI Changed Ref Des value not maintained in DEHDL block when part is replaced
: I6 m+ a* ^; x5 E s896655 CAPTURE EDIF Import/Export Design of Hierarcy design with OrCAD Capture1 h8 h7 s' t# U# [7 S; M
896846 CAPTURE IMPORT/EXPORT Import edif2cap and capture is crashing
- w4 N5 K$ f+ J8 _. H1 }897155 ALLEGRO_EDITOR REPORTS Copper coverage in L2 and L7 looks like the same but film area report had large gap.
- H4 ^$ N: ]7 ]897654 CAPTURE EE_INTERSHEET_RE Capture crashes on adding intersheet refernces in abbreviated format on attached design.
8 E b6 U( E& z6 B C; l899344 RF_PCB BE_IFF_EXPORT dlibx2iff does not provide the component boundary drawing$ t* Z2 y% v* W, w
899629 CONSTRAINT_MGR OTHER ECset for Total Etch Lenght is not present in OrCAD Prof
3 p* y: t: W5 U- ~+ v4 j4 P900175 CONCEPT_HDL CONSTRAINT_MGR Few Xnets are lost from Match Group after packaging and importing the netlist to board file.
x7 _# Q E3 C/ L- I! H4 X P900481 CONCEPT_HDL CORE Genview creates a larger symbol without taking the no. of pin in consideration
* n0 H) }1 V" l900813 ALLEGRO_EDITOR DRC_CONSTR With rotated pads, pad (pin - via) soldermask spacing DRC is unreasonable.
* _# H( t, A5 P3 u+ O900905 PSPICE STABILITY Simsrvr crash and RPC Server unavailable error while running simulation.
7 b! Y% A0 b/ @3 d901783 CONCEPT_HDL CORE CDS_PART_NAME is annotated on the schematic canvas after running back annotation in 16.5; e, R! a- i" P( P$ Y9 j5 N6 A
901909 APD EXPORT_DATA The "package_pin_delay_length.rpt" with Z-axis delay turned on seems wrong
! q; p0 w' z% N0 a* b( h/ G& W901987 CONCEPT_HDL OTHER SPB16.5 zoom fit does not center the page while ploting the schematic page
# W( ]" Z' `' L" b% T' b902133 CIS OTHER The visible part property value are being shown very distant from part graphics on schematic) T% _1 e! `0 f4 u
902166 SPECCTRA ROUTE Specctra crashes when reading in "bestsave.w" file
M" E( z3 @! v) K9 e! A# ]9 T902170 ALLEGRO_EDITOR DATABASE Diffpair Issues with OrCad PCB Designer Professional0 n4 v7 D5 \( H7 o5 g/ S3 b5 B8 N
902177 CONSTRAINT_MGR CONCEPT_HDL Option to view the layer thickness in CM worksheet through worksheet customization
; X( R0 t q( @, u5 c/ o; s902463 ALLEGRO_EDITOR INTERACTIV APD crashes when we click ( show element ) on certain components
+ |8 ~: [8 f9 Q q902621 CONCEPT_HDL OTHER Design Differences (vdd) Crashes3 A% D7 G* q/ w; B) {; J g
902909 APD WIREBOND die to die wirebond crash
+ f5 U9 {1 z Q0 }902933 ALLEGRO_EDITOR PADS_IN Pads_in fails while reading PADS ASCII file body# j X/ [( n& n. O. h; T" C/ W$ X
903284 PDN_ANALYSIS PCB_STATICIRDROP IRDrop voltage gradients are plotted outside of the PCB outline
" Y! Y3 _ ~3 y% K( ^4 D6 f: l903680 CONSTRAINT_MGR ECS_APPLY Constraint Manager not passing all hiearchical member objects to a custom measurement.
4 m; v( \( E/ G6 Z9 w904403 ALLEGRO_EDITOR DATABASE Allegro crashes when refreshing module |
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发表于 2012-2-21 14:58
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