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各位大神,小弟新使用MSP430F6726A做开发,遇到晶振不起振问题,头疼不已,还请各位大神指点迷津。
) `5 o% B- r7 @* U0 G" z主要问题:使用32.768kHz晶振接mcu24,25管脚(XIN,XOUT),根据规格书使用12pF的匹配电容,晶振不起振,更换3pF,6pF,9pF,15pF,22pF,30pF,47pF匹配电容还是不起振,询问ti技术人员也没给出具体解决办法,基本上也是从PCB布线,电容匹配方面给分析的,但都已试过,没起作用,由于此款MCU自带晶振,外部晶振不起振会转到内部晶振起振,以下是源码部分从TI官网上弄得:
1 f9 K1 A' S5 N" V4 }void Systerm_Clock_init(void)
+ ~" L5 e) F; c1 b! S* K% s4 f{
2 d& B2 a+ ?0 A" V7 ? volatile unsigned int i; # |4 m7 Q$ g$ K" ~0 l
PJDIR |= BIT0 | BIT1 | BIT3; //ACLK, MCLK, SMCLK set out to pins& `' z4 Y9 ]/ t# V& ^
PJSEL |= BIT0 | BIT1 | BIT3; //PJ.0,1,3 for debugging purposes.
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8 p, o& M. C" O+ E // Setup UCS
& _% Z: Z( _4 x0 a- R // Loop until XT1 fault flag is cleared
; F# p& ?! v7 x! N o9 H do
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- s( ~: ^3 n1 ?! u$ R7 A( q UCSCTL7 &= ~XT1LFOFFG; //Clear XT1 fault flags
. ]9 }# Z) Y( K7 ~5 ^+ H% t, X; v } while (UCSCTL7 & XT1LFOFFG); //Test XT1 fault flag- R: k m! w& k y7 Y
8 p. u( c0 Z( R/ j5 Y* s+ h UCSCTL6 &= ~(XT1OFF); //XT1 On
# {; x T. o! _# _ UCSCTL6 |= XCAP_3; //Internal load cap
& n6 y T3 F3 M& D9 h) P __bic_SR_register(SCG0); // Enable the FLL control loop# ?1 X- u2 w ^; a* q
UCSCTL0 = 0x0000; //Set lowest possible DCOx, MODx
7 V; N- M: r, Q8 r ]# x$ C8 D UCSCTL1 = DCORSEL_5; //Select DCO range 16MHz operation9 H! h5 b1 q& y/ S7 J
UCSCTL2 = FLLD_0 + 511; //(N + 1) * FLLRef = Fdco=(487 + 1) * 32768 =15990784Hz= 16MHz $ A0 H; l7 q. X9 X# B ~
__bic_SR_register(SCG0); //Enable the FLL control loop
* Q0 C. c# `/ ^4 h+ P" r __delay_cycles(600000); //32 x 32 x 16 MHz / 32,768 Hz = 500000 = MCLK cycles for DCO to settle) J8 U1 h2 O- @& ]1 O
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UCSCTL4 |= SELA_0+SELS_3+SELM_3; //Set ACLK = XT1,SCLK=MCLK=DCOCLK=16M4 c. z' {; x. S: i- X" G* F
UCSCTL6 &= ~(XT1DRIVE_3); //XT1 stable, reduce drive strength*/
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}
. e+ ]& S6 H+ `4 J实在不清楚到底哪出问题了,还望使用过此芯片的大神给指导一二。3 v. U' p" I( `0 Y% n5 u" p( p
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