Group | Feature | GTP | GTX | GTH |
PCS | 2-byte internal datapath | X | X | X |
4-byte internal datapath |
9 e/ z. Y" Q4 V5 R% x | X | X |
8B/10B encoding and decoding | X | X | X |
64B/66B and 64B/67B support | X | X | X |
Comma detection and byte and word alignment | X | X | X |
PRBS generator and checker | X | X | X |
FIFO for clock correction and Channel bonding | X | X | X |
Programmable FPGA logic inteRFace | X | X | X |
PMA | One shared LC tank PLL per Quad | 7 _0 n7 I' x* ]
| X | X |
One ring oscillator PLL per channel |
3 K1 l- Z, @" {" K0 P- i2 v6 F" ^ | X | X |
Two shared ring oscillator PLLs per Quad | X |
. r( F+ z' s$ A; n0 o+ ~# D |
! A2 M* N5 O: l( _ |
Flexible reference clocking options | X | X | X |
Decision feedback equalization (DFE) | , }2 X2 Q# y& \6 `, m4 j
| X | X |
power-efficient adaptive linear equalizer mode called the low-power mode (LPM) | X | X | X |
TX Pre-emphasis | X | X | X |
Beacon signaling for PCI Express® designs | X | X | X |
Out-of-band (OOB) signaling including COM signal support for Serial ATA (SATA) designs | X | X | X |
RX Margin Analysis | X | X | X |