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偶也跟一贴！
/ p, b& l W; r1 ?6 Y以下内容来自《high speed digital system design》。( }- V' [- U- y8 O
?0 W7 y7 W1 R9 ]8 s& X( r
A via is a small hole drilled through a PCB that is used to make connections between various
% T* \: Z. \: |( ?. W; O- {1 ^6 ^layers of the PCB or to connect components to traces. It consists of the barrel, the pad, and; ]8 r3 [4 N) P
the antipad. The barrel is a conductive material that fills the hole to allow an electrical
( {% [0 M+ j: }7 E8 R% [# Jconnection between layers, the pad is used to connect the barrel to the component or trace,. {* |4 f' j: T3 a. r( v1 J
and the antipad is a clearance hole between the pad and the metal on a layer to which no
% u5 C' b" ~5 H: ~ s9 Kconnection is required. The most common type of via is called a through-hole via because it
$ d" K7 m8 l; B6 s" D! Bis made by drilling a hole through the board, filling it with solder, and making connections on/ J5 a$ S$ s' D" B7 K
appropriate layers via the pad. Other, less common types of vias, used primarily in multichip
0 ]5 V5 [ q2 u" S% }( Emodules (MCMs) and advanced PCBs, are blind, buried, and micro-vias. Figure 5.1 depicts0 \9 w" h; O( L& N# G
a typical through-hole via and its equivalent circuit. Notice that the pads used to connect the
3 ^& |! m3 D4 A1 p$ ^traces on layers 1 and 2 make contact with the barrel and that there is no connection on( m0 v6 b, v, w# ]; j) {3 V. z
layer 3. Blind and buried vias have a slightly different construction. Since through-hole vias7 H9 {$ I# h- Y$ ~ [9 d
are by far the most common used in industry, they are the focus of this discussion.
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Notice that the via model is simply a pi network. The capacitors represent the via pad$ f# i8 ^# R" U+ g* D
capacitance on layers 1 and 2. The series inductance represents the barrel. Since the via
: |5 p2 U9 f" U% k) Z7 }structures are so small, they can be modeled as lumped elements. This assumption, of4 r' J. H( p1 d, u
course, will break down when the delay of the via is larger than one-tenth of the edge rate.! M8 m. ^+ Z# B; ?9 K( i
The main effect that via capacitance has on a signal is that it will slow down the signal edge9 G. z& y, N3 q, s" }, ]) j
rate, especially after several transitions. The amount that the signal edge rate will be slowed5 V- j7 C' J! W, M. a/ J' Z
can be estimated by examining the degradation of a signal transmitted through a capacitive/ Z% I9 A% |) z$ h
load, as shown later in this chapter in equation (5.21). Furthermore, if several consecutive
! e) @' \8 b% Q; M4 J1 w* uvias are placed in close proximity to one another, it will lower the effective characteristic! E9 Q7 e9 k; r- K! [5 \
impedance, as explained in Section 5.3.3. The approximate value of the pad capacitance is
8 m/ U6 @5 o* _3 W: G[Johnson and Graham, 1993]
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% l2 I$ T6 K+ ~; P: i; p[ 本帖最后由 killerljj 于 2007-11-21 20:51 编辑 ] |
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发表于 2007-9-11 14:20
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支持！
反对！
发表于 2008-1-17 21:53
发表于 2007-9-15 15:34
俺也顶一下,因为焊盘描述的太形象啦!