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偶也跟一贴！9 I4 \$ F- g0 k$ l7 G2 v& W
以下内容来自《high speed digital system design》。
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A via is a small hole drilled through a PCB that is used to make connections between various
9 V; l. V) ^3 D( Y# ^layers of the PCB or to connect components to traces. It consists of the barrel, the pad, and
& H4 O% n S$ Jthe antipad. The barrel is a conductive material that fills the hole to allow an electrical
# q9 X& a3 e& i3 Lconnection between layers, the pad is used to connect the barrel to the component or trace,8 T% S% b% W/ Z
and the antipad is a clearance hole between the pad and the metal on a layer to which no0 S% Z! i! m) G& l) x
connection is required. The most common type of via is called a through-hole via because it
, @( Z& M( I, V9 E" t! a* y' zis made by drilling a hole through the board, filling it with solder, and making connections on) Z- n, M2 O1 l
appropriate layers via the pad. Other, less common types of vias, used primarily in multichip/ s/ i: g5 J' w) y, e* Z8 l8 @
modules (MCMs) and advanced PCBs, are blind, buried, and micro-vias. Figure 5.1 depicts
- Z0 X( s) g( c, f5 H. F! {a typical through-hole via and its equivalent circuit. Notice that the pads used to connect the+ b6 W# p! i: u2 q# s7 Q# K; f0 x% g
traces on layers 1 and 2 make contact with the barrel and that there is no connection on
# x: `9 y, [' D0 j# E" m. V& Wlayer 3. Blind and buried vias have a slightly different construction. Since through-hole vias
[5 e% t, E/ N. Q9 Tare by far the most common used in industry, they are the focus of this discussion.
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Notice that the via model is simply a pi network. The capacitors represent the via pad
% i3 P2 P3 @+ e8 C- \capacitance on layers 1 and 2. The series inductance represents the barrel. Since the via
9 }* y- r9 c! _8 ~$ ?structures are so small, they can be modeled as lumped elements. This assumption, of
$ {! A* O! N+ X4 F$ G! gcourse, will break down when the delay of the via is larger than one-tenth of the edge rate.: M( k: N! z# W5 A
The main effect that via capacitance has on a signal is that it will slow down the signal edge
$ y6 m) E' G1 N. Brate, especially after several transitions. The amount that the signal edge rate will be slowed X# p1 ?# k p! T
can be estimated by examining the degradation of a signal transmitted through a capacitive
- b. _% d$ Q. X# h2 U/ Fload, as shown later in this chapter in equation (5.21). Furthermore, if several consecutive) ] T: F: W, Y, a+ P
vias are placed in close proximity to one another, it will lower the effective characteristic
0 `" R* \5 t6 p4 ~/ timpedance, as explained in Section 5.3.3. The approximate value of the pad capacitance is4 `8 k( p& d% J6 }8 k
[Johnson and Graham, 1993]
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. ?) h4 F* m. p- L" \2 g1 O[ 本帖最后由 killerljj 于 2007-11-21 20:51 编辑 ] |
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发表于 2007-9-11 14:20
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支持！
反对！
发表于 2008-1-17 21:53
发表于 2007-9-15 15:34
俺也顶一下,因为焊盘描述的太形象啦!