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偶也跟一贴！
p- r( l7 i6 R# b* M以下内容来自《high speed digital system design》。- z2 s {( m6 R$ E* D9 w( ?
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A via is a small hole drilled through a PCB that is used to make connections between various
" {4 ^5 C* E' I7 Hlayers of the PCB or to connect components to traces. It consists of the barrel, the pad, and
8 X9 D6 D, X, j5 ~5 G& I" S& ]$ {the antipad. The barrel is a conductive material that fills the hole to allow an electrical4 t- y% o, V2 j, J. }
connection between layers, the pad is used to connect the barrel to the component or trace,
7 |$ ^2 y! a0 p) q$ vand the antipad is a clearance hole between the pad and the metal on a layer to which no
- Q! A; d' @/ Y) B. k* ?connection is required. The most common type of via is called a through-hole via because it
8 J! v0 @ X' H+ f% _- }1 }is made by drilling a hole through the board, filling it with solder, and making connections on
2 `/ X. N9 H9 L9 p& d2 iappropriate layers via the pad. Other, less common types of vias, used primarily in multichip
. d( t4 o) m0 k+ H2 L: kmodules (MCMs) and advanced PCBs, are blind, buried, and micro-vias. Figure 5.1 depicts
, r* H0 M# f% c8 X7 E2 ea typical through-hole via and its equivalent circuit. Notice that the pads used to connect the9 y ]: u( X/ |& d" m0 h/ _
traces on layers 1 and 2 make contact with the barrel and that there is no connection on
* }3 E* o3 s4 L ulayer 3. Blind and buried vias have a slightly different construction. Since through-hole vias
! {. Q+ V9 h7 |+ mare by far the most common used in industry, they are the focus of this discussion.
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Notice that the via model is simply a pi network. The capacitors represent the via pad
1 ?! V7 e9 c' ]capacitance on layers 1 and 2. The series inductance represents the barrel. Since the via- ]/ x3 G* G: |. b! i% G$ Y6 [
structures are so small, they can be modeled as lumped elements. This assumption, of
- l* y& ~9 Q' v& D3 I! Ncourse, will break down when the delay of the via is larger than one-tenth of the edge rate.
7 d: a* n0 o9 \- R4 |% GThe main effect that via capacitance has on a signal is that it will slow down the signal edge
+ }! d% ~8 Q: J& x' r/ G) trate, especially after several transitions. The amount that the signal edge rate will be slowed
0 c' |4 w0 Q6 rcan be estimated by examining the degradation of a signal transmitted through a capacitive3 O0 g' D# O7 a
load, as shown later in this chapter in equation (5.21). Furthermore, if several consecutive
- B& T) B8 A6 W' A7 N; uvias are placed in close proximity to one another, it will lower the effective characteristic: U1 [! Z1 N: v
impedance, as explained in Section 5.3.3. The approximate value of the pad capacitance is
- l) W8 D. q! D D- R( U. ]) J[Johnson and Graham, 1993]
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! X% z2 z$ m0 r$ k[ 本帖最后由 killerljj 于 2007-11-21 20:51 编辑 ] |
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发表于 2007-9-11 14:20
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支持！
反对！
发表于 2008-1-17 21:53
发表于 2007-9-15 15:34
俺也顶一下,因为焊盘描述的太形象啦!