F28335的svpwm的实现

sdsdwwwe22 · 发表于 2021-12-16 18:44

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F28335的svpwm的实现：已经调试，晶振是20MHz

// TI File $Revision: /main/8 $
// Checkin $Date: August 10, 2007 09:04:53 $
//###########################################################################
//
// FILE: Example_2833xEPwm3UpAQ.c
//
// TITLE: Action Qualifier Module Upcount mode.
//
// ASSUMPTIONS:
//
// This program requires the DSP2833x header files.
//
// Monitor the ePWM1 - ePWM3 pins on a oscilloscope as
// described below.
//
// EPWM1A is on GPIO0
// EPWM1B is on GPIO1
//
// EPWM2A is on GPIO2
// EPWM2B is on GPIO3
//
// EPWM3A is on GPIO4
// EPWM3B is on GPIO5
//
// As supplied, this project is configured for "boot to SARAM"
// operation. The 2833x Boot Mode table is shown below.
// For information on configuring the boot mode of an eZdsp,
// please refer to the documentation included with the eZdsp,
//
// $Boot_Table:
//
// GPIO87 GPIO86 GPIO85 GPIO84
// XA15 XA14 XA13 XA12
// PU PU PU PU
// ==========================================
// 1 1 1 1 Jump to Flash
// 1 1 1 0 SCI-A boot
// 1 1 0 1 SPI-A boot
// 1 1 0 0 I2C-A boot
// 1 0 1 1 eCAN-A boot
// 1 0 1 0 McBSP-A boot
// 1 0 0 1 Jump to XINTF x16
// 1 0 0 0 Jump to XINTF x32
// 0 1 1 1 Jump to OTP
// 0 1 1 0 Parallel GPIO I/O boot
// 0 1 0 1 Parallel XINTF boot
// 0 1 0 0 Jump to SARAM <- "boot to SARAM"
// 0 0 1 1 Branch to check boot mode
// 0 0 1 0 Boot to flash, bypass ADC cal
// 0 0 0 1 Boot to SARAM, bypass ADC cal
// 0 0 0 0 Boot to SCI-A, bypass ADC cal
// Boot_Table_End$
//
// DESCRIPTION:
//
// This example configures ePWM1, ePWM2, ePWM3 to produce an
// waveform with independant modulation on EPWMxA and
// EPWMxB.
//
// The compare values CMPA and CMPB are modified within the ePWM's ISR
//
// The TB counter is in upmode for this example.
//
// View the EPWM1A/B, EPWM2A/B and EPWM3A/B waveforms
// via an oscilloscope
//
//
//###########################################################################
// $TI Release: DSP2833x Header Files V1.01 $
// $Release Date: September 26, 2007 $
//###########################################################################
#include "DSP2833x_Device.h" // DSP2833x HeadeRFile Include File
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
#include "math.h"
#include "IQmathLib.h"
typedef struct
{
float ds;
float qs;
float ang;
float de;
float qe;
}IPARK;
IPARK ipark1={0,0,0,0.3,0.4};
IPARK *v=&ipark1;
// Prototype statements for functions found within this file.
void InitEPwm1Example(void);
void InitEPwm2Example(void);
void InitEPwm3Example(void);
interrupt void epwm1_isr(void);
void ipark(IPARK *v);
void svgen(IPARK *v);
// Configure the period for each timer
#define PRD 7500 // Period register
#define PI 3.1415926
float tmr1,tmr2,tmr3;
void main(void)
{
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the DSP2833x_SysCtrl.c file.
InitSysCtrl();
// Step 2. Initalize GPIO:
// This example function is found in the DSP2833x_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
// InitGpio(); // Skipped for this example
// For this case just init GPIO pins for ePWM1, ePWM2, ePWM3
// These functions are in the DSP2833x_EPwm.c file
InitEPwm1Gpio();
InitEPwm2Gpio();
InitEPwm3Gpio();
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
DINT;
// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the DSP2833x_PieCtrl.c file.
InitPieCtrl();
// Disable CPU interrupts and clear all CPU interrupt flags:
IER = 0x0000;
IFR = 0x0000;
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example. This is useful for debug purposes.
// The shell ISR routines are found in DSP2833x_DefaultIsr.c.
// This function is found in DSP2833x_PieVect.c.
InitPieVectTable();
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.EPWM1_INT = &epwm1_isr;
EDIS; // This is needed to disable write to EALLOW protected registers
// Step 4. Initialize all the Device Peripherals:
// This function is found in DSP2833x_InitPeripherals.c
// InitPeripherals(); // Not required for this example
// For this example, only initialize the ePWM
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;
InitEPwm1Example();
InitEPwm2Example();
InitEPwm3Example();
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
// Step 5. User specific code, enable interrupts:
// Enable CPU INT3 which is connected to EPWM1-3 INT:
IER |= M_INT3;
// Enable EPWM INTn in the PIE: Group 3 interrupt 1-3
PieCtrlRegs.PIEIER3.bit.INTx1 = 1;
// Enable global Interrupts and higher priority real-time debug events:
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
// Step 6. IDLE loop. Just sit and loop forever (optional):
for(;;)
{
asm(" NOP");
}
}
interrupt void epwm1_isr(void)
{
// Update the CMPA and CMPB values
svgen(v);
EPwm1Regs.CMPA.half.CMPA=tmr1;
EPwm2Regs.CMPA.half.CMPA=tmr2;
EPwm3Regs.CMPA.half.CMPA=tmr3;
EPwm1Regs.CMPB=tmr1;
EPwm2Regs.CMPB=tmr2;
EPwm3Regs.CMPB=tmr3;
// Clear INT flag for this timer
EPwm1Regs.ETCLR.bit.INT = 1;
// Acknowledge this interrupt to receive more interrupts from group 3
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
void ipark(IPARK *v)
{
float ang;
ang=(v->ang/360)*2*PI;
v->ds=v->de*cos(ang)-v->qe*sin(ang);
v->qs=v->qe*cos(ang)+v->de*sin(ang);
}
void svgen(IPARK *v)
{
_iq Va,Vb,Vc,t1,t2,Ta,Tb,Tc;
Uint32 sector=0;
ipark(v);
Va=v->qs;
Vb=_IQmpy(_IQ(-0.5),v->qs)+_IQmpy(_IQ(0.8660254),v->ds);
Vc=_IQmpy(_IQ(-0.5),v->qs)-_IQmpy(_IQ(0.8660254),v->ds);
if(Va>_IQ(0))
sector=1;
if(Vb>_IQ(0))
sector=sector+2;
if(Vc>_IQ(0))
sector=sector+4;
Va=v->qs;
Vb=_IQmpy(_IQ(0.5),v->qs)+_IQmpy(_IQ(0.8660254),v->ds);
Vc=_IQmpy(_IQ(0.5),v->qs)-_IQmpy(_IQ(0.8660254),v->ds);
if(sector==0)
{
tmr1=_IQ(0.5);
tmr2=_IQ(0.5);
tmr3=_IQ(0.5);
}
if(sector==1)
{
t1=Vc;
t2=Vb;
Tb=_IQmpy(_IQ(0.25),(_IQ(1)-t1-t2));
Ta=Tb+_IQmpy(_IQ(0.5),t1);
Tc=Ta+_IQmpy(_IQ(0.5),t2);
}
if(sector==2)
{
t1=Vb;
t2=-Va;
Ta=_IQmpy(_IQ(0.25),(_IQ(1)-t1-t2));
Tc=Ta+_IQmpy(_IQ(0.5),t1);
Tb=Tc+_IQmpy(_IQ(0.5),t2);
}
if(sector==3)
{
t1=-Vc;
t2=Va;
Ta=_IQmpy(_IQ(0.25),(_IQ(1)-t1-t2));
Tb=Ta+_IQmpy(_IQ(0.5),t1);
Tc=Tb+_IQmpy(_IQ(0.5),t2);
}
if(sector==4)
{
t1=-Va;
t2=Vc;
Tc=_IQmpy(_IQ(0.25),(_IQ(1)-t1-t2));
Tb=Tc+_IQmpy(_IQ(0.5),t1);
Ta=Tb+_IQmpy(_IQ(0.5),t2);
}
if(sector==5)
{
t1=Va;
t2=-Vb;
Tb=_IQmpy(_IQ(0.25),(_IQ(1)-t1-t2));
Tc=Tb+_IQmpy(_IQ(0.5),t1);
Ta=Tc+_IQmpy(_IQ(0.5),t2);
}
if(sector==6)
{
t1=-Vb;
t2=-Vc;
Tc=_IQmpy(_IQ(0.25),(_IQ(1)-t1-t2));
Ta=Tc+_IQmpy(_IQ(0.5),t1);
Tb=Ta+_IQmpy(_IQ(0.5),t2);
}
tmr1=Ta;
tmr2=Tb;
tmr3=Tc;
}
void InitEPwm1Example()
{
// Setup TBCLK
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm1Regs.TBPRD = PRD; // Set timer period
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV2;
// Setup shadow register load on ZERO
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Set Compare values
EPwm1Regs.CMPA.half.CMPA = 1875; // Set compare A value
EPwm1Regs.CMPB = 1875; // Set Compare B value
// Set actions
EPwm1Regs.AQCTLA.bit.ZRO = AQ_CLEAR; // Set PWM1A on Zero
EPwm1Regs.AQCTLA.bit.CAU = AQ_TOGGLE; // Clear PWM1A on event A, up count
EPwm1Regs.AQCTLB.bit.ZRO = AQ_SET; // Set PWM1B on Zero
EPwm1Regs.AQCTLB.bit.CBU = AQ_TOGGLE; // Clear PWM1B on event B, up count
// Interrupt where we will change the Compare Values
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 3rd event
}
void InitEPwm2Example()
{
// Setup TBCLK
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm2Regs.TBPRD = PRD; // Set timer period
EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm2Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm2Regs.TBCTR = 0x0000; // Clear counter
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV2;
// Setup shadow register load on ZERO
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Set Compare values
EPwm2Regs.CMPA.half.CMPA =1875; // Set compare A value
EPwm2Regs.CMPB = 1875; // Set Compare B value
// Set actions
EPwm2Regs.AQCTLA.bit.ZRO = AQ_CLEAR; // Set PWM1A on Zero
EPwm2Regs.AQCTLA.bit.CAU = AQ_TOGGLE; // Clear PWM1A on event A, up count
EPwm2Regs.AQCTLB.bit.ZRO = AQ_SET; // Set PWM1B on Zero
EPwm2Regs.AQCTLB.bit.CBU = AQ_TOGGLE; // Clear PWM1B on event B, up count
// Interrupt where we will change the Compare Values
//EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm2Regs.ETSEL.bit.INTEN = 0; // Enable INT
//EPwm2Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 3rd event
}
void InitEPwm3Example(void)
{
// Setup TBCLK
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm3Regs.TBPRD = PRD; // Set timer period
EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm3Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm3Regs.TBCTR = 0x0000; // Clear counter
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// Setup shadow register load on ZERO
EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Set Compare values
EPwm3Regs.CMPA.half.CMPA = 1875; // Set compare A value
EPwm3Regs.CMPB = 1875; // Set Compare B value
// Set Actions
EPwm3Regs.AQCTLA.bit.ZRO = AQ_CLEAR; // Set PWM1A on Zero
EPwm3Regs.AQCTLA.bit.CAU = AQ_TOGGLE; // Clear PWM1A on event A, up count
EPwm3Regs.AQCTLB.bit.ZRO = AQ_SET; // Set PWM1B on Zero
EPwm3Regs.AQCTLB.bit.CBU = AQ_TOGGLE; // Clear PWM1B on event B, up count
// Interrupt where we will change the Compare Values
//EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm3Regs.ETSEL.bit.INTEN = 0; // Enable INT
//EPwm3Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 3rd event
}
//===========================================================================
// No more. R+ I# c) W, n3 i

xiaoming11 · 发表于 2021-12-16 18:52

这是三相的还是单相的？

unix155 · 发表于 2021-12-16 18:53

哪个单片机？

CLBuu · 发表于 2021-12-16 19:11

为什么输出的是方波，占空比不变化

angern · 发表于 2021-12-21 19:14

PWM怎么初始化

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F28335的svpwm的实现

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