Orcad capture生成网表时出错，大家帮我看看

lyf9908

大家好，以前用AD6,pads, 与在用SPB16.2,很不习惯呀。
     在做完原理图，DRC检查没有错误后，生成网表时，出现：
3 k; m% v3 ]2 `; A5 ^   #248 ERROR(SPCODD-248): All physical pins are common in section 1 of physical part 'CEJMK212BJ106KD_T'.  Each section must have at least one non-common pin.
        Open the part in Part Developer and ensure that you have at least one non-common pin for each section of a physical part.
% t  p3 ~; w8 [* d; t$ v* ~! m      我检查了原理图SYMBOL和PCB封装，也换另外的PCB封装试了试，错误依旧。
8 T# F1 d, }8 W7 h6 D% z  大家帮我看看，是什么原因呀。
+ d& p& ~8 W5 r1 p    我在画原理图时还碰到其它的问题：
      1：元件编号如电阻电容之后，总自动出现一个A或是B,  如：R120A
" b* e, Y0 k2 M2 U. u/ T      2: 在COPY一个元件到另外一个地方去时，本应每COPY一次编号都自动增加，可现在是每COPY两次，编号才自动增加一次。
         为方便大家检查，我把生成网有的出错贴在下面了：
( u9 i& ^4 u$ A0 U8 ]* y8 ?* D      ********************************************************************************
4 P- W# q. n8 f) Y! J. a% _Design Name:
/ k9 z6 u: |' fE:\Hi3515FJ_cadence\hi3515fj.dsn
5 r/ ?# F; ?, Z$ V1 d2 nNetlist Directory:
, L- S$ M& }% }) G' X% f( UE:\HI3515FJ_CADENCE\NETLIST
/ [1 E+ ]6 D8 o3 nConfiguration File:
D:\Candence\SPB16.2\tools\capture\allegro.cfg
Spawning... "D:\Candence\SPB16.2\tools\capture\pstswp.exe" -pst -d "E:\Hi3515FJ_CADENCE\hi3515fj.dsn" -n "E:\HI3515FJ_CADENCE\NETLIST" -c "D:\Candence\SPB16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"
#1 Warning [ALG0016] Part Name "PHONE JACK-4_0_PHONEJACT_4_PHONE JACK-4" is renamed to "PHONE JACK-4_0_PHONEJACT_4_PHON".
8 [5 i) G8 S3 C' k6 Z#2 Warning [ALG0016] Part Name "SN74CBT16214_0_SOP56-20-250-550_SN74CBT16214C" is renamed to "SN74CBT16214_0_SOP56-20-250-550".
/ z$ ?8 X2 i1 Q' u# T( KScanning netlist files ...
6 ]4 b% _  E* f: R. {0 t5 yLoading... E:\HI3515FJ_CADENCE\NETLIST/pstchip.dat
* C# ]9 _0 |9 H& P* U#248 ERROR(SPCODD-248): All physical pins are common in section 1 of physical part 'CEJMK212BJ106KD_T'.  Each section must have at least one non-common pin.
        Open the part in Part Developer and ensure that you have at least one non-common pin for each section of a physical part.
              ERROR(SPCODD-47): File E:/HI3515FJ_CADENCE/NETLIST/pstchip.dat could not be loaded, and the packaging operation did not complete. Check the pxl.log file for the errors causing this situation and package the design again.
: e* n) P7 e& W( }#53 ERROR(SPCODD-53): Packaging cannot be completed because packaging has encountered a null object ID. The design may not have been saved correctly. Save the schema
  S. a! y/ N4 Xtic and rerun packaging.
! E" F! Z& n2 k& p8 i. }#3 Error   [ALG0036] Unable to read logical netlist data.
Exiting... "D:\Candence\SPB16.2\tools\capture\pstswp.exe" -pst -d "E:\Hi3515FJ_CADENCE\hi3515fj.dsn" -n "E:\HI3515FJ_CADENCE\NETLIST" -c "D:\Candence\SPB16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"

3 N3 J) H, f( T/ Z' g2 ?/ L*** Done ***

rockyawei

定义其中的某个电源Pin类型为power就好了。

九零年代

Part Name "PHONE JACK-4_0_PHONEJACT_4_PHONE JACK-4" is renamed to "PHONE JACK-4_0_PHONEJACT_4_PHON".
: @& h( i2 A% f5 N7 B) G
请问这个问题该怎么解决？