基于FPGA的单稳态脉冲展宽电路的设计问题！

marshal403006

请各位高手看看本人的程序，编译通过了，仿真却没有结果。我想实现的功能是单稳态脉冲展宽（通过外端口控制展宽宽度）。程序如下：
/ G. ?" f5 T1 q5 i& k计数器（控制展宽电路的宽度）部分：
% _  t: Y  }0 S# y) flibrary IEEE;
use IEEE.STD_LOGIC_1164.ALL;
' J/ n" W3 O. ouse IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
& F" N2 I/ B6 k2 p2 tentity counter is
0 P# m: ^  Y' q. `1 K  port(reset,en,clk: in std_logic;
2 T4 M- b# T" V, L  }5 z. e1 ~       N1,N2,N3,N4: in std_logic;
       feed_out: out std_logic);
$ |1 E- G7 `! z" T5 P  end counter;
architecture Behavioral of counter is
signal temp: integer range 0 to 15:=0;
7 k: `5 p  i$ J. {signal k:integer:=0;
begin
process(N1,N2,N3,N4,k,clk) is
1 T/ X% R* C4 t+ ]begin
" J- Q/ ~, }) J/ h+ I   if(N1='1') then temp<=temp+1;
  elsif(N2='1') then temp<=temp+2;
  elsif(N3='1') then temp<=temp+4;
  elsif(N4='1') then temp<=temp+8;
  else null;
3 I( S( `/ }, C/ \4 E7 u7 n  end if;
3 t' H& f* k/ v6 l6 S7 F  if (clk'event and clk='1') then
& e) X' W0 e2 r8 B4 f8 ?) A    if (reset='1') then
$ }: J& Z6 l0 Z       k<=0;
     feed_out<='0';
3 {7 Y( @# s  W& t     elsif (en='1') then   
; g; P9 q( x( d" B/ `3 L    if (k=temp-1) then
         feed_out<='1';
2 ]( J  e5 `( V3 ]5 A. W         k<=temp-1;
     else k<=k+1;
    end if;
    end if;
& p! K, J! s# U) g$ ~8 X  C, cend if;
$ z7 \: k4 q% Kend process;
end Behavioral;
D触发器（脉冲前沿产生电路，又是展宽脉冲宽度形成电路）：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity D_trigger is
& G; q% h/ e5 C- j! z/ R, o) V  port(D,clear: in std_logic;
       clk: in std_logic;
/ @2 H1 L! t% g  L   Q: out std_logic);
6 O/ Z1 k  ]  N; Z; Q0 qend D_trigger;
9 x# N; `$ e) S# m$ V( ]/ Q) [architecture Behavioral of D_trigger is
begin
" Y" o  m- h/ g* I3 gprocess(D,clear,clk) is
& O. O8 m7 a( V7 P+ Bbegin
; i( ~# |0 f* [' Z* t  A: A  if (clear='1') then
; h% q( X+ L2 ]  o+ v4 o6 n0 @% C$ p    Q<='0';     
# Q+ x5 Z! |% e0 ~1 S: V9 `- p  elsif (clk'event and clk='1') then
    Q<=D;
  end if;
end process;  
1 J& Y1 r2 }4 ]; N' G" M3 G4 dend Behavioral;
外部综合部分：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
0 `; [, n- j8 m3 [+ g  {1 Buse IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity pulse_expand is
  port(pulse_in,D_in: in std_logic;
' S1 V+ t3 d/ J5 p3 W) r2 Y. C       clk_in: in std_logic;
2 s, s$ S: e% u& ^* Z   n1,n2,n3,n4: in std_logic;
) M. w$ w" p3 w6 ^4 T   pulsewidth_out: out std_logic);
end pulse_expand;
# A" P7 T7 I9 t( d6 m; H/ Qarchitecture Behavioral of pulse_expand is
signal a1,a2,a3: std_logic;
component counter is
   port(reset,en,clk: in std_logic;
/ w9 O4 l# F$ B4 I      N1,N2,N3,N4: in std_logic;
        feed_out: out std_logic);
+ P& z" g6 p# w8 o. n4 H$ O  end component counter;
  component  D_trigger is
     port(D,clear: in std_logic;
* {* ?9 y* ~% Y$ c/ J, {8 w          clk: in std_logic;
9 a8 O3 p/ z; c" p+ D  B0 e* c      Q: out std_logic);
$ j4 Q- C3 r& Z0 y/ z  end component D_trigger;
# p8 {/ E  k# rbegin
- _! Y* i. W3 A0 z9 X% aP1: D_trigger port map (D=>D_in,clear=>a1,clk=>pulse_in,Q=>a2);
; B! p/ J& ?& q4 c1 Fa3<= not a2;
P2: counter port map ( reset=>a3,en=>a2,clk=>clk_in,feed_out=>a1,
) q4 r- ?7 Z9 L9 X5 q8 [: o    N1=>n1,N2=>n2,N3=>n3,N4=>n4);
pulsewidth_out<=a2;
end Behavioral;

[ 本帖最后由 marshal403006 于 2008-6-2 09:38 编辑 ]