PCB Designer’s si guide

snowwolfe

PCB Designer's SI GUIDETable of Content
' k/ s3 q' \& P( ^# W% ^0 cBasics of SI___________________________________________________________________5
% ^. @/ [6 a6 P. W7 y1 S1 k) C4 x1.1 When Speed is important? _____________________________________________5
' J- L( d# u, m1.1.1 Acceptable Voltage and timing values ________________________________5
- _: g' l/ V/ O+ o/ n8 V1.2 Signal Integrity ______________________________________________________5
* r( K8 y- d3 k% G5 |" q% w/ \# m1.2.1 Waveform Voltage Accuracy _______________________________________5
: n2 E. i- ?4 M1.2.2 Timing_________________________________________________________5
1.3 Speed of currently used logic families ____________________________________5
1.3.1 Transition Electrical Length (TEL) __________________________________6
1.3.2 Critical length ___________________________________________________6
1.3.3 What is Transmission Line? ________________________________________6
1.3.4 What is moving in a Transmission line?_______________________________6
1.3.5 Power Plane Definition____________________________________________6
. t& o2 |- V# I. h2 w6 d1.3.6 The concept of Ground ____________________________________________7
1.4 STRIPLINE circuit with Electromagnetic field _____________________________7
1.5 RLC Transmission Line Model _________________________________________8
7 W! l! W  b7 R: s3 ^" b: i1.5.1 What is Impedance? ______________________________________________8
1.5.2 A Practical impedance equation for microstrip _________________________8
* z1 E2 @+ M6 g4 i8 S' Y# N; ^1.5.3 What is relative dielectric constant Er? _______________________________9
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2 Interconnections for High Speed Digital Circuits _______________________________10

" X0 d$ v! i) i# N6 J2.1.1 Summary______________________________________________________10
2.2 Examples of dynamic inteRFacing problems _______________________________10
2.3 IC Technology and Signal Integrity _____________________________________12
; ]+ g; `* I& }! t$ M5 f2.4 Speed and distance __________________________________________________14
; m; ~3 \) \; D7 x2.5 Digital signals: Static interfacing _______________________________________15
, g) a# q: W9 C7 }! s2 s. \2.6 Digital signals: Dynamic interfacing ____________________________________16
1 _+ P7 t; y: z' _; @" x+ E2.7 Review questions ___________________________________________________18
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3 Interconnection Models____________________________________________________20

3.1 Summary__________________________________________________________20
3.2 Reference model for interconnection analysis _____________________________20
! R0 T9 a& ?, [' W! U3.3 Receiver model_____________________________________________________21
. ]7 m8 _: O0 A, _. V. S4 y2 F% v3.4 RC interconnection model ____________________________________________23
3.5 Parameters of the interconnection ______________________________________25
3.6 Refined models _____________________________________________________26
3.7 Review question ____________________________________________________28

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4 Transmission Line Models _________________________________________________31

2 |( M1 J5 |7 g# y: Q* H' v4.1 Summary__________________________________________________________31
7 Q0 y7 O, B8 c9 H: ?4.2 Transmission line models _____________________________________________31
4.3 Loss-less transmission lines ___________________________________________32
; Q$ L1 J" T2 T* Z/ H$ J* s  t- n4.4 Critical Length _____________________________________________________34
, J/ q7 T9 W) \, R1 v, @4.5 Reference transmission line model______________________________________35
4.6 Line driving _______________________________________________________36
$ R7 N/ c3 w6 o" R4.7 Propagation and reflected waves _______________________________________37
4.8 A sample system____________________________________________________39
1 |3 X: S+ n( X4.9 Review questions ___________________________________________________42
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PCB Designer’s SI Guide Page 2 Venkata

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5 Analysis techniques _______________________________________________________45

5.1 Summary__________________________________________________________45
5.2 Transmission time and skew___________________________________________45
9 J: v) E5 S" F6 O' r5.3 Effects of termination resistance _______________________________________46
6 `% d$ Z: f  i) Z0 E+ G1 }/ A5.4 Lattice diagram _____________________________________________________48
5.5 Examples of Real Lines ______________________________________________49
5.6 Simulation code ____________________________________________________51
5.7 Examples of results__________________________________________________54
4 R6 W8 [0 V' }+ s' A5.8 Review questions ___________________________________________________55
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6 Design guide for interconnection ____________________________________________57

6.1 Summary__________________________________________________________57
. Q+ ?8 R6 }- J. H  X) h4 E: Q6.2 Incident wave switching ______________________________________________57
, ~  g* J9 ]3 ~" @2 i6.3 Effects of capacitive loading __________________________________________58
6.4 Termination circuits _________________________________________________59
7 t2 ]- B$ m: U9 h6.4.1 Passive termination______________________________________________60
6.4.2 Low power termination___________________________________________61
, R% o4 g4 j+ y6.4.3 Active low power termination circuit. _______________________________61
6.5 Driving point-to-point lines ___________________________________________62
6.6 Driving bused lines __________________________________________________64
6.7 Design guidelines ___________________________________________________67
* o2 z/ Z# f' l* Y% N6.8 Review questions ___________________________________________________67

snowwolfe

Signal Integrity in Digital Circuits ___________________________________________70
7.1 Crosstalk __________________________________________________________70
7.1.1 Summary______________________________________________________70
7.2 Examples of signal integrity problems ___________________________________70
7.3 Simplified Model for Crosstalk Analysis _________________________________71
7.4 Forward and backward crosstalk _______________________________________74
# z; T' d5 I0 k- p. c5 V7.5 Examples__________________________________________________________76
7 |$ y* C5 \6 u+ Z* L3 ?2 [7.6 Near-end and Far-end crosstalk ________________________________________80
7.7 Review questions ___________________________________________________81
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8 Design Guide to Handle Crosstalk ___________________________________________85

* T4 e% j1 I2 q8.1 Summary__________________________________________________________85
8.2 Effects of Crosstalk __________________________________________________85
8.3 Passive countermeasures _____________________________________________86
8.4 Active Control of Crosstalk ___________________________________________92
4 j) O6 \% I  r! P" y; W. d6 ]* R- h8.5 Review questions ___________________________________________________94
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9 Ground Bounce and Switching Noise_________________________________________97

# ~( U4 j( B3 w0 C9 x# K9.1 Summary__________________________________________________________97
9.2 The totem pole Current Spike__________________________________________97
9.3 Current flow in the output capacitance __________________________________100
9.4 Total Ground Bounce _______________________________________________100
9.5 Review questions __________________________________________________105

10 Design Guide for Ground & Power Distribution _____________________________107

10.1 Summary_________________________________________________________107

PCB Designer’s SI Guide Page 3 Venkata

8 k) n- H7 n4 e' o10.2 Decoupling Capacitors ______________________________________________107
- w0 I8 ~& x+ ^& p10.3 Placement of bypass Capacitors _______________________________________113
10.4 Ground and power distribution________________________________________114
5 R0 I$ g' I: y4 P3 v# p' U10.5 Clock distribution __________________________________________________115
  {* j# ~' h& G2 {& t: K8 p: f. }10.6 Review Questions __________________________________________________118
; O9 E8 A) J" |0 ~% G11 Laboratory Experience _________________________________________________120
11.1 Summary_________________________________________________________120
11.2 Aim of the experience_______________________________________________120
11.3 Generator Parameters _______________________________________________122
6 T$ W( I$ f+ |% n: R11.4 Cable Parameters __________________________________________________123
11.5 Mismatch at driver and at termination __________________________________124
4 a+ I( f9 M* J5 ^4 G2 F7 `% M! x& d( Q11.6 Capacitive Load ___________________________________________________125
3 {1 w4 x" Y* Y& U  D11.7 7. Time-domain reflectometer ________________________________________127
11.8 Driving the line with logic devices _____________________________________128
12 SI Analysis Strategy____________________________________________________133
12.1.1 A modern high-speed design methodology must involve the at least the following: ____________________________________________________________133
" C" v5 l0 Y! b3 C12.2 POSSIBLE HIGH-SPEED DESIGN APPROACHES ______________________133
$ L/ I. @  U- e4 _. n+ O12.2.1 There are two fundamental types of conditions that need to be considered for solution space analysis:__________________________________________________134
12.3 SOLUTION SPACE ANALYSIS _____________________________________135
12.3.1
# m- _- D) t& p$ j6 q6 FSTEP 1 — DEFINING THE INITIAL TOPOLOGY __________________135
( r' N- n; p) r4 c9 f; X1 H# L: C12.3.2 STEP 2 — DEFINE MANUFACTURING TOLERANCES AND THEIR MIN/MAX VALUES ___________________________________________________135
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STEP 3 — DEFINE THE STARTING POINT FOR DESIGN VARIANCES 136
6 \. |6 y* a' h/ n7 r  D7 u2 `9 ?4 q12.3.4
STEP 4 — SET UP AND RUN A NUMBER OF SIMULATION CASES _136
5 D9 L; t8 @1 z. H4 R% s; l12.3.5 STEP 5 — EXAMINE THE SIMULATION RESULTS, IDENTIFY WHICH CASES FAILED AND WHY ____________________________________________136
4 D+ f) ~' _$ `12.3.6 STEP 6 — ADAPT THE TOPOLOGY AND DESIGN RULES AS APPROPRIATE _______________________________________________________137
12.3.7 STEP 7 — REPEAT STEPS 4-6 UNTIL THE TOPOLOGY CONVERGES ON A SET OF VALUES THAT PASS FOR ALL CASES ANALYZED __________137
12.3.8
STEP 8 — DERIVE DESIGN RULES FOR THE TARGET CAD SYSTEM 137
! k' t7 `' b. D5 A6 r12.3.9 STEP 9 — DRIVE THE CAD RULES INTO THE CAD DATABASE, AND USE THEM TO DRIVE THE PLACEMENT/ROUTING PROCESSES ___________138
12.3.10 STEP 10 — POST LAYOUT SI ANALYSIS ______________________139
; K3 j2 S, A6 |( [7 z5 y12.4 CONCLUSION____________________________________________________139
& r$ F6 e$ k! @* ?  o1 z( B13 Glossary _____________________________________________________________141

PCB Designer’s SI Guide Page 4Venkata

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