PCB Designer’s si guide

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PCB Designer's SI GUIDETable of Content
Basics of SI___________________________________________________________________5
1.1 When Speed is important? _____________________________________________5
6 p  W5 u0 F3 r; O$ U1.1.1 Acceptable Voltage and timing values ________________________________5
1.2 Signal Integrity ______________________________________________________5
. r" }; c4 T& C1 ~1.2.1 Waveform Voltage Accuracy _______________________________________5
1.2.2 Timing_________________________________________________________5
1.3 Speed of currently used logic families ____________________________________5
1.3.1 Transition Electrical Length (TEL) __________________________________6
1.3.2 Critical length ___________________________________________________6
1.3.3 What is Transmission Line? ________________________________________6
1.3.4 What is moving in a Transmission line?_______________________________6
% H' C3 L* f! |! U1.3.5 Power Plane Definition____________________________________________6
1.3.6 The concept of Ground ____________________________________________7
1.4 STRIPLINE circuit with Electromagnetic field _____________________________7
1.5 RLC Transmission Line Model _________________________________________8
1.5.1 What is Impedance? ______________________________________________8
/ V/ ?" o4 _: f: `* w1.5.2 A Practical impedance equation for microstrip _________________________8
1.5.3 What is relative dielectric constant Er? _______________________________9
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2 Interconnections for High Speed Digital Circuits _______________________________10

2.1.1 Summary______________________________________________________10
2 u4 G7 u# F' ]1 z2.2 Examples of dynamic inteRFacing problems _______________________________10
, u' o5 |4 O6 \2.3 IC Technology and Signal Integrity _____________________________________12
9 J5 V7 k! X  J2.4 Speed and distance __________________________________________________14
2.5 Digital signals: Static interfacing _______________________________________15
2.6 Digital signals: Dynamic interfacing ____________________________________16
* W! A8 v. B9 v* e  P6 J$ |2.7 Review questions ___________________________________________________18
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3 Interconnection Models____________________________________________________20

! M& D3 Y/ G' s$ m( j3.1 Summary__________________________________________________________20
6 t: I" u' ~: o9 d) n1 @3.2 Reference model for interconnection analysis _____________________________20
! M6 Y+ R  N# t7 E! z) s7 x3.3 Receiver model_____________________________________________________21
" Q! ?( C: L- J/ D6 E3 k3.4 RC interconnection model ____________________________________________23
3.5 Parameters of the interconnection ______________________________________25
3.6 Refined models _____________________________________________________26
" ~; Y# _: N( r, j9 C3.7 Review question ____________________________________________________28

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4 Transmission Line Models _________________________________________________31

4.1 Summary__________________________________________________________31
4.2 Transmission line models _____________________________________________31
4.3 Loss-less transmission lines ___________________________________________32
9 C4 O# y/ X. Q9 S7 G  w4.4 Critical Length _____________________________________________________34
8 d1 u' e, f7 b; v8 P4.5 Reference transmission line model______________________________________35
4.6 Line driving _______________________________________________________36
/ e# \" n- G3 ~7 x2 Y" }4.7 Propagation and reflected waves _______________________________________37
4.8 A sample system____________________________________________________39
4.9 Review questions ___________________________________________________42
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PCB Designer’s SI Guide Page 2 Venkata

5 Analysis techniques _______________________________________________________45

5.1 Summary__________________________________________________________45
5.2 Transmission time and skew___________________________________________45
7 p0 T; w; }9 _: M8 O; V5.3 Effects of termination resistance _______________________________________46
1 F  w* u6 k% S( B8 ~; ~5.4 Lattice diagram _____________________________________________________48
5.5 Examples of Real Lines ______________________________________________49
0 F2 n7 L6 [) \% ^& L" v& f5.6 Simulation code ____________________________________________________51
3 u; k+ J8 g( h5 s0 f5.7 Examples of results__________________________________________________54
5.8 Review questions ___________________________________________________55
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6 Design guide for interconnection ____________________________________________57

6.1 Summary__________________________________________________________57
6.2 Incident wave switching ______________________________________________57
6.3 Effects of capacitive loading __________________________________________58
6.4 Termination circuits _________________________________________________59
6.4.1 Passive termination______________________________________________60
# Y4 l1 ?( \0 C6.4.2 Low power termination___________________________________________61
7 F" ~* Z7 P5 \: G9 V6.4.3 Active low power termination circuit. _______________________________61
8 A4 F4 @7 z) W4 p- S! ^6.5 Driving point-to-point lines ___________________________________________62
( C2 X* T0 ?$ N3 e  ?1 _5 [9 E6.6 Driving bused lines __________________________________________________64
: [! C0 l- d' f2 O6.7 Design guidelines ___________________________________________________67
6.8 Review questions ___________________________________________________67

snowwolfe

Signal Integrity in Digital Circuits ___________________________________________70
5 p5 M: `% z9 E& I% U5 j7.1 Crosstalk __________________________________________________________70
7.1.1 Summary______________________________________________________70
- Q6 O4 M+ m  }$ |7.2 Examples of signal integrity problems ___________________________________70
7.3 Simplified Model for Crosstalk Analysis _________________________________71
+ \6 G) ^/ h4 n5 ]7 A9 y; M& g7.4 Forward and backward crosstalk _______________________________________74
4 f. t: O4 H$ [0 f" W7.5 Examples__________________________________________________________76
( b0 O9 B: I2 B) J1 S. V# y7.6 Near-end and Far-end crosstalk ________________________________________80
! K6 x  @8 u+ R6 r  s* Q7.7 Review questions ___________________________________________________81


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8 Design Guide to Handle Crosstalk ___________________________________________85

4 E- |- _1 I8 E/ ]; b8 p$ M  b8 W8.1 Summary__________________________________________________________85
8.2 Effects of Crosstalk __________________________________________________85
8.3 Passive countermeasures _____________________________________________86
/ k  X: |* U0 d) z2 t* G8.4 Active Control of Crosstalk ___________________________________________92
, @5 P; k& F& ~) n0 ^1 s8.5 Review questions ___________________________________________________94
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9 Ground Bounce and Switching Noise_________________________________________97

9.1 Summary__________________________________________________________97
9.2 The totem pole Current Spike__________________________________________97
5 v: Q/ Z% M5 i9 f) e' {8 `* c9.3 Current flow in the output capacitance __________________________________100
9 p  v: K, S6 e4 v/ D: I6 k9.4 Total Ground Bounce _______________________________________________100
9.5 Review questions __________________________________________________105
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10 Design Guide for Ground & Power Distribution _____________________________107

+ y% c6 ~1 t2 `1 S10.1 Summary_________________________________________________________107

PCB Designer’s SI Guide Page 3 Venkata

* l& v+ |5 g  R) W8 P7 y, f1 Y10.2 Decoupling Capacitors ______________________________________________107
10.3 Placement of bypass Capacitors _______________________________________113
10.4 Ground and power distribution________________________________________114
/ k  N+ ]0 x* L2 l! {* K, i2 K6 c10.5 Clock distribution __________________________________________________115
8 R& g5 s1 y& x  o% A10.6 Review Questions __________________________________________________118
: z7 y" }; S, Q( I  n11 Laboratory Experience _________________________________________________120
11.1 Summary_________________________________________________________120
/ F/ T8 j/ a/ ~! _9 s. {7 K11.2 Aim of the experience_______________________________________________120
11.3 Generator Parameters _______________________________________________122
9 ^/ A, R  V8 [8 I9 g11.4 Cable Parameters __________________________________________________123
; u  S$ h& X7 E4 ]- [, p4 m11.5 Mismatch at driver and at termination __________________________________124
11.6 Capacitive Load ___________________________________________________125
11.7 7. Time-domain reflectometer ________________________________________127
11.8 Driving the line with logic devices _____________________________________128
12 SI Analysis Strategy____________________________________________________133
; K; I3 b1 O: {, c0 n1 x7 o12.1.1 A modern high-speed design methodology must involve the at least the following: ____________________________________________________________133
12.2 POSSIBLE HIGH-SPEED DESIGN APPROACHES ______________________133
12.2.1 There are two fundamental types of conditions that need to be considered for solution space analysis:__________________________________________________134
12.3 SOLUTION SPACE ANALYSIS _____________________________________135
12.3.1
2 M6 ?8 w3 G' \3 f  [9 \STEP 1 — DEFINING THE INITIAL TOPOLOGY __________________135
12.3.2 STEP 2 — DEFINE MANUFACTURING TOLERANCES AND THEIR MIN/MAX VALUES ___________________________________________________135
, c" v  D7 _4 L) X- n+ G12.3.3
, e% S- {1 M& x) ?& uSTEP 3 — DEFINE THE STARTING POINT FOR DESIGN VARIANCES 136
12.3.4
STEP 4 — SET UP AND RUN A NUMBER OF SIMULATION CASES _136
2 F( z/ k0 E3 [: A  \# {12.3.5 STEP 5 — EXAMINE THE SIMULATION RESULTS, IDENTIFY WHICH CASES FAILED AND WHY ____________________________________________136
12.3.6 STEP 6 — ADAPT THE TOPOLOGY AND DESIGN RULES AS APPROPRIATE _______________________________________________________137
: P8 h$ ]6 ?" i2 a/ _12.3.7 STEP 7 — REPEAT STEPS 4-6 UNTIL THE TOPOLOGY CONVERGES ON A SET OF VALUES THAT PASS FOR ALL CASES ANALYZED __________137
12.3.8
STEP 8 — DERIVE DESIGN RULES FOR THE TARGET CAD SYSTEM 137
12.3.9 STEP 9 — DRIVE THE CAD RULES INTO THE CAD DATABASE, AND USE THEM TO DRIVE THE PLACEMENT/ROUTING PROCESSES ___________138
12.3.10 STEP 10 — POST LAYOUT SI ANALYSIS ______________________139
12.4 CONCLUSION____________________________________________________139
13 Glossary _____________________________________________________________141
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PCB Designer’s SI Guide Page 4Venkata

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