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本帖最后由 金志峰 于 2020-11-5 01:02 编辑 , M7 T: c$ T# ]; F) p
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Hotfix_SPB17.40.012: U1 g8 f0 S a! _% `8 @% H
5 M& u; L4 n! [1 X百度云链接: https://pan.baidu.com/s/1udP4SQr7pERhzD2tHlMuCA 提取码: a6q4 $ x( o4 q# F: o
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Fixed CCRs: SPB 17.4 HF012 - Date: 10-30-2020
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* o Y2 n* O) W# k) `0 u/ o2324284 ADV_PKG_ROUTER OTHER APR fails to route and does not use the BBVias.
8 w5 O% r5 r# {2346605 ADW ADWSERVER Librarian license incorrectly checked out by data nodes during LiveBOM creation
' B% ]( h+ c0 q1 ~1 P/ A2317952 allegro_EDITOR 3D_CANVAS Allegro 3D Canvas does not show STEP models placed on paste mask correctly
! k8 S9 n' J! ^' Y1 W8 T2192222 ALLEGRO_EDITOR DFM Allegro PCB Editor crashed during check 'Mask' with the setting of 'Via Partially Covered With Mask Opening'; E8 ]& v7 U3 }8 |# ?9 f
2197203 ALLEGRO_EDITOR DFM Wrong alert on Soldermask sliver checking& v8 d% g3 l( g1 d
2280806 ALLEGRO_EDITOR DFM Importing netlist results in error related to illegal subclass (SPMHNI-234)
* e5 q$ R+ L) v. i/ @2262559 ALLEGRO_EDITOR DRC_CONSTR Copper Features: Minimum Acid traps Angle gives false DRC# Q( U# x4 {0 Y& s, W
2319385 ALLEGRO_EDITOR INTERACTIV Find by Query for Via structures is not working with Symbol field filter
; H, I# [, w7 @1 b* i- c t) E8 Y. M2279179 ALLEGRO_EDITOR PLOTTING File> Plot ignores the printer setup properties and always prints in Portrait format.
2 w! M- A0 f4 f3 E2 }8 q3 S$ [2306419 ALLEGRO_EDITOR PLOTTING File -> Plot -> Properties only accepts 'Portrait' and not 'Landscape'+ O2 u- `2 w; }$ Z( K8 V0 z
2333930 ALLEGRO_EDITOR PLOTTING The File> Plot always prints PCB in portrait
. z7 c2 w2 n8 @' U9 \/ u% v* F. ?2327088 ALLEGRO_EDITOR SHAPE Design Sync gets a SAV file reported but there is no information about the cause of the problem in netrev.lst9 d+ K% p5 z# J/ F3 N8 V5 e$ U1 d
2331947 ALLEGRO_EDITOR SHAPE When adding shape, pressing the 'Shift' key ends the process) K* r( m' Q* d- P; x4 Y+ `
2339008 ALLEGRO_EDITOR STREAM_IF Stream import view layers give error
+ \' q# ^. e3 Z" O- X5 @2328322 APD DRC_CONSTRAIN Database getting corrupted during artwork creation even after running DBDoctor.
9 B ?) e0 t: E0 V( n; z8 |7 P: Q2280535 APD REPORTS About the missing fillets report result: Ignore fillets not generated inside via regular pad area
' V: c5 J# |: z% p9 v2323629 CAPTURE OTHER Product unusable with DSN file: Operations have significant delays and application stops responding
6 n0 p" l* |5 a7 x$ x. U2261147 CONSTRAINT_MGR ANALYSIS Setting "Mechanical drill hole to conductor spacing" does not flag DRC
4 D* t7 L( \6 c- S+ k* D, c2330712 CONSTRAINT_MGR DATABASE Physical Constraints Set value cannot be modified
f& e2 _0 S: V& a( P, p2333755 CONSTRAINT_MGR SCHEM_FTB CM simplified out-of-sync pop-up form has clipped text* W# [3 M) h* J9 h
2235714 CONSTRAINT_MGR UI_FORMS Using the 'Change all design unit attributes…' pop-up menu option changes only the Min BB Via Gap value
: j7 b) a: j/ w" j$ X8 n" t9 M2288109 CONSTRAINT_MGR UI_FORMS Column sort is not working for match group/ z) [; i" A% ]4 S. q' f
2306092 CONSTRAINT_MGR UI_FORMS Display Constraints shows empty constraints in Constraint Manager- f( R! T6 u0 @, ~) b# v, o) V
2332795 CONSTRAINT_MGR UI_FORMS CMGR Worksheet colums are not sorted as per the columns definitions. E- J3 D1 H- u# E0 K5 }8 p" W
2326995 PCB_LIBRARIAN SYMBOL_EDITOR Graphics and pin number locations are incorrect
# }. r5 ?1 `3 C9 ~# v$ G) Y3 Q' g2280766 Pspice MODELEDITOR Error while converting Verilog-A model
. d# j5 ?# D/ I2285008 PSPICE MODELEDITOR Model Editor crashes if file name does not match with IBIS model file name* y7 H0 U" @) `( _6 h! h- _. I
2346048 PULSE ADHOC Importing or File New Block as a designer working on a design that has been shared does not work) i1 y9 e3 g; f. P. i8 ]+ e) X
2346643 PULSE ADHOC System Capture crashes when adding a part
9 j- g5 q! x2 S/ E0 u1 [2214054 PULSE UNIFIED_SEARC Unified Search does not honor operating system HTTP proxy settings
/ J, B9 r {+ S" o: }' l5 b7 j! S0 e2325635 PULSE UNIFIED_SEARC Errors in Unified Search (vista) using customer database: T0 y b) [# T! E4 a$ ^
2326089 PULSE UNIFIED_SEARC Unified search does not show EDM parts and gives error (SPPSUN-1)3 H" c! W5 p2 _. @
2329750 PULSE VERSION_ON_SA Live BOM data disappearing from migrated DE-HDL design with variants
7 Y* v9 M! }/ N$ x2 Y2319690 SIP_LAYOUT EDIT_ETCH Allegro SiP Layout XL - Auto-I Breakout Closest End excessive run time: Takes long time to complete
- _* w U3 K5 S V& |' D, l2320336 SIP_LAYOUT EDIT_ETCH Auto-Interactive Pin Swapping /Auto Breakout cannot route in design
I! r# U) B% u) J& C& w2333679 SIP_LAYOUT INTERACTIVE Add Offset Via Angle Field* ? q$ s) d$ T
2344732 SYSTEM_CAPTURE DESIGN_CORRUP Page cannot be loaded because the design database is corrupt; B1 s: Q Z/ O7 U, C' X
2342258 SYSTEM_CAPTURE MISCELLANEOUS System Capture is impacting PCB Editor GUI Readability by Setting QT_SCALE_FACTOR
4 v. b% ~8 G1 b: H. T" \2337610 SYSTEM_CAPTURE PART_MANAGER System Capture crashes when updating a part with changed PACK_TYPE and Symbol" H2 P$ [; Z, y7 T% U
2341550 SYSTEM_CAPTURE VERSION_ON_SA Projects migrated from HotFix 002 to HotFix 010 have slow peRFormance
" N) ]7 @5 H) m1 Z" _ c$ E2341591 SYSTEM_CAPTURE WIRING Moving wire segments still leaves odd pieces of wires, _2 |! E5 i f
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发表于 2020-11-5 00:58
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