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本帖最后由 金志峰 于 2020-11-5 01:02 编辑
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8 B9 @. a& I) l% R: j1 e5 q# hHotfix_SPB17.40.012
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) S( M5 o1 Z9 R, d! B% Z百度云链接: https://pan.baidu.com/s/1udP4SQr7pERhzD2tHlMuCA 提取码: a6q4 ! O2 Y) D( }: N2 }; b" ^! J! X
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# n% ` Z- H" J4 {( W! [Fixed CCRs: SPB 17.4 HF012 - Date: 10-30-2020; Z1 x" U$ k8 l, C
' d( O3 A. a3 D( H4 O: s0 a$ p=============================================================
/ }: Y P) e6 F$ H4 x1 ?& pCCRID Product ProductLevel2 Title
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2324284 ADV_PKG_ROUTER OTHER APR fails to route and does not use the BBVias.
6 V" ^- p$ L6 B1 a. Z, N! ^8 T2346605 ADW ADWSERVER Librarian license incorrectly checked out by data nodes during LiveBOM creation
- M8 x6 V; \' n5 [4 R2317952 allegro_EDITOR 3D_CANVAS Allegro 3D Canvas does not show STEP models placed on paste mask correctly$ p. A; @5 P Y. V; z/ `0 o# C" z! p
2192222 ALLEGRO_EDITOR DFM Allegro PCB Editor crashed during check 'Mask' with the setting of 'Via Partially Covered With Mask Opening'
" d2 V, o& y& }7 z5 x- ^0 A2 d9 m2197203 ALLEGRO_EDITOR DFM Wrong alert on Soldermask sliver checking
' i% Y! n) B, Q2280806 ALLEGRO_EDITOR DFM Importing netlist results in error related to illegal subclass (SPMHNI-234). i. T/ c& ?3 w; M* x
2262559 ALLEGRO_EDITOR DRC_CONSTR Copper Features: Minimum Acid traps Angle gives false DRC8 I' C% @+ Z7 x1 e; V" Y
2319385 ALLEGRO_EDITOR INTERACTIV Find by Query for Via structures is not working with Symbol field filter
' d0 C L5 W z9 j" C9 |2279179 ALLEGRO_EDITOR PLOTTING File> Plot ignores the printer setup properties and always prints in Portrait format.
7 p, h$ Z4 n4 w+ y/ G# [5 N8 P2306419 ALLEGRO_EDITOR PLOTTING File -> Plot -> Properties only accepts 'Portrait' and not 'Landscape'
9 K+ F& w3 J5 H6 d8 Y$ |( q2333930 ALLEGRO_EDITOR PLOTTING The File> Plot always prints PCB in portrait/ {9 ^$ a! n# V/ U3 y8 `, e! o
2327088 ALLEGRO_EDITOR SHAPE Design Sync gets a SAV file reported but there is no information about the cause of the problem in netrev.lst5 G: O4 x6 |, m0 t. a
2331947 ALLEGRO_EDITOR SHAPE When adding shape, pressing the 'Shift' key ends the process5 b+ F4 b7 p! {2 M' S) d
2339008 ALLEGRO_EDITOR STREAM_IF Stream import view layers give error$ A, ~6 j- [3 X2 I
2328322 APD DRC_CONSTRAIN Database getting corrupted during artwork creation even after running DBDoctor.
$ ^, n0 ^ f/ B* m m$ s2280535 APD REPORTS About the missing fillets report result: Ignore fillets not generated inside via regular pad area
7 y* Y; H: \, ~; q* s/ Q2323629 CAPTURE OTHER Product unusable with DSN file: Operations have significant delays and application stops responding1 `' Y; E4 H( F* b
2261147 CONSTRAINT_MGR ANALYSIS Setting "Mechanical drill hole to conductor spacing" does not flag DRC- q4 L0 t, m+ Y6 f) g9 K
2330712 CONSTRAINT_MGR DATABASE Physical Constraints Set value cannot be modified
4 X$ }5 d' C( C6 K6 W4 M2333755 CONSTRAINT_MGR SCHEM_FTB CM simplified out-of-sync pop-up form has clipped text
- j! q) c: q! }' _; C2 `2235714 CONSTRAINT_MGR UI_FORMS Using the 'Change all design unit attributes…' pop-up menu option changes only the Min BB Via Gap value0 g" z9 u1 j4 N/ \ G6 ^$ ]
2288109 CONSTRAINT_MGR UI_FORMS Column sort is not working for match group& H# O; v# D) \4 o
2306092 CONSTRAINT_MGR UI_FORMS Display Constraints shows empty constraints in Constraint Manager
% ~; \0 k* u$ G, d. T+ n' n! s1 Y2332795 CONSTRAINT_MGR UI_FORMS CMGR Worksheet colums are not sorted as per the columns definitions' q. F) g8 w5 [: K
2326995 PCB_LIBRARIAN SYMBOL_EDITOR Graphics and pin number locations are incorrect
5 O* Z* i, D4 ]& [0 _- g2280766 Pspice MODELEDITOR Error while converting Verilog-A model
( u: l) {: p+ v2285008 PSPICE MODELEDITOR Model Editor crashes if file name does not match with IBIS model file name) T0 o$ F) b" D- B1 G8 V
2346048 PULSE ADHOC Importing or File New Block as a designer working on a design that has been shared does not work
% o; G9 m7 s$ b. n2346643 PULSE ADHOC System Capture crashes when adding a part
1 O/ C6 D( f8 B1 q& D2214054 PULSE UNIFIED_SEARC Unified Search does not honor operating system HTTP proxy settings7 f" c4 V( g) M9 ^ l% z s' r+ @
2325635 PULSE UNIFIED_SEARC Errors in Unified Search (vista) using customer database
, |- w. J c7 C9 l$ j2326089 PULSE UNIFIED_SEARC Unified search does not show EDM parts and gives error (SPPSUN-1)
% `, C* ^$ o* w7 ^2329750 PULSE VERSION_ON_SA Live BOM data disappearing from migrated DE-HDL design with variants" L; n0 g/ S8 j4 e2 f' d' K# B
2319690 SIP_LAYOUT EDIT_ETCH Allegro SiP Layout XL - Auto-I Breakout Closest End excessive run time: Takes long time to complete2 ]- G5 j+ Z% E6 Q
2320336 SIP_LAYOUT EDIT_ETCH Auto-Interactive Pin Swapping /Auto Breakout cannot route in design3 W8 V `6 y6 {" U4 W p/ y8 ~
2333679 SIP_LAYOUT INTERACTIVE Add Offset Via Angle Field$ {! l* @3 }- Y2 i- x- t
2344732 SYSTEM_CAPTURE DESIGN_CORRUP Page cannot be loaded because the design database is corrupt( N4 x7 L4 q+ u
2342258 SYSTEM_CAPTURE MISCELLANEOUS System Capture is impacting PCB Editor GUI Readability by Setting QT_SCALE_FACTOR7 l2 E3 e% j# g8 _( s2 F. k3 O0 j5 Y
2337610 SYSTEM_CAPTURE PART_MANAGER System Capture crashes when updating a part with changed PACK_TYPE and Symbol C/ C# C! i2 O3 H/ s
2341550 SYSTEM_CAPTURE VERSION_ON_SA Projects migrated from HotFix 002 to HotFix 010 have slow peRFormance. Z# Q1 `, T7 F
2341591 SYSTEM_CAPTURE WIRING Moving wire segments still leaves odd pieces of wires
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发表于 2020-11-5 00:58
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