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本帖最后由 金志峰 于 2020-11-5 01:02 编辑
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! f! }5 w3 v/ z0 a* l, G5 ~ _( V5 f6 V# OHotfix_SPB17.40.012
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Y! x# W ?1 S; b/ d- k+ ]百度云链接: https://pan.baidu.com/s/1udP4SQr7pERhzD2tHlMuCA 提取码: a6q4 . w, A9 V2 v9 F v
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Fixed CCRs: SPB 17.4 HF012 - Date: 10-30-2020
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CCRID Product ProductLevel2 Title
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; |0 {. l4 r8 j5 \/ L" w2324284 ADV_PKG_ROUTER OTHER APR fails to route and does not use the BBVias.1 V4 q2 \/ E' M( U+ [& I0 w+ k! U
2346605 ADW ADWSERVER Librarian license incorrectly checked out by data nodes during LiveBOM creation
, U& _4 V& s+ r- x4 O# U u+ ~2317952 allegro_EDITOR 3D_CANVAS Allegro 3D Canvas does not show STEP models placed on paste mask correctly
0 Y' A6 l- W) o" ?! ^# X2192222 ALLEGRO_EDITOR DFM Allegro PCB Editor crashed during check 'Mask' with the setting of 'Via Partially Covered With Mask Opening'
3 R4 A2 r9 u m S7 a2197203 ALLEGRO_EDITOR DFM Wrong alert on Soldermask sliver checking6 M1 q* S7 V3 i
2280806 ALLEGRO_EDITOR DFM Importing netlist results in error related to illegal subclass (SPMHNI-234)
' Q4 f- Y7 H8 V; r6 o: x6 w2262559 ALLEGRO_EDITOR DRC_CONSTR Copper Features: Minimum Acid traps Angle gives false DRC+ x, h$ e, W b" I* o- l
2319385 ALLEGRO_EDITOR INTERACTIV Find by Query for Via structures is not working with Symbol field filter/ \- t1 @% G" Z% T) d
2279179 ALLEGRO_EDITOR PLOTTING File> Plot ignores the printer setup properties and always prints in Portrait format.
9 P- v9 {0 C; {5 ^1 ]! ?% {9 A! [2306419 ALLEGRO_EDITOR PLOTTING File -> Plot -> Properties only accepts 'Portrait' and not 'Landscape'6 F6 `6 x/ D5 P
2333930 ALLEGRO_EDITOR PLOTTING The File> Plot always prints PCB in portrait( C2 `! D6 F" G8 M
2327088 ALLEGRO_EDITOR SHAPE Design Sync gets a SAV file reported but there is no information about the cause of the problem in netrev.lst4 r8 d+ ]. N$ {3 I0 n$ [+ w
2331947 ALLEGRO_EDITOR SHAPE When adding shape, pressing the 'Shift' key ends the process
- V) q( L* [7 U& }6 t% r- \, K2339008 ALLEGRO_EDITOR STREAM_IF Stream import view layers give error% H7 D; X& T2 Y O) W* `
2328322 APD DRC_CONSTRAIN Database getting corrupted during artwork creation even after running DBDoctor.
+ @8 n9 a( U' @5 G6 ~! {9 }2280535 APD REPORTS About the missing fillets report result: Ignore fillets not generated inside via regular pad area( O2 @. C1 H; F3 [4 p1 S
2323629 CAPTURE OTHER Product unusable with DSN file: Operations have significant delays and application stops responding6 ]' G( }0 z; P, T5 j( e* H
2261147 CONSTRAINT_MGR ANALYSIS Setting "Mechanical drill hole to conductor spacing" does not flag DRC2 g5 t; O h |
2330712 CONSTRAINT_MGR DATABASE Physical Constraints Set value cannot be modified9 D- A+ |2 i K P3 J
2333755 CONSTRAINT_MGR SCHEM_FTB CM simplified out-of-sync pop-up form has clipped text
7 W3 u9 T( ~9 V4 B7 D2235714 CONSTRAINT_MGR UI_FORMS Using the 'Change all design unit attributes…' pop-up menu option changes only the Min BB Via Gap value( C$ F3 H! w7 ^& o
2288109 CONSTRAINT_MGR UI_FORMS Column sort is not working for match group
& z/ N; r: i* F; s) }5 X& G2306092 CONSTRAINT_MGR UI_FORMS Display Constraints shows empty constraints in Constraint Manager
0 E- R1 A9 u$ e5 A/ g7 d! \2332795 CONSTRAINT_MGR UI_FORMS CMGR Worksheet colums are not sorted as per the columns definitions
( C) s% g% V$ p" |4 c2326995 PCB_LIBRARIAN SYMBOL_EDITOR Graphics and pin number locations are incorrect
Z+ s: w. J- s$ r2280766 Pspice MODELEDITOR Error while converting Verilog-A model6 [; s& Y$ X5 U* D' J6 x
2285008 PSPICE MODELEDITOR Model Editor crashes if file name does not match with IBIS model file name
$ O6 y4 P: e2 U P* f+ y* w2346048 PULSE ADHOC Importing or File New Block as a designer working on a design that has been shared does not work" q) y' k! p) D0 h9 v6 T, F
2346643 PULSE ADHOC System Capture crashes when adding a part
: p" Z& m7 k% G2214054 PULSE UNIFIED_SEARC Unified Search does not honor operating system HTTP proxy settings
, _" W' I' i6 U3 l* q2325635 PULSE UNIFIED_SEARC Errors in Unified Search (vista) using customer database: O) ^! H O9 e+ [9 I9 t
2326089 PULSE UNIFIED_SEARC Unified search does not show EDM parts and gives error (SPPSUN-1)
n9 {5 M3 P( h0 ?2329750 PULSE VERSION_ON_SA Live BOM data disappearing from migrated DE-HDL design with variants
+ n8 e+ i j: @" k' `4 N' Y9 v2319690 SIP_LAYOUT EDIT_ETCH Allegro SiP Layout XL - Auto-I Breakout Closest End excessive run time: Takes long time to complete
4 `6 u/ z8 m' O7 J2320336 SIP_LAYOUT EDIT_ETCH Auto-Interactive Pin Swapping /Auto Breakout cannot route in design; _- L* V! I* r3 f$ U/ _
2333679 SIP_LAYOUT INTERACTIVE Add Offset Via Angle Field
! O. C1 l& d5 ^9 H2344732 SYSTEM_CAPTURE DESIGN_CORRUP Page cannot be loaded because the design database is corrupt0 F& Q, x6 ^; k+ X( P
2342258 SYSTEM_CAPTURE MISCELLANEOUS System Capture is impacting PCB Editor GUI Readability by Setting QT_SCALE_FACTOR! Z& t5 t' {0 Q/ z7 \* Q. c! ]2 L* q8 X
2337610 SYSTEM_CAPTURE PART_MANAGER System Capture crashes when updating a part with changed PACK_TYPE and Symbol$ [7 t4 }& M! `5 W0 k l$ s
2341550 SYSTEM_CAPTURE VERSION_ON_SA Projects migrated from HotFix 002 to HotFix 010 have slow peRFormance+ }' w* h5 C$ I) \- \6 h
2341591 SYSTEM_CAPTURE WIRING Moving wire segments still leaves odd pieces of wires) r9 D# u0 e" ~8 }! W
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发表于 2020-11-5 00:58
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