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本帖最后由 金志峰 于 2020-11-5 01:02 编辑 9 p) \3 {$ y( M$ ~7 N
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Hotfix_SPB17.40.012
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6 Z9 W4 r: K" {( M" a$ C" U S1 O3 E百度云链接: https://pan.baidu.com/s/1udP4SQr7pERhzD2tHlMuCA 提取码: a6q4 5 M. Z2 E% y/ Z
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Fixed CCRs: SPB 17.4 HF012 - Date: 10-30-2020 ~+ Y( x- S# X+ e# f3 x
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CCRID Product ProductLevel2 Title; J; ~; W& E0 Y" [
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2324284 ADV_PKG_ROUTER OTHER APR fails to route and does not use the BBVias.5 r, j+ i7 L) s) E; }& J5 r8 j
2346605 ADW ADWSERVER Librarian license incorrectly checked out by data nodes during LiveBOM creation
1 u5 _1 Z" K$ k$ E3 M; r: ]2317952 allegro_EDITOR 3D_CANVAS Allegro 3D Canvas does not show STEP models placed on paste mask correctly
) v& V3 x# ]: d6 ^! I. ]5 c3 j2192222 ALLEGRO_EDITOR DFM Allegro PCB Editor crashed during check 'Mask' with the setting of 'Via Partially Covered With Mask Opening'
8 w$ z9 s9 m' @1 l; y2197203 ALLEGRO_EDITOR DFM Wrong alert on Soldermask sliver checking
" D3 j0 r% d, ?" |0 V$ h) G2280806 ALLEGRO_EDITOR DFM Importing netlist results in error related to illegal subclass (SPMHNI-234)
: }4 J' ~9 ^; C) ]: \/ p" c+ F/ r2262559 ALLEGRO_EDITOR DRC_CONSTR Copper Features: Minimum Acid traps Angle gives false DRC
' k8 A4 u; r9 K- i' s, t2319385 ALLEGRO_EDITOR INTERACTIV Find by Query for Via structures is not working with Symbol field filter& D( P4 o- f- p) w1 E5 ^" j
2279179 ALLEGRO_EDITOR PLOTTING File> Plot ignores the printer setup properties and always prints in Portrait format.2 X) p2 g0 O8 T- m3 P* e3 h
2306419 ALLEGRO_EDITOR PLOTTING File -> Plot -> Properties only accepts 'Portrait' and not 'Landscape'5 e" u% I9 B3 v6 r V3 e, K
2333930 ALLEGRO_EDITOR PLOTTING The File> Plot always prints PCB in portrait
0 [" ]6 C% c& @6 i& e e0 y) B2327088 ALLEGRO_EDITOR SHAPE Design Sync gets a SAV file reported but there is no information about the cause of the problem in netrev.lst
; W" U8 f+ e$ @: E) H7 F5 n2331947 ALLEGRO_EDITOR SHAPE When adding shape, pressing the 'Shift' key ends the process
4 {+ E3 H! A: R3 a( } o) T2339008 ALLEGRO_EDITOR STREAM_IF Stream import view layers give error
7 Y7 e' s( B5 v4 z( Q/ ^" V3 {2328322 APD DRC_CONSTRAIN Database getting corrupted during artwork creation even after running DBDoctor.4 a/ o* d; g: c- |1 a8 u
2280535 APD REPORTS About the missing fillets report result: Ignore fillets not generated inside via regular pad area
7 b0 H& q$ p+ i P- {) T2323629 CAPTURE OTHER Product unusable with DSN file: Operations have significant delays and application stops responding6 q! `- S1 S) k# @- L* \
2261147 CONSTRAINT_MGR ANALYSIS Setting "Mechanical drill hole to conductor spacing" does not flag DRC
2 ]9 e2 M$ D: \. b- d* p) A: u2330712 CONSTRAINT_MGR DATABASE Physical Constraints Set value cannot be modified
- G* x5 l1 Q8 ^2 Q8 G6 f$ u2333755 CONSTRAINT_MGR SCHEM_FTB CM simplified out-of-sync pop-up form has clipped text
$ m; x8 U* P. L: f. L2235714 CONSTRAINT_MGR UI_FORMS Using the 'Change all design unit attributes…' pop-up menu option changes only the Min BB Via Gap value) e) N8 X: }1 o# J; x. h! Y
2288109 CONSTRAINT_MGR UI_FORMS Column sort is not working for match group' j6 X/ }' U" [! G4 l, l9 Q# b$ D
2306092 CONSTRAINT_MGR UI_FORMS Display Constraints shows empty constraints in Constraint Manager$ n4 t* s/ v( z8 r S
2332795 CONSTRAINT_MGR UI_FORMS CMGR Worksheet colums are not sorted as per the columns definitions5 F' D( d$ n# n! i( h9 c: m4 P, J
2326995 PCB_LIBRARIAN SYMBOL_EDITOR Graphics and pin number locations are incorrect
& r- M+ n* d! V: i2280766 Pspice MODELEDITOR Error while converting Verilog-A model3 p- [0 @2 W$ d1 i" c# b
2285008 PSPICE MODELEDITOR Model Editor crashes if file name does not match with IBIS model file name
3 s+ e& p) j5 a( N2346048 PULSE ADHOC Importing or File New Block as a designer working on a design that has been shared does not work
4 b3 y& F5 n) U7 v2 g& q( q2346643 PULSE ADHOC System Capture crashes when adding a part
# [; P5 y1 B$ ?3 h, B6 U2214054 PULSE UNIFIED_SEARC Unified Search does not honor operating system HTTP proxy settings4 `( o0 w4 I. R# ^, T2 A
2325635 PULSE UNIFIED_SEARC Errors in Unified Search (vista) using customer database4 J: g; v2 r- g" l) [
2326089 PULSE UNIFIED_SEARC Unified search does not show EDM parts and gives error (SPPSUN-1)
, G0 _+ M) F4 ]4 R9 _2329750 PULSE VERSION_ON_SA Live BOM data disappearing from migrated DE-HDL design with variants
1 \7 `! `# Y: E. R6 @2319690 SIP_LAYOUT EDIT_ETCH Allegro SiP Layout XL - Auto-I Breakout Closest End excessive run time: Takes long time to complete
& A' d3 {; E6 D2320336 SIP_LAYOUT EDIT_ETCH Auto-Interactive Pin Swapping /Auto Breakout cannot route in design8 U7 y8 u( g2 t7 n0 B3 D
2333679 SIP_LAYOUT INTERACTIVE Add Offset Via Angle Field
. D/ K3 o3 K; s* i2344732 SYSTEM_CAPTURE DESIGN_CORRUP Page cannot be loaded because the design database is corrupt! V7 Y4 f7 g9 d, @1 ~% L6 g
2342258 SYSTEM_CAPTURE MISCELLANEOUS System Capture is impacting PCB Editor GUI Readability by Setting QT_SCALE_FACTOR
( \! G, \9 c7 N+ Z2337610 SYSTEM_CAPTURE PART_MANAGER System Capture crashes when updating a part with changed PACK_TYPE and Symbol
/ T* m: U0 P0 }+ n( y2341550 SYSTEM_CAPTURE VERSION_ON_SA Projects migrated from HotFix 002 to HotFix 010 have slow peRFormance7 k7 b0 y9 a* l( C# ~3 u) v
2341591 SYSTEM_CAPTURE WIRING Moving wire segments still leaves odd pieces of wires' c" l. _; ^' q6 W5 I7 L
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发表于 2020-11-5 00:58
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