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本帖最后由 金志峰 于 2020-11-5 01:02 编辑
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Hotfix_SPB17.40.012
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9 c7 l+ r6 U1 D4 L7 M* }百度云链接: https://pan.baidu.com/s/1udP4SQr7pERhzD2tHlMuCA 提取码: a6q4
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Fixed CCRs: SPB 17.4 HF012 - Date: 10-30-2020' [: x" ~$ E6 y! M. [8 F
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$ \. L) D7 E' R: kCCRID Product ProductLevel2 Title: ~8 H0 G# [" a# K
========================================================================
* z' ^$ u. Z, k& d+ Q7 T2324284 ADV_PKG_ROUTER OTHER APR fails to route and does not use the BBVias.
. u9 y2 F9 S% G. z4 y2346605 ADW ADWSERVER Librarian license incorrectly checked out by data nodes during LiveBOM creation5 G+ K" ^! F' f+ _* w
2317952 allegro_EDITOR 3D_CANVAS Allegro 3D Canvas does not show STEP models placed on paste mask correctly
: L! Y' z, C. s5 ]: [' d2192222 ALLEGRO_EDITOR DFM Allegro PCB Editor crashed during check 'Mask' with the setting of 'Via Partially Covered With Mask Opening'
9 L3 n/ d/ K5 E5 i3 V2197203 ALLEGRO_EDITOR DFM Wrong alert on Soldermask sliver checking$ t( b2 @3 ~5 J! z, j' S
2280806 ALLEGRO_EDITOR DFM Importing netlist results in error related to illegal subclass (SPMHNI-234)
$ e( c! } o2 w: ^4 Y7 b0 [- ~+ y2262559 ALLEGRO_EDITOR DRC_CONSTR Copper Features: Minimum Acid traps Angle gives false DRC
Z6 w* r5 r3 b) ]2319385 ALLEGRO_EDITOR INTERACTIV Find by Query for Via structures is not working with Symbol field filter
8 I2 D7 Y' k+ V) o( ~# v2279179 ALLEGRO_EDITOR PLOTTING File> Plot ignores the printer setup properties and always prints in Portrait format.
; k8 n/ m1 Y N! C2306419 ALLEGRO_EDITOR PLOTTING File -> Plot -> Properties only accepts 'Portrait' and not 'Landscape'
$ P. V" w4 K" S. Y9 s( B& A, I2333930 ALLEGRO_EDITOR PLOTTING The File> Plot always prints PCB in portrait
1 Z( i2 \ Y) V; e4 O f2327088 ALLEGRO_EDITOR SHAPE Design Sync gets a SAV file reported but there is no information about the cause of the problem in netrev.lst; f, P; ?- k: G0 T7 u- L1 G) t& G
2331947 ALLEGRO_EDITOR SHAPE When adding shape, pressing the 'Shift' key ends the process
; `- {9 t1 ?, [$ L7 Y2 o* R) u0 U1 m2339008 ALLEGRO_EDITOR STREAM_IF Stream import view layers give error+ j6 y. ?4 g+ b9 L
2328322 APD DRC_CONSTRAIN Database getting corrupted during artwork creation even after running DBDoctor.
, S1 u! W! n/ D `6 g, k/ x+ ?9 o2280535 APD REPORTS About the missing fillets report result: Ignore fillets not generated inside via regular pad area
% f) P4 v d9 Z- i& W2323629 CAPTURE OTHER Product unusable with DSN file: Operations have significant delays and application stops responding. Q- ~9 C, k2 W
2261147 CONSTRAINT_MGR ANALYSIS Setting "Mechanical drill hole to conductor spacing" does not flag DRC
# Z. R3 ]+ e; L" v2 n6 ]0 t! q2330712 CONSTRAINT_MGR DATABASE Physical Constraints Set value cannot be modified
8 Y% U% \0 O$ t+ P1 o2333755 CONSTRAINT_MGR SCHEM_FTB CM simplified out-of-sync pop-up form has clipped text
& l$ i, Y- c$ v5 ^, ?+ p$ c, _2235714 CONSTRAINT_MGR UI_FORMS Using the 'Change all design unit attributes…' pop-up menu option changes only the Min BB Via Gap value( `* M# R: c* ^4 t" w n/ T- F$ J
2288109 CONSTRAINT_MGR UI_FORMS Column sort is not working for match group
: `% q% a. k k- @& z) u2306092 CONSTRAINT_MGR UI_FORMS Display Constraints shows empty constraints in Constraint Manager
2 O5 ]$ ?0 O$ |. V0 ^& x5 k2332795 CONSTRAINT_MGR UI_FORMS CMGR Worksheet colums are not sorted as per the columns definitions
: t+ K6 l5 K. E2326995 PCB_LIBRARIAN SYMBOL_EDITOR Graphics and pin number locations are incorrect0 {$ i5 {5 }- D& R( U+ e( ^
2280766 Pspice MODELEDITOR Error while converting Verilog-A model. i7 X& d$ y [) M) J% V
2285008 PSPICE MODELEDITOR Model Editor crashes if file name does not match with IBIS model file name
0 b: `/ D) y. Y% ]1 G! [% W2346048 PULSE ADHOC Importing or File New Block as a designer working on a design that has been shared does not work
9 H% T) G: v: ?" ?' T E2346643 PULSE ADHOC System Capture crashes when adding a part
, M( S- R" `8 J% K& ~+ S& d2214054 PULSE UNIFIED_SEARC Unified Search does not honor operating system HTTP proxy settings [1 J3 G! A0 a% n* R" q
2325635 PULSE UNIFIED_SEARC Errors in Unified Search (vista) using customer database
" o8 \/ G5 c+ R, A1 s) a2326089 PULSE UNIFIED_SEARC Unified search does not show EDM parts and gives error (SPPSUN-1)" ]/ p! }* D2 c' a9 N: N; ^
2329750 PULSE VERSION_ON_SA Live BOM data disappearing from migrated DE-HDL design with variants8 a8 B' A) K, b3 i; _0 G
2319690 SIP_LAYOUT EDIT_ETCH Allegro SiP Layout XL - Auto-I Breakout Closest End excessive run time: Takes long time to complete* c5 O; ` i a& y# S7 h
2320336 SIP_LAYOUT EDIT_ETCH Auto-Interactive Pin Swapping /Auto Breakout cannot route in design9 Q% `, ]8 C: s5 Y
2333679 SIP_LAYOUT INTERACTIVE Add Offset Via Angle Field/ T1 I- l }# V' X. Y; ?
2344732 SYSTEM_CAPTURE DESIGN_CORRUP Page cannot be loaded because the design database is corrupt& u3 R4 Q& A9 p2 H' v9 y5 Y4 \
2342258 SYSTEM_CAPTURE MISCELLANEOUS System Capture is impacting PCB Editor GUI Readability by Setting QT_SCALE_FACTOR
3 i- t+ _; m# n7 _, b/ o" A2337610 SYSTEM_CAPTURE PART_MANAGER System Capture crashes when updating a part with changed PACK_TYPE and Symbol
: \, S+ q7 l6 s- m2341550 SYSTEM_CAPTURE VERSION_ON_SA Projects migrated from HotFix 002 to HotFix 010 have slow peRFormance. W9 _2 s7 _5 M
2341591 SYSTEM_CAPTURE WIRING Moving wire segments still leaves odd pieces of wires; [1 {4 V9 W2 m$ Q# n: {
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发表于 2020-11-5 00:58
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