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本帖最后由 金志峰 于 2020-11-5 01:02 编辑
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百度云链接: https://pan.baidu.com/s/1udP4SQr7pERhzD2tHlMuCA 提取码: a6q4 4 q9 _( E; V7 T6 u* C; M( Q4 w
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. @+ h6 `4 K& z+ l" F* pFixed CCRs: SPB 17.4 HF012 - Date: 10-30-2020
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, w9 A5 S8 H/ A; }3 ~% tCCRID Product ProductLevel2 Title7 m# w, S* {5 ]( t9 |
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2324284 ADV_PKG_ROUTER OTHER APR fails to route and does not use the BBVias.
1 n3 S# C% V& i2 F) O2346605 ADW ADWSERVER Librarian license incorrectly checked out by data nodes during LiveBOM creation
) k3 v5 H+ V7 Y& y2317952 allegro_EDITOR 3D_CANVAS Allegro 3D Canvas does not show STEP models placed on paste mask correctly9 i% ]5 H4 @% w2 X* Z4 v! W
2192222 ALLEGRO_EDITOR DFM Allegro PCB Editor crashed during check 'Mask' with the setting of 'Via Partially Covered With Mask Opening': i! Q' @: l; M! s( o p
2197203 ALLEGRO_EDITOR DFM Wrong alert on Soldermask sliver checking$ l- J; L: Q. q( B+ P* Q
2280806 ALLEGRO_EDITOR DFM Importing netlist results in error related to illegal subclass (SPMHNI-234) j& j9 V3 l2 y' E
2262559 ALLEGRO_EDITOR DRC_CONSTR Copper Features: Minimum Acid traps Angle gives false DRC, u' `. E: P' x
2319385 ALLEGRO_EDITOR INTERACTIV Find by Query for Via structures is not working with Symbol field filter4 ]& v& J% @3 T% ]
2279179 ALLEGRO_EDITOR PLOTTING File> Plot ignores the printer setup properties and always prints in Portrait format.
1 {9 k7 T+ Q( a8 M+ `2 ~2306419 ALLEGRO_EDITOR PLOTTING File -> Plot -> Properties only accepts 'Portrait' and not 'Landscape'& H N: E: f. l$ S; I
2333930 ALLEGRO_EDITOR PLOTTING The File> Plot always prints PCB in portrait
# F$ `' X, N2 L4 p; _2327088 ALLEGRO_EDITOR SHAPE Design Sync gets a SAV file reported but there is no information about the cause of the problem in netrev.lst
; I% I% @1 q |. C4 p2331947 ALLEGRO_EDITOR SHAPE When adding shape, pressing the 'Shift' key ends the process4 j7 y4 [: Z- T7 t
2339008 ALLEGRO_EDITOR STREAM_IF Stream import view layers give error( ?5 h s* U+ }: W$ B
2328322 APD DRC_CONSTRAIN Database getting corrupted during artwork creation even after running DBDoctor.
9 h9 h2 k5 f, r7 ~2280535 APD REPORTS About the missing fillets report result: Ignore fillets not generated inside via regular pad area+ H+ l! K* ]% w
2323629 CAPTURE OTHER Product unusable with DSN file: Operations have significant delays and application stops responding
2 a) n3 V7 Y& t, b2261147 CONSTRAINT_MGR ANALYSIS Setting "Mechanical drill hole to conductor spacing" does not flag DRC1 a9 G& c! F( T& f
2330712 CONSTRAINT_MGR DATABASE Physical Constraints Set value cannot be modified: @* w& h+ d5 w+ r" v
2333755 CONSTRAINT_MGR SCHEM_FTB CM simplified out-of-sync pop-up form has clipped text. k( y, f) Y `3 R
2235714 CONSTRAINT_MGR UI_FORMS Using the 'Change all design unit attributes…' pop-up menu option changes only the Min BB Via Gap value4 {5 |7 [8 f5 \9 _* H1 p
2288109 CONSTRAINT_MGR UI_FORMS Column sort is not working for match group; D6 O: }3 }: f3 \/ f2 n/ q& [0 B
2306092 CONSTRAINT_MGR UI_FORMS Display Constraints shows empty constraints in Constraint Manager w( l, y, R$ H# J' ^# l
2332795 CONSTRAINT_MGR UI_FORMS CMGR Worksheet colums are not sorted as per the columns definitions J7 q0 R) U7 ~2 z8 h
2326995 PCB_LIBRARIAN SYMBOL_EDITOR Graphics and pin number locations are incorrect# }) j4 E F9 i/ D$ Y2 A/ O3 T& e
2280766 Pspice MODELEDITOR Error while converting Verilog-A model5 \! Y6 I n2 d! \' t1 O3 Q R3 M3 k
2285008 PSPICE MODELEDITOR Model Editor crashes if file name does not match with IBIS model file name/ p6 H, e& X9 Z: \/ e& Q
2346048 PULSE ADHOC Importing or File New Block as a designer working on a design that has been shared does not work
" T" }$ d' s( O( e. ~# w2346643 PULSE ADHOC System Capture crashes when adding a part$ ?% ^1 i' g: Q9 s
2214054 PULSE UNIFIED_SEARC Unified Search does not honor operating system HTTP proxy settings9 a/ Q+ p4 X0 H6 A+ A W+ o/ x
2325635 PULSE UNIFIED_SEARC Errors in Unified Search (vista) using customer database2 n4 @8 s% |# E( X# P2 `1 Y
2326089 PULSE UNIFIED_SEARC Unified search does not show EDM parts and gives error (SPPSUN-1)
l u3 s5 j+ g/ m6 q2329750 PULSE VERSION_ON_SA Live BOM data disappearing from migrated DE-HDL design with variants
6 C$ ?! [) S( Y( F: h2 I! F+ e2319690 SIP_LAYOUT EDIT_ETCH Allegro SiP Layout XL - Auto-I Breakout Closest End excessive run time: Takes long time to complete
5 F3 y$ p5 j* G" y. o! y2320336 SIP_LAYOUT EDIT_ETCH Auto-Interactive Pin Swapping /Auto Breakout cannot route in design+ r& }2 ^9 ]* G: r4 k b% i; z. v
2333679 SIP_LAYOUT INTERACTIVE Add Offset Via Angle Field
8 L: k, Y3 `% w% m2344732 SYSTEM_CAPTURE DESIGN_CORRUP Page cannot be loaded because the design database is corrupt* x7 T# Y5 p U8 D5 y
2342258 SYSTEM_CAPTURE MISCELLANEOUS System Capture is impacting PCB Editor GUI Readability by Setting QT_SCALE_FACTOR, F( l$ Y7 e* L/ Z5 R7 w0 [
2337610 SYSTEM_CAPTURE PART_MANAGER System Capture crashes when updating a part with changed PACK_TYPE and Symbol7 H K, p/ b/ B1 ^
2341550 SYSTEM_CAPTURE VERSION_ON_SA Projects migrated from HotFix 002 to HotFix 010 have slow peRFormance$ O: |) A% I5 e
2341591 SYSTEM_CAPTURE WIRING Moving wire segments still leaves odd pieces of wires' V2 ~* S- A6 {# Y* {
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发表于 2020-11-5 00:58
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