PCB 装配的假设分析模型 *
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| Standards | PCB X before DFM | PCB X after DFM |
Process
1 `% h% w& E2 t& x9 G' z v | dpm
9 X% H6 Y" V9 {" a" T" _ | S/U
) M c% P" ]& d! r; W& `2 h | Run% c. S9 Y* n" s v2 d; M
| Variable7 q0 C# p5 {2 y9 n
| S/U# C5 r2 N8 U' E: C+ N4 b0 t. Q: `
| Run! d5 D; v7 P+ m# j( v. \+ U8 g
| Quantity
, F3 X+ E& Z* J0 D Q | S/U, {+ j2 C# X4 t
| Run
& {: f( a4 G* o* _# P9 @* E7 }1 { | Quantity1 d( _- z3 K m6 W
|
Stencil Print(T)/ B* E* ~# K1 q, U. l( `5 r: A
| 20 | 5 | 0.5 | (PCB); O$ r! i: S) X+ Q* a5 q
| 5 | 0.5 | 1 | 5 | 0.5 | 1 |
Chip Place6 t2 Y; [ m9 m) l% M! u
| 100 | 10 | 0.012 | (SMT)
1 @- u9 S# u% S0 F | 10 | 0.048 | 4 | 10 | 0.312 | 26 |
IC Place
1 b$ p5 I3 [8 E/ H7 q | 200 | 15 | 0.025 | (SMT)) [& ~3 p& b7 k2 n8 {/ X2 m$ x
| 0 | 0 | 0 | 0 | 0 | 0 |
Reflow1 @% V0 B5 j" c# ~, W
| 25 | 5 | - | Internal
) D. b) W' c7 P9 } | 5 | 0.3 | 1 | 5 | 0.3 | 1 |
Stencil Print(B)
! S" L' m- e. {4 }# ?1 @9 w ~ | 20 | 5 | 0.5 | (PCB); g% F8 J3 M3 g0 g
| 0 | 0 | 0 | 0 | 0 | 0 |
Chip Place6 O4 ~, Z) B; z. b, L ]
| 100 | 10 | 0.012 | (SMT)+ \$ l% Z1 A- B8 k4 i r( F; L/ W; N
| 0 | 0 | 0 | 0 | 0 | 0 |
IC Place9 R' \: B, Q- [: y9 k6 q
| 200 | 15 | 0.025 | (SMT). U- \$ Z+ ~2 \* L+ ^" C! N4 E a
| 0 | 0 | 0 | 0 | 0 | 0 |
Reflow
* G9 q5 F6 j* Y. I1 \ | 25 | 5 | - | Internal9 D+ B6 C' y! R( W
| 0 | 0 | 0 | 0 | 0 | 0 |
Clean' \1 {+ K4 B+ Z1 V
| 10 | 5 | 0.3 | (PCB); v+ e! c0 F R& a( i( ]
| 0 | 0 | 0 | 0 | 0 | 0 |
DIP
+ I& M m6 e% l | 5000 | 15 | 0.1 | (Comp)- c* Y3 i: {3 z1 B; ]- v2 m/ x0 ?
| 0 | 0 | 0 | 0 | 0 | 0 |
Sequence
' l& [3 o0 s- |$ q/ E | 1500 | 20 | 0.02 | (Comp)
r7 y* L% g0 c0 p: B$ S4 [ | 20 | 0.26 | 13 | 0 | 0 | 0 |
VCD
/ s( l4 O" K8 |1 y5 T6 L; l | 1500 | 15 | 0.03 | (Comp)3 I# A& H7 J8 D7 u; d) G3 o# D
| 15 | 0.39 | 13 | 0 | 0 | 0 |
Radial
: W3 c1 Z5 B* ?0 M/ q; m | 5000 | 30 | 0.04 | (Comp); B" ]0 Y/ h- R1 Q2 v3 b: i
| 0 | 0 | 0 | 0 | 0 | 0 |
Stake
1 ^3 h9 }4 {5 l% | N5 m7 h; s8 N | 6000 | 10 | 0.14 | (Comp)* w: D- |. n4 J1 S3 |$ S# o
| 0 | 0 | 0 | 0 | 0 | 0 |
Mask" |8 Z7 p. Q" B% ]4 j
| 2500 | 10 | 0.05 | (Point)
) m9 ^9 D5 A) V' T | 10 | 0.15 | 3 | 0 | 0 | 0 |
Adhesive Dispense* w* v1 I) l8 k
| 50 | 5 | - | Internal! d; C3 H2 k+ z7 u( i: ~- x
| 5 | 0 | 50 | 5 | 0 | 50 |
Chip Place
$ h) f$ G) D! B: }/ G; Q | 100 | 10 | 0.12 | (SMT)
G! X+ J" C. O3 b4 n3 r9 ?" U | 10 | 0.6 | 50 | 10 | 0.6 | 50 |
IC Place- p* R4 x; K/ _
| 200 | 15 | 0.025 | (SMT)
$ Q/ B' k7 U. @& d4 X | 0 | 0 | 0 | 0 | 0 | 0 |
Cure2 H" l, U6 C( |* n" ^" b
| 25 | 5 | - | Internal& a3 C0 i1 l$ d9 |6 E
| 5 | 0 | 1 | 5 | 0 | 1 |
Clean/ F( S; D3 p7 e1 l6 I3 X
| 10 | 5 | 0.3 | (PCB)
+ [# j+ i% D( I4 _ | 0 | 0 | 0 | 0 | 0 | 0 |
Prep
& o- e. Q7 G6 _9 w+ e, T6 U | 5000 | 15 | 0.1 | (Comp)
+ V6 d* V$ D" n$ w- V- _ | 15 | 0.7 | 7 | 0 | 0 | 0 |
Prewave
3 ]) z6 H6 F3 D# C | 7500 | 10 | 0.2 | (Comp)5 p& n; f5 l: B
| 10 | 2 | 10 | 10 | 0.8 | 4 |
Wave Solder/Clean y0 d3 R4 T2 `7 n. \* s: i
| 2000 | 5 | 0.7 | (PCB)
4 g5 u U- N1 I9 E P& U' b9 ]5 \ | 5 | 0.7 | 1 | 5 | 0.7 | 1 |
Postwave Difficult8 X( ?: G p2 m3 t, `9 `
| 15000 | 10 | 3 | (Comp)
, ]" T2 I9 h7 S" ? | 10 | 9 | 3 | 0 | 0 | 0 |
Postwave Easy+ b( b5 `( H. O! E
| 10000 | 10 | 1 | (Comp)8 E& A- x/ Y- [$ x2 |3 }0 I/ x j6 I
| 0 | 0 | 0 | 0 | 0 | 0 |
Clean
8 u# f h' Z8 T5 O | 500 | 5 | 0.3 | (PCB)( R/ D9 V" U, \5 X" _2 I; g: \
| 5 | 0.3 | 1 | 0 | 0 | 0 |
Depanel# p/ j% N. G# a0 v1 O
| 5000 | 5 | 1.5 | (PCB)
4 h# A) ]/ h: O1 E9 S% P | 5 | 6 | 4 | 5 | 1.5 | 1 |
Conformal Coat9 h; d* ^$ M( z+ q( y8 U$ O8 q
| 10000 | 20 | 10 | (PCB)6 q" `, V/ ~" k6 V
| 20 | 10 | 1 | 20 | 10 | 1 |
Inspection6 ]% O! ?6 ~% o+ |3 r& ]) k- H8 M
| 500 | 5 | 0.007 | (Solder Joint)( i+ w; |7 {9 H% y! D
| 5 | 1.12 | 160 | 5 | 1.12 | 160 |
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|
Enter Lot Size | 50 | 50 |
Enter Realization | 0.55
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0.8 |
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I.E. Minutes | 165 | 32.068 | $ L3 w/ F: X9 G" n* U& s# C+ N$ v
| 90 | 15.832 | 2 G# K5 y* E' p$ }$ j" g
|
Prorated Setup | 3.3 |
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{8 W4 d7 M! n5 v9 N6 @! h | 1.8 |
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Total I.E. Min. | 2 l# K g9 Y: ~/ `2 j! e
| 35.368 |
Z0 c& A) m6 N& O+ @! j3 S- ~ | | 17.632 | |
Total I.E. Hours | | 0.589 | | | 0.294 | |
Expected Cycle Time | | 1.072 | | | 0.367 | |
Expected Cost | | $32.15 | | | $11.02 | |
Expected Yield | | 89.40% | | | 98.70% | |
* All numbers are fictitious and are intended for instructioal purposes only.
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Design for Manufacturability Scoring2 p3 D6 k4 R0 `
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Project: X
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Board #: Y
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Components
* X, @8 B- N3 D | Specs v8 e. d' q6 Q1 A
| Proto 1 Q4 Z* |& o% V% x& h7 P
| Proto 2
^! U! [/ }0 E. \3 S | Manufacturing Model, a% J# E0 S$ k! S0 u- R
| Production" |1 `4 L- b) P8 }7 h$ M4 J8 X9 N& @
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<1% sole-sourced components
, Y7 p! l' n8 @! N+ [ | 1 | 0 | 0 | 1 | 1 |
>95% PPSL compliance
; j1 ?$ K; L P4 c' H | 1 | 1 | 1 | 1 | 1 |
Process compatible packaging
/ [5 |; f$ _1 J0 a | 1 | 0 | 1 | 1 | 1 |
Component count - single pass
2 o3 _0 z I0 \3 Y$ [: L" J | 1 | 1 | 1 | 1 | 0 |
<2% hardware
( V1 M: @/ b% O, o5 H- |5 Z* ^ | 1 | 0 | 0 | 0 | 1 |
Correct Strategy selected
# p/ y; |9 e" m$ G$ t2 m | 1 | 0 | 0 | 0 | 1 |
| | | | | |
Design" h& I; k |$ W1 Q6 {3 W
| | | | | |
Optimal PCB panel# X* n$ x" J( Q8 Z! u7 _# b
| 1 | 0 | 1 | 1 | 1 |
Fabrication DRC resolved; b7 w( O* t$ ]2 g# B' X
| 1 | 0 | 0 | 0 | 0 |
Zero defect documentation
) z5 y2 L* P5 T& a% v# K | 1 | 0 | 0 | 1 | 1 |
CAM ready data# K4 S1 s# n' \7 Y, ]
| 1 | 1 | 1 | 1 | 1 |
Within PCB design guidelines* C# V! y: X9 u/ r
| 1 | 1 | 1 | 1 | 1 |
Process compatible orientation' S8 c+ Z* X" G9 m8 x8 h
| 1 | 0 | 1 | 1 | 1 |
| | | | | |
Manufacturing Process
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Correct material packaging# k- R0 w" c- y. E
| 1 | 0 | 0 | 1 | 1 |
Automation content >90%
5 ?* Z2 C8 r t# _8 I' R% G. X | 1 | 1 | 1 | 1 | 1 |
<1% post wave process
! M+ {/ {5 I0 N1 I | 1 | 0 | 0 | 0 | 1 |
Process steps <101 u7 ]# t D( V( l% e* q* h; k
| 1 | 0 | 0 | 0 | 1 |
No fixtures/tools required
! F; @$ M. F6 t$ Q+ ?9 D6 { | 1 | 1 | 1 | 1 | 1 |
6 sigma yield possible2 h4 O- M* B, J* C, L$ Z. Z
| 1 | 0 | 0 | 1 | 1 |
DFM Score | 18% | 33% | 50% | 72% | 89% |
93-100% | World Class
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85-92% | Highly Manufacturable
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77-84% | Acceptable) F Y# |( w5 ^* x
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69-76% | Poor, H4 a' x7 {9 p: B5 s
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0-68% | Unacceptable. O' Z& t! o4 a9 B
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