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本帖最后由 金志峰 于 2020-6-8 03:33 编辑
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cadence orcad and allegro 17.4-2019 QIR1新特性
& l4 a/ \3 A1 p4 H: g: g' c·焕然一新的图标及UI6 P) e, }- X) H" q" j( N
5 h8 n: I. a0 n, P2 A4 C4 {" kQIR1中全新启动界面 （点击图片放大）3 M, w% i+ v9 B! D
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- Q8 `+ [" @ B% g: h- X7 L: tQIR1中全新启动界面（点击图片放大）
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QIR1中capture官方Dark主题（点击图片放大）(QIR1中UI界面中所有图标也全部更换全新并统一了)8 Y' Z) q4 R% J2 n* k6 P" s
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- m; k" ]: b$ qQIR1中capture官方Light主题（点击图片放大）
3 c, \7 c3 ~2 |) l& @& k7 O(QIR1中UI界面中所有图标也全部更换全新并统一了)
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QIR1中PCB Editor新增官方Dark主题（点击图片放大）
8 T# g$ d. Y( w4 j(QIR1中UI界面中所有图标也全部更换全新并统一了), J6 D* @1 g" r3 K( j7 a6 H7 C
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& [: ~9 _, s1 c; d' B$ VQIR1中PCB Editor官方Light主题（点击图片放大）3 ]' M1 @# `7 T _) a) ~* b8 |
(QIR1中UI界面中所有图标也全部更换全新并统一了)2 @1 D4 A8 I' X6 P5 T8 b% B
1 y6 b7 \# u$ W4 B( D4 ~) I- l w$ ^
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8 S* o$ { r6 a0 ^Fixed CCRs: SPB 17.4 HF007
4 V1 z6 h6 @3 w$ E) Q. s05-21-2020
9 a5 s& Z; n- r4 ?========================================================================================================================================================
- ?$ `% N5 a" ^! Q% b! j2 MCCRID Product ProductLevel2 Title
& o1 |- B( j4 e- T1 }========================================================================================================================================================/ }) N+ s6 ~8 G0 @6 r
2247686 ADW CORE Allegro EDM: Unable to create a project using a newly created flow/ n% W( `6 k4 l" R/ D
2137594 ADW DBADMIN EDM is not allowing changes to STEP models( B: x. _9 Z, K" Q
2135452 ADW DBEDITOR DBEditor poor peRFormance in high-latency networks2 J9 ]$ ^5 h7 C4 R. U H
2113265 ADW LIBDISTRIBUTI Various database operations take a long time; rebooting server seems to fix the problem
2 K r' M6 q! x( R2122941 ADW LIBDISTRIBUTI Lib_dist execution taking a long time to run; Capture CIS DBC file appears to be taking the most time3 ~6 m1 w M4 k7 l; ]: _* e
2127319 ADW LIBDISTRIBUTI Library distribution fails at cisexport function with error (ORCIS-6250): T- a% U5 c0 s4 i1 b% ?' L
1975317 ADW PART_BROWSER Space at the end of the line in CDS.LIB results in zero libraries being shown in System Capture library search
( Y z8 G3 h- N* {& r+ {: X- ? O- Q& K2078057 ADW PART_BROWSER Symbol Graphics preview is not available in Designer Servers" ^5 L& [, i; s; o9 I, J: B
2092863 ADW PART_BROWSER System Capture library search is not displaying the symbol and footprint preview C, |6 Q: x' R+ u
2086463 ADW PART_MANAGER System Capture cannot add components when accessing remote machine via Citrix( ^$ q! a; Q, N
2092868 ADW PART_MANAGER Release 17.2-2016, HotFix 054: Empty cache.ptf causing injected properties to not flow from pstchip
- z# y- E6 ^1 V/ m0 K2092872 ADW PART_MANAGER System Capture stops responding when importing from DE-HDL
7 c& H5 L/ l- Y7 o& d/ T+ s2113226 ADW PART_MANAGER System Capture stops responding while importing DE-HDL sheets
, m6 T3 C2 }+ G" i2212406 ADW PART_MANAGER Allegro System Capture: Part Manager is deleting properties from all instances upon Update
" [! }1 N" ~. X9 s4 y- E; \2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name
) z: `3 H1 T( j- L" s2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to Team Design F+ D* L/ k `
2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object
- M! I3 c4 N; `: k9 e3 F# O/ Z2048086 ALLEGRO_EDITOR 3D_CANVAS Wire bonds are not linked to die pad when component is embedded body down
5 W. a' K4 \+ E0 M. _% v2051277 ALLEGRO_EDITOR 3D_CANVAS Vias are offset from board in Z direction in 3D Canvas+ r. a, Z, f" U8 x6 e w' T9 A
2054243 ALLEGRO_EDITOR 3D_CANVAS Plating is not shown on stacked vias in 3D canvas
( a2 f% _* U" P7 X* t* ]2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation- e& n0 t) i/ D! X5 q3 }3 G
2079732 ALLEGRO_EDITOR 3D_CANVAS Enhance 3D Canvas to merge the lines segment and overlapping lines and shapes
$ P* v# f' }0 ]3 A, P2206045 ALLEGRO_EDITOR ARTWORK Artwork Control Form fails to create film if Film record has a period (.) in the title
* m. o+ [7 ~9 L! T) D2209200 ALLEGRO_EDITOR ARTWORK PCB Editor stops responding on rebuilding apertures without rotation* \) w* T8 b* l7 t8 H
2244407 ALLEGRO_EDITOR ARTWORK Automatic editing apertures with rotation takes time in the General Parameters tab of Artwork Control Form; ~7 O! q6 d5 n* h
2267942 ALLEGRO_EDITOR ARTWORK Allegro PCB Editor stops responding when generating apertures in HotFix 006
- G: o4 p+ S' O: n7 p8 d5 s, d7 e$ X567342 ALLEGRO_EDITOR COLOR Add option under View menu for 'load color view'
! a9 ?& H* n. |4 t- {4 m637828 ALLEGRO_EDITOR COLOR Line highlights in 'shape select' command: j$ o) t0 S9 h! u: Q- r
720274 ALLEGRO_EDITOR COLOR Add menu option for the 'colorview load' command. v9 T: M5 \3 N' ^- }7 e. d3 W
1602652 ALLEGRO_EDITOR COLOR Color/Visibility behavior variation using "Enable Layer Select Mode"
& b$ R) Y; Y! {% o! U2072695 ALLEGRO_EDITOR COLOR Clines of colored nets not colored when 'display_nohighlight_priority' is set
8 z; Y$ z- l! _! z4 T* x2207580 ALLEGRO_EDITOR COLOR Component color is inconsistent when display_nocolor_dynamics is set.$ f8 s2 h7 P- M9 t8 P c
2056497 ALLEGRO_EDITOR DATABASE Place manual is slow
! v: d6 P0 Z- M: Q# i2250988 ALLEGRO_EDITOR DATABASE Inner Layer keep out as illegal subclasses: Shape object may not exist on layer ROUTE KEEPOUT/INNER_SIGNAL_LAYERS" p. K& I% k$ k% U( m5 P
2096958 ALLEGRO_EDITOR DFA Cannot launch Constraint Manager after assigning CSet and closing3 w& z9 I0 t2 p" J+ k8 A) `
2049681 ALLEGRO_EDITOR DFM DFF check for plating in via should not flag DRC for surface mount testpoint Via1 Z, g4 _+ V+ Z8 T
2155060 ALLEGRO_EDITOR DFM Inconsistent behavior in displaying DRCs for Via to Via spacing. F/ ]# |4 b; z, b6 D+ `) j5 s
2166431 ALLEGRO_EDITOR DFM DesignTrue annular ring thru pin pad to mask checks compared to smd pin to mask checks are inconsistent in behavior
9 X( x- _9 i" a2221975 ALLEGRO_EDITOR DFM DFM missing mask check reporting mask is missing when pins have a mask geometry overlaying them.7 p$ I% C6 t) Q( m
2249498 ALLEGRO_EDITOR DRAFTING When a Symbol with a Dimension is placed on the board, an extra Dimension is added to the Symbol origin.' Y# x; B+ T- m, T7 ]0 q
2250631 ALLEGRO_EDITOR DRC_CONSTR Cannot import netlist into design due to illegal DRC element: no DBDoctor error
& I. D" V; Q8 J1794593 ALLEGRO_EDITOR EDIT_ETCH Unable to deselect return path vias selected when creating High-speed via structures: W( A9 Y! C5 Y5 n% H
2099538 ALLEGRO_EDITOR EDIT_ETCH Gloss - Via Eliminate shifts traces to another layer D" b S1 K, P$ ?6 D
2204339 ALLEGRO_EDITOR EDIT_ETCH Differential pair line lost during slide operation8 F4 ]4 B0 Z0 C( |8 W
2208938 ALLEGRO_EDITOR EDIT_ETCH Slide operation makes one of the differential pair cline invisible
. y9 x( G) `0 w6 C6 y2222047 ALLEGRO_EDITOR EDIT_ETCH One of the traces disappear when sliding a differential pair in single trace mode5 M+ r- ]5 c3 i5 L6 P
2233991 ALLEGRO_EDITOR EDIT_ETCH One cline of a differential pair disappears temporarily upon sliding the Differential Pair in Single Trace Mode, G; g' `, u" i9 u- @, a$ D
2240827 ALLEGRO_EDITOR EDIT_ETCH Cline of a Differential pair net disappears after sliding the other net of the Differential pair1 p' C+ a% G9 h1 X
2245775 ALLEGRO_EDITOR EDIT_ETCH Differential pair slide in single trace mode removes other trace
$ p" {6 z! g2 v4 l u/ `! T4 k1813358 ALLEGRO_EDITOR GRAPHICS Allegro PCB Editor enables shape boundary when disabling etch layer in Visibility pane. M, L: n, }! W" b# ]+ X6 V; X& d1 |
1911613 ALLEGRO_EDITOR GRAPHICS The subclass for boundary class stays on, even if Subclass for Etch Class is turned off from Visibility tab8 C' e0 Y# Z. r! l" W% K% q
1966343 ALLEGRO_EDITOR GRAPHICS Shape boundary remains enabled even after turning off the etch layer visibility# b8 d+ E9 k9 _3 W( l4 e* _, M6 e* P
2195276 ALLEGRO_EDITOR GRAPHICS Selecting File view is slow
1 p+ D) V" a1 ^7 I: l2031883 ALLEGRO_EDITOR INTERACTIV Sub-Drawing: Clipboard origin point is not set correctly5 ]: X: U9 J" L6 Q0 `% C+ N% f, i
2050177 ALLEGRO_EDITOR INTERACTIV Letters need to remain aligned and uniform after performing Shape ANDNOT operation
0 h; Q# N. `7 M% x" A8 c' x2069247 ALLEGRO_EDITOR INTERACTIV DFA bubble on wrong layer after mirroring the part4 D' b, R# ~4 I+ e% Y
2103711 ALLEGRO_EDITOR INTERACTIV Placement edit mode popup 'Rotate' leaves ghost image in the background
7 Z6 a& Z* T) D0 @ Y+ O- b8 Z2136859 ALLEGRO_EDITOR INTERACTIV DFA Problem if we mirror component while placing$ r5 o4 x3 N$ t$ ? ]0 d
2165027 ALLEGRO_EDITOR INTERACTIV Different behavior in OrCAD Capture when using crossprobe to select Power nets9 ?4 y7 |4 m( W
2240235 ALLEGRO_EDITOR INTERACTIV The design file name changes automatically to board template name while creating new board (wizard).
/ ?4 G& N9 H+ w4 \) R& m' V2244765 ALLEGRO_EDITOR INTERACTIV License 4150+226 does not have AiDT/AiPT in release 17.2-20167 q% g( {* W% \9 M2 \$ k% G7 X- e1 [
2259800 ALLEGRO_EDITOR INTERACTIV DFA DRC circle not shown on the layer of placement in Placement App Mode- z6 H0 j; Q; B; R) g" s8 p0 w
2120420 ALLEGRO_EDITOR INTERFACES Drill figures missing in the exported PDF if drill legend deleted- N8 E0 ]# e/ g/ @ `
2136454 ALLEGRO_EDITOR INTERFACES Export - PDF output is not correct
3 ?) G t G% F2 ~6 P* n2116748 ALLEGRO_EDITOR IN_DESIGN_ANA Impedance vision data not available for cline segments for some nets x* i2 _1 a3 m4 B! j- J2 V
2138977 ALLEGRO_EDITOR IN_DESIGN_ANA Impedance check results are incorrect and Crosstalk analysis stops running after updating to 17.2-2016, HotFix 057
7 v) k# N) d5 S7 T4 K6 m2247167 ALLEGRO_EDITOR IN_DESIGN_ANA IDA Impedance Analysis: Add an option to export CSV automatically2 R- Q% t4 p3 _6 O7 K# s" x
2222638 ALLEGRO_EDITOR IPC Documentation Editor crashes with error: Failed to complete the job because of unspecified error5 f2 ]# |$ \4 G5 X
2106425 ALLEGRO_EDITOR NC Disable undersize regular pad and oversize soldermask pad for start layers in Backdrill Setup and Analysis
4 B1 X3 [& g. k$ w2091932 ALLEGRO_EDITOR OTHER Unsupported Prototypes command missing for the OrCAD licenses: W! g# i0 P! c* L
2221345 ALLEGRO_EDITOR OTHER Speed up Allegro PCB Editor startup by removing check for defunct PCB/Package co-design capability (NG_450). W) |1 u6 E/ |, o
2257934 ALLEGRO_EDITOR PLACEMENT Error (SPMHGE-626) on place component: Symbol not valid on any layer: W: l) v% s" P9 m* k
1001000 ALLEGRO_EDITOR PLOTTING File - Plot in PCB Editor does not plot more than one copy
1 r6 v# ^: ?5 e8 q2 _4 t6 {2234538 ALLEGRO_EDITOR REPORTS Allow Unused Blind/Buried Via report to run as Batch Process through the reports batch command
- ?# ?. Q) a0 M$ v) E# m+ C! D2222738 ALLEGRO_EDITOR SCHEM_FTB Netrev not completing, showing error for electrical constraints data (pstcmdb.dat) import) O5 t* g, N( n% P2 {5 b
2255426 ALLEGRO_EDITOR SCHEM_FTB Netrev is running for hours without closing1 K2 ]4 V5 \* x& g7 T' |, a
1702190 ALLEGRO_EDITOR SCRIPTS Allegro PCB Editor script file: Some sub-classes not created and error for form field label5 N) G# O+ Q4 F/ ~1 q& n. g
1791099 ALLEGRO_EDITOR SCRIPTS Allegro PCB Editor does not terminate when the script is run with '-nographic'
7 {6 C: |9 [) P+ Q7 x# x1791267 ALLEGRO_EDITOR SCRIPTS Allegro PCB Editor script does not run with '-nograph' in release 17.2-2016* D1 Q) A" m) z0 T- r$ c4 F
1892520 ALLEGRO_EDITOR SCRIPTS Allegro PCB Editor stops responding for script when run with '-nographic'
; i- K9 w' S# W5 X" W! R1962010 ALLEGRO_EDITOR SCRIPTS Allegro PCB Editor stops responding for script when run with -nongraph option/ M% J9 @/ T& X0 j- L% f
2056857 ALLEGRO_EDITOR SHAPE Shape boundary error by shape parameter
5 B6 w5 ?4 U3 q2081946 ALLEGRO_EDITOR SHAPE Shape Update takes twice the time in release 17.2-2016, HotFix 053 as compared to HotFix 047
/ {; t9 G5 f% s% p2104559 ALLEGRO_EDITOR SHAPE PCB Editor crashes while performing shape operation 'andnot'" } }! n* m7 A9 O3 E, i! \
2108207 ALLEGRO_EDITOR SHAPE No Void Overlap option is not working in Auto Metal Balancing (AMB); q* M3 ]5 s' I4 s) O t# V, C
2240996 ALLEGRO_EDITOR SHAPE Detecting Shape Island: Ignored for copied or moved shape3 }- ?8 P5 `! e3 ], m b
2258758 ALLEGRO_EDITOR SHAPE Allegro PCB Editor crashes when routing two signals together+ x% ?7 x2 o3 b6 _, u3 i! h
717389 ALLEGRO_EDITOR skill Ability to set and return the application mode using SKILL
! j" O* f$ f" e' z4 E8 Q. [; F& Q853160 ALLEGRO_EDITOR SKILL Need ability to get and set application modes using SKILL
1 ^; f, v% s3 h981446 ALLEGRO_EDITOR SKILL Request the ability to get and set application modes using SKILL
& f4 E3 d5 L5 G4 b& z9 p+ a1235409 ALLEGRO_EDITOR SKILL SKILL option to get application mode
# D# j& K# D t2 E$ w5 `7 D1316962 ALLEGRO_EDITOR SKILL SKILL option to switch between application modes
' r! r- h5 ]3 M5 H0 W! M4 O1553621 ALLEGRO_EDITOR SKILL Ability to change application modes using SKILL function
6 l* F' j/ u2 m1885442 ALLEGRO_EDITOR SKILL Ability to change application modes using SKILL function.
* j2 ?3 u1 B, e4 F; t0 b2080351 ALLEGRO_EDITOR SKILL SKILL to determine current application mode
1 C! A" E( {6 c8 h0 V2195645 ALLEGRO_EDITOR THIEVING Thieving pad cannot be added on some areas in the board in latest hotfix but could be added earlier% a2 D& S# M1 j- b) O% i
1721594 ALLEGRO_EDITOR UI_FORMS STEP name Filter for STEP Package mapping form should be case insensitive
% s0 y3 J- ?) H" f# B% Z1 W2090604 ALLEGRO_EDITOR UI_FORMS Undo/Redo UI grayed out when invoking Color1924 R1 G7 j n4 W9 q
2203278 ALLEGRO_EDITOR UI_FORMS 'Width' keyword in Place Rectangle field is grayed out when Place Rectangle is selected
: W3 i& e9 Q' J$ H3 c' R2209172 ALLEGRO_EDITOR UI_FORMS Labels truncated by drop-down lists in Options ('Manufacture' - 'Drafting' - 'Relative Copy')
" U+ b' ^( `3 M3 A3 q* a2239426 ALLEGRO_EDITOR UI_FORMS Cannot start text size with decimal in 'Design Parameter Editor' - 'Text' for English (Denmark) regional settings
^, V/ c6 s6 s& v% ]% I3 {9 |2245035 ALLEGRO_EDITOR UI_FORMS The right edge of the default Define Grid form looks cut off in 17.4.
6 [6 |: B L% ?& N2245955 ALLEGRO_EDITOR UI_FORMS Resizing of 'Reject Item Selection' window not possible in release 17.4-2019, HotFix 004
( Z3 H! M. ^( z# ]' l2249202 ALLEGRO_EDITOR UI_FORMS Extra click required to activate Pass field in Autorouter form( {2 c0 E5 t( j- n! g, S6 _
2259605 ALLEGRO_EDITOR UI_FORMS Add ability to resize Reject pop-up. Y( P6 N0 H) Y
2090517 ALLEGRO_EDITOR UI_GENERAL Shape visibility box is not being enabled with the Enable layer select mode option in the Visibility Pane% @' O2 J& a# d1 p
2092436 ALLEGRO_EDITOR UI_GENERAL RefDes length of input string for Modify Design padstack is limited to 20 characters
/ F3 e1 F0 i/ _2134781 ALLEGRO_EDITOR UI_GENERAL The Pin Class is missing in Options tab when creating or opening a Mechanical Symbol
! I& _% s" t3 n: f0 J2 w2168026 ALLEGRO_EDITOR UI_GENERAL Edit Properties UI slow to launch for boards with many drawing properties' M$ a& E5 e5 T+ r6 K6 ?! E$ c% C! S
2191267 ALLEGRO_EDITOR UI_GENERAL Changing Visibility of any object type disables links in Layer Select Mode in the Visibility pane7 F5 _4 V: \; w6 r$ A) E
2208018 ALLEGRO_EDITOR UI_GENERAL Text on BGA pins not visible in release 17.4-2019 if not zoomed to maximum( w# s) r0 ]- n" Z
2225753 ALLEGRO_EDITOR UI_GENERAL dark theme does not respect TRBICON size for 4K monitors: i2 g- D( I$ [- h: S
2256841 ALLEGRO_EDITOR UI_GENERAL Enlarge the Shape Copy to Layers form as the window is quite small and not resizable
0 s2 U+ c- f0 O9 v2258019 ALLEGRO_EDITOR UI_GENERAL Canvas turns white after closing STEP Package Mapping window) l2 Y* o9 \1 n8 `. v3 {
2258167 ALLEGRO_EDITOR UI_GENERAL Enhance 'Shape copy to layers' window in release 17.4-2019 to expand or resize
1 W$ x8 D9 x3 @2 V% q5 D, W$ D2262305 ALLEGRO_EDITOR UI_GENERAL Assign Differential Pair form list box size too small to add signals
/ z* U3 g; @! b3 {; Q& [' s2086574 APD OTHER APD is showing duplicate layer text on the vias2 W# _/ W& `1 q0 E
1723825 APD SCRIPTS Allegro Package Designer in release 17.2 is not writing out to either jrl files or script files in real time.; A, `, d& G! T9 v6 L- }
2186363 APD UI_GENERAL Text on the Pin is not visible until zoomed in to certain extent
1 ? O* q1 d. ?9 _" h3 f. U2253484 APD WIREBOND APD stops responding when running 'wirebond soldermask create' with 'Measure from soldermask pad'
6 \; I( p. ^0 U& E& V/ c2241725 CAPTURE DRC Waive DRC option not working from batch DRC window" p- t# A$ U8 o* F! T, W! f
2243645 CAPTURE DRC Online DRC bug in release 17.4-2019, hotfix 004 - offpage connector does not have wire
9 E. l' v/ F! Q2250867 CAPTURE DRC Hanging wire custom DRC not working when selected standalone. A6 C9 N4 h0 K. N* |5 b
2252912 CAPTURE DRC Unable to create new DRC file using Browse button in DRC window
8 K, O8 r2 g* f# u0 U2047391 CAPTURE PART_EDITOR Pin type cannot be changed in release 17.2-2016, hotfix 051
; r6 ^4 X0 @& O: Y) }2183187 CAPTURE SCHEMATIC_EDI OrCAD Capture: Ctrl + N seems to call a legacy dialog that allows projects to be created with no name
$ O8 B# i/ m: ]0 w4 I0 G) d9 k2190602 CAPTURE SCHEMATIC_EDI Cascading options of Window menu not working in OrCAD Capture in release 17.4-2019
$ N' G7 d4 I( b9 V# t9 E a2 i2194374 CAPTURE UX Design Sync issues: Session log does not report information about errors u( ?( @: A! W* y# k. y7 W
2183037 CIS LINK_DATABASE CTRL-L shortcut for Link DB-Parts for Query in CIS-Explorer not working' B4 M: @: M- `" T2 E2 D f
2201323 CIS PLACE_DATABAS Capture CIS displays empty dialog on placing part from database in release 17.4-2019
/ {' p& J3 i* ~ k9 N' E0 O" [2216963 CIS PLACE_DATABAS Light Theme: Warning text not visible in Capture CIS dialog9 n4 {2 U3 i" d6 o, {8 a
2246354 CIS PLACE_DATABAS Warning (ORCIS-6159) pop-up window is blank.
1 H$ S3 D+ {4 h3 R$ S2230651 concept_HDL CHECKPLUS Discrepancy in the 'checkplus' marker files: C: ?: ^5 O' i. `! o0 E
2237145 CONCEPT_HDL CONSTRAINT_MG T-Points match groups get deleted after saving a design
3 Q! v( b$ _! ^7 s# y6 T U2246452 CONCEPT_HDL CORE Page information gets removed from 'master.tag' of the top-level design when subdesigns are read-only' k1 t6 a% v6 b# d3 z2 C/ M
2057490 CONSTRAINT_MGR CONCEPT_HDL Constraint Manager Worksheet flips after running hier_write when CM is open. e7 P; {! Q+ m x9 t
2236329 CONSTRAINT_MGR CONCEPT_HDL Pin Pairs not added to Match Group' |1 h( U1 b$ m. l- }6 X$ |- K
2214367 CONSTRAINT_MGR INTERACTIV CSet assignment matrix sorting in Net Class-class random in Capture to Constraint Manager flow2 a9 x% B0 c* R3 n; r1 f
2243574 CONSTRAINT_MGR OTHER CM SKILL cmxlPutAttribute() cannot set constraint value
6 b# }6 z1 U& i* \2259598 CONSTRAINT_MGR OTHER Importing netlist: Error for electrical constraint data (pstcmdb.dat) import1 Z, ^7 p& h) \
2207862 CONSTRAINT_MGR SYSCAP Save icon and 'File' - 'Save' menu in Constraint Manager is inactive
/ J6 y; _" o0 r) U% ]& P2200316 CONSTRAINT_MGR UI_FORMS Expanding 'Analysis Mode' form resets column width0 M% Y; N) W+ Q
2097479 PCB_LIBRARIAN CORE Symbol import in Part Developer does not show the correct pin shape.5 [ c6 k; G( ~8 H- e( ]
2145385 PCB_LIBRARIAN CORE Error-SPLBPD-972 reports missing parentheses in the ALT_SYMBOLS property of a part
0 v' ]$ [% k& u+ s( d* }8 t' t4 J2202622 PCB_LIBRARIAN CORE When adding a new pin to a symbol in Symbol Editor, the space between pins changes. B' T: y; k: { v( [
1955570 PCB_LIBRARIAN FLOW Using the PACK_SHORT property with more than 256 characters does not work or report an error on packaging1 \% W7 x H8 s( b) e
2072190 PCB_LIBRARIAN FLOW Allow PACK_SHORT property value longer than 255 characters
" l. X/ q9 r9 P0 H' _- e E1720395 PCB_LIBRARIAN IMPORT_OTHER Converting OrCAD Capture OLB to Design Entry HDL library adds braces to pin number
4 b* \) p" c5 j& Y. |2141340 PCB_LIBRARIAN SETUP SPLBPD-216 Error logged in PDV even when MAX_SIZE Sheet is defined
u N2 @( g! Q6 Y* N ?, }2214973 PCB_LIBRARIAN SETUP Unable to apply symbol property templates when PDV lock directives are set
$ {& f- K* D# {: p! [ V2257527 PCB_LIBRARIAN SETUP Locking PDV directives prevents applying symbol property templates) H3 f; C c8 }
2033898 PCB_LIBRARIAN SYMBOL_EDITOR Running Symbol Editor with no arguments results in a background process, not an error.( s% u9 @& k9 N: E1 O8 [( z
2093849 PCB_LIBRARIAN SYMBOL_EDITOR Symbols and font sizes appear different when placed in designs
7 L- V7 }5 [7 R) ~0 O4 v8 l% R2200399 PCB_LIBRARIAN SYMBOL_EDITOR Multiple issues observed when editing parts in the New Symbol Editor2 l) X6 E% z2 [) B' c: a4 B' \, T$ c
2218940 PCB_LIBRARIAN SYMBOL_EDITOR Duplicate pins cannot be removed
* G) G: W$ T2 {% g' v2230542 PCB_LIBRARIAN SYMBOL_EDITOR Bus pin location changes after expanding or collapsing pins in Symbol Editor
^8 g5 ?" [, ~& q2 n9 ^2239303 PCB_LIBRARIAN SYMBOL_EDITOR Expanding and collapsing a bus is changing the msb and lsb for the pin name V" s# o) }& }- K- I! K
2243431 PCB_LIBRARIAN SYMBOL_EDITOR Group of pins that are not adjacent cannot be moved together
& z/ y1 m6 C4 a; S2 d7 r2029056 PCB_LIBRARIAN SYMBOL_EDITOR Unable to change Grid Settings in Part Developer: e8 u! N7 \' c3 e4 z5 s9 Y$ a
2149948 PCB_LIBRARIAN SYMBOL_EDITOR New Symbol Editor and System Capture moved pins from 0.01 grid to 0.05 grid.
8 P5 H# ]$ H/ B2206975 Pspice MODELEDITOR PSpice Model Import Wizard symbol preview readability improvement requested) n0 W; A8 g7 T: T1 E# {
2211187 PSPICE MODELEDITOR Model Editor color scheme not readable" W% b* ?3 C c" E
2214415 PSPICE MODELEDITOR Symbol view in Model Import Wizard has a visibility problem1 j# l: m7 Y' Q' d3 c) }
2199570 PSPICE PROBE Unable to 'select sections' after Monte Carlo runs with Temperature
+ C1 X% w! R ]$ h. H2 v4 V( a6 s2244140 PSPICE PROBE Not able to select multiple sections to plot in probe4 b% S* t9 B" Z2 J; j2 Q' @! E) |
2249565 PSPICE PROBE Selecting multiple traces for PSpice A/D Monte Carlo run not working
" [8 I/ w8 @2 D/ K+ P6 H6 [2171626 PULSE CORE Pulse crashed with error related to third-party development kit platform issue# F1 Y- e q1 `7 H5 S4 \" z$ b9 W
2221523 PULSE UNIFIED_SEARC Cannot log in to third-party search providers but can log in to Cadence Online Support3 g! `; D1 a5 N
2019229 RF_PCB OTHER Layer conversion file data does not update GDSII layer mapping using Package Symbol Wizard1 m# R e) x0 U! H* O$ t
820288 SIP_LAYOUT COLOR Layer Priority command does not seem to be functioning$ \) b! w, e: J* j' V! w+ B k ?" S: ]
820305 SIP_LAYOUT COLOR Layer Priority menus do not match the Color dialog in the package substrate tools
0 I! D: Z9 i, f2 }2256044 SIP_LAYOUT DATABASE Fix teardrop does not work for some situation: Deleting fixed fillets
2 o2 y2 Q; E/ ?* ]2254932 SIP_LAYOUT DEGASSING APD Plus generating assertion failures when running degassing mode with script
3 I7 ~8 Y, w8 G6 u2106314 SIP_LAYOUT INTERACTIVE Large design causing severe lag in Windows Server machine# X6 J% z+ a2 q& A- f. S
2096239 SIP_LAYOUT STREAM_IF Database fails to create stream out file, i8 \3 e, d' l
2079071 SIP_LAYOUT SYMB_EDIT_APP Response very slow after Show IC Details on a very large co-design die
* J5 z4 H5 ?; x. Q0 J: m: [2251630 SIP_LAYOUT WIREBOND 'Change Profile' does not change the diameter of the wire bond
' L) h$ o8 e) N2253633 SIP_LAYOUT WLP Advanced degassing passing illegal arguments to dba routine
4 T! v1 K# M3 q% R0 v2259630 SIP_LAYOUT WLP Advanced WLP: Import PVS DRC results in error
- R9 z1 r: ]2 |6 D" S1 b1968437 SYSTEM_CAPTURE ASSIGN_SIGNAL Net name pasted in lower-case though uppercase input is enabled3 M- M% r2 o. ~. `6 \
2131976 SYSTEM_CAPTURE AUTOMATION syscap exits when run with the -tclfile argument and an invalid Tcl file* c- W, ~* H3 a
1983063 SYSTEM_CAPTURE BLKDIAGRAM_AU Auto Shapes are being shown as part of components2 K2 F: @/ s8 p; h& T- Z
1977673 SYSTEM_CAPTURE COMPONENT_BRO adding reference blocks through add component error when cell name matches design name
3 b( P& j( R3 M/ Q9 ~2247567 SYSTEM_CAPTURE COMPONENT_BRO Symbol property placeholder changes not updated on the canvas
( W( Y3 d; i; H# `& t2027100 SYSTEM_CAPTURE COMPOSITE_FIL pstdedb.cdsz and netlist preview in System Capture is not being updated when individual netlist files are written
$ L( L( e4 h" G$ D3 y. R& p: g. w% u% R1863460 SYSTEM_CAPTURE DARK_THEME thumbnail preview of pages is in light them but dragging the page the previes is dark
- w6 @& H+ N6 Q2168622 SYSTEM_CAPTURE EDIT_SEARCHRE Reports from Find Results are dumped even when the operation is canceled
9 }9 l) m8 I1 |2168625 SYSTEM_CAPTURE EDIT_SEARCHRE Sort icons for columns in 'Find Results' are incorrectly placed: appear to be in adjacent column
% o5 |- c! h' g7 w1895142 SYSTEM_CAPTURE EXPORT_PCB System Capture incorrectly reports unsaved changes when closing after running export physical2 e9 q) g& I: P0 { h8 e7 Z4 a
1931660 SYSTEM_CAPTURE EXPORT_PCB SDA is non-responsive while Allegro launches and opens a board when launched from SDA6 v, f% z" N5 W1 e
2087387 SYSTEM_CAPTURE EXPORT_PCB System Capture: After Export PCB completes, busy cursor shown for a while
9 F& M$ R9 |* T8 v! c2202179 SYSTEM_CAPTURE FIND_REPLACE Replacing a net name with the same name by using Find and Replace results in a crash* U- [+ T7 o2 j( \5 X, g6 s
1843885 SYSTEM_CAPTURE FORMAT_OBJECT Renaming a net causes it to lose custom color assignment
9 I8 r7 l4 X9 i! \1993208 SYSTEM_CAPTURE FORMAT_OBJECT Setting font prior to placing text does not work, pop-up does not work, and bucket results in scrolling page
: _$ F8 ^, n3 X" w3 x2231399 SYSTEM_CAPTURE IMPORT_BLOCK 'importBlock' Tcl command not working when using a script. h- H4 g U1 Y7 {) K7 E8 G: u
1907729 SYSTEM_CAPTURE IMPORT_DEHDL_ Import DE-HDL sheets - differential pair properties on nets are lost
1 L \' d4 q. W4 l& E7 J# {$ y2025949 SYSTEM_CAPTURE IMPORT_DEHDL_ Title block and thick wires/lines of border in DE-HDL do not translate in System Capture7 x& M) e, v( C. o1 V% D, N
1942542 SYSTEM_CAPTURE IMPORT_PCB System Capture - TDO backannotation overwrites net names with stale data in lower-level blocks
! c: b- c! M2 Y, C1 w1982320 SYSTEM_CAPTURE IMPORT_PCB View files are not created in the schematic-to-board flow2 S8 F0 h: q1 M$ @- W1 w3 D
2117532 SYSTEM_CAPTURE MENUS_AND_TOO Ability to customize menus for a site* a5 V# [2 L# v7 n
2213478 SYSTEM_CAPTURE MENUS_AND_TOO Help - About menu item appears twice! P% a5 l; \2 r6 y d" _9 a
1910941 SYSTEM_CAPTURE MISCELLANEOUS Parts that are not in any schematic page appear in netlist and BOM
7 y8 w& e' C, {9 T2 w0 h9 P1967614 SYSTEM_CAPTURE MISCELLANEOUS Dragging a circuit with net aliases does not move the net aliases with it& N9 f9 }) A( R3 \) Z
2189846 SYSTEM_CAPTURE MISCELLANEOUS Inconsistent display of same font& f- t) ? S" ?! g# i
2178961 SYSTEM_CAPTURE NOTES Cannot add Japanese text in notes in release 17.4-2019 on Windows 10
0 y. P/ n7 W9 _, m& l6 `- ~4 \1973437 SYSTEM_CAPTURE OPEN_CLOSE_PR Opening a design crashes System Capture
0 T- R! ?) ? R- g2079857 SYSTEM_CAPTURE OPEN_CLOSE_PR System Capture: Unable to select design to open if license selection box is canceled the first time) x5 f3 K `' i
2065025 SYSTEM_CAPTURE PACKAGER Export to PCB Layout reports wrong path but exports correctly7 ]" m' F* i3 l: A/ h- w* N7 x
2229611 SYSTEM_CAPTURE PACKAGER Path for the 'packaged' folder shown in the 'Export Physical' is incorrect
; u/ I4 w9 E; x v" G* b' H1993146 SYSTEM_CAPTURE PROJECT_EXPLO Cannot move page up by only one position
9 U* i1 T+ ]- p: m& X1892120 SYSTEM_CAPTURE PROPERTY_EDIT Some parts are missing reference designators and some have two properties - RefDes and REFDES: N( c6 q6 @! v" g5 V4 ^" w$ U
2201060 SYSTEM_CAPTURE PROPERTY_EDIT Some of the icons in the Properties window do not have tooltips5 O$ H+ u; H, v2 K
2246667 SYSTEM_CAPTURE SCRIPTING Running the 'replay.tcl' script gives an invalid command name error3 Y, m Q; g) V. W/ G- J
2010032 SYSTEM_CAPTURE SHORTCUTS Cannot enter Page-Up/Page-Down as shortcuts
0 _$ |6 ~/ u; E% A7 ?- z2017985 SYSTEM_CAPTURE TDO Allegro System Capture ability for multiple users to open a design0 |9 \3 f0 u) v+ ?
2106743 SYSTEM_CAPTURE TDO Ability for multi-user access to the same schematic
/ z8 O' b1 T8 A x& I2209628 SYSTEM_CAPTURE UI Tooltips for Design Rule Checks are getting truncated
+ H C- K( p6 v4 [ ^1990258 SYSTEM_CAPTURE VARIANT_MANAG Cannot paste copied preferred part to multiple parts with the same part number9 M8 a+ D, n1 ~, c, @
2032005 SYSTEM_CAPTURE VARIANT_MANAG Custom variables not saved for variants7 q+ L2 }+ x! A7 w9 u1 x8 G+ F
2228299 SYSTEM_CAPTURE VARIANT_MANAG CAP parts should not show up in the Preferred Parts list when changing a RES0 x# H1 t3 `( U$ S0 p
1627835 SYSTEM_CAPTURE WIRING Inconsistencies in wire movements/ a1 S+ _" r5 [8 [8 t
1670888 SYSTEM_CAPTURE WIRING Rotation error when a component is connected to a power symbol
$ ]' X9 `2 w7 C' v' q' |1721863 SYSTEM_CAPTURE WIRING Net names move to random locations when components are moved around the canvas.1 I Y" M% q. Q, i
1960130 SYSTEM_CAPTURE WIRING Disconnected nets when using the mirror option! f* k/ E6 L) ]/ L7 D2 `+ m4 Y0 }$ d
1961274 SYSTEM_CAPTURE WIRING XNet removed during pin swapping% J/ d& H: `: e3 O
1968463 SYSTEM_CAPTURE WIRING System Capture should not allow illegal characters to be entered for net names& s$ J" _! F0 q) H1 E: ^( ]
1973426 SYSTEM_CAPTURE WIRING Selecting multiple net names and trying to delete only deletes one net name.$ ~& W! u; O) b0 i
1978381 SYSTEM_CAPTURE WIRING 'oops' does not remove the first vertex placed$ A4 D* e- | L2 I& i
1985029 SYSTEM_CAPTURE WIRING Net aliases are not dragged with circuit, they appear to move after the circuit is dropped8 v1 D! A& k# o0 g* J; Q# Q
2013647 SYSTEM_CAPTURE WIRING Replacing a vertically oriented RES with a horizontal CAP breaks the wire connections
& d; u& |5 f4 X2014188 SYSTEM_CAPTURE WIRING Context menu not working in Variant mode8 B% J4 g: D0 C5 `! Z& Q7 V1 y
2041879 SYSTEM_CAPTURE WIRING XNets generated for nets with pull-up resistors: g1 S0 ]* P7 n# a _- X
2050533 SYSTEM_CAPTURE WIRING Need an option to increase junction dot size
: _8 i7 s/ \; H3 k' s& Q5 n1 W$ ]2061877 SYSTEM_CAPTURE WIRING Unable to add a power symbol with the Place - Special Symbol menu
% D9 L. T" n; ], {% v2079409 SYSTEM_CAPTURE WIRING Increase the size of the wire connection dot in System Capture
K# Z5 \4 B5 ^9 w: J; S6 m s& n2081884 SYSTEM_CAPTURE WIRING Symbols take a long time to move, and results in DRCs and broken connections8 \2 }, g& P2 |! s! Y
2085263 SYSTEM_CAPTURE WIRING System Capture: Focus lost from the Format tab if font name starting with typed letter is not present7 g; u: `4 f1 J; L
2089569 SYSTEM_CAPTURE WIRING Ability to specify the solder dot radius size- {* B5 d# _- z
& l5 y# J5 t9 [4 c" t
QIR1详细特性说明：
Hotfix_SPB17.40.007_README-Release_Notes.pdf
(2.51 MB, 下载次数: 55)
: X" [9 N8 h+ t: t待我上传完后附上链接，这次QIR1比较大，4.59 GB
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