|
|
EDA365欢迎您登录！
您需要 登录 才可以下载或查看，没有帐号？注册
x
本帖最后由 金志峰 于 2020-6-8 03:33 编辑 0 q) c A. g, ]. Y- a
( p e- j. s' j) A6 Z
cadence orcad and allegro 17.4-2019 QIR1新特性 8 W: e* v9 y) K6 m8 `6 q4 e
·焕然一新的图标及UI( Q1 X: d" k+ }, N6 t3 h% p. D
; \# L3 ]7 K1 ]QIR1中全新启动界面 （点击图片放大）
; a( ]* L6 S$ t" W6 H2 L% ?1 E' C
# h3 w8 p0 \; W# t( _
7 n/ p# O( I1 a' D d
QIR1中全新启动界面（点击图片放大）/ d5 _: q; T3 l, h- k& X+ M
- W0 y+ C! l4 @" L0 h
5 k' F% W) B( {3 \4 y, J4 t4 ]) E * H! L5 a0 H, L( e
QIR1中capture官方Dark主题（点击图片放大）(QIR1中UI界面中所有图标也全部更换全新并统一了)
* E4 {6 @! S8 @2 u2 P- V! n5 s
6 f9 B1 J Q2 x2 T0 f% n2 a
$ l7 q/ T l: }2 Q; I. RQIR1中capture官方Light主题（点击图片放大）1 x; a7 J, X8 C3 [
(QIR1中UI界面中所有图标也全部更换全新并统一了)$ l' P0 ?" F0 Q* Y% O, q8 S
' x% a: l4 {' r" i$ E
3 @# x2 j# n8 x1 s; Y( a+ Q' fQIR1中PCB Editor新增官方Dark主题（点击图片放大）
: O/ U) R+ c% [: B# J! p(QIR1中UI界面中所有图标也全部更换全新并统一了)# I; R3 a/ Z& u$ f# u
& Q8 c& C- H; O7 U. ~- g v* Q6 a* s$ z
QIR1中PCB Editor官方Light主题（点击图片放大）, g# x7 g8 [- @+ s" d2 |
(QIR1中UI界面中所有图标也全部更换全新并统一了)0 a( Z. E0 W# s$ Q ?5 M( N
6 M1 o0 l$ f0 \- W( C. E
Z' @7 m# W) M9 B# z* l% p, A5 o4 a# x5 I5 a" \( H
1 V e A6 G7 l+ u- \2 j" U5 }$ M
1 F) K1 ^$ l; G# G9 |7 w' Q& M
Fixed CCRs: SPB 17.4 HF007# M+ _ P! [8 Y+ b
05-21-2020
: F1 \( }! V, y$ l' Y: ?0 k6 b========================================================================================================================================================
, B+ z9 W4 h* n$ O. H: J* [0 ~& S* FCCRID Product ProductLevel2 Title
# k P; |/ q6 I0 s2 |3 f+ f========================================================================================================================================================
6 P; b7 V: w- E* B8 v5 r2 G5 z, e2247686 ADW CORE Allegro EDM: Unable to create a project using a newly created flow
( d" T- M4 w+ C; @* X3 Q& L& v2137594 ADW DBADMIN EDM is not allowing changes to STEP models
: v8 m3 O) e7 o3 F& K) r, d# w8 N2135452 ADW DBEDITOR DBEditor poor peRFormance in high-latency networks
5 u8 i$ T# J( J* c) e2113265 ADW LIBDISTRIBUTI Various database operations take a long time; rebooting server seems to fix the problem
% G3 \/ d+ Z( Y2122941 ADW LIBDISTRIBUTI Lib_dist execution taking a long time to run; Capture CIS DBC file appears to be taking the most time6 q$ \9 v3 K2 c* |% } p5 S) v
2127319 ADW LIBDISTRIBUTI Library distribution fails at cisexport function with error (ORCIS-6250)
* Q/ \; U a: M8 D2 ^1975317 ADW PART_BROWSER Space at the end of the line in CDS.LIB results in zero libraries being shown in System Capture library search5 m$ d" S" U2 g8 p4 B+ `
2078057 ADW PART_BROWSER Symbol Graphics preview is not available in Designer Servers! _; r# S; n0 P' } `
2092863 ADW PART_BROWSER System Capture library search is not displaying the symbol and footprint preview$ u7 B! v# ?( w/ t5 v
2086463 ADW PART_MANAGER System Capture cannot add components when accessing remote machine via Citrix
6 c1 m: j* [1 x2092868 ADW PART_MANAGER Release 17.2-2016, HotFix 054: Empty cache.ptf causing injected properties to not flow from pstchip0 q) K, s, M; q7 ^! M
2092872 ADW PART_MANAGER System Capture stops responding when importing from DE-HDL
: N" z0 c5 ~/ K5 a0 T0 C/ ~! W2113226 ADW PART_MANAGER System Capture stops responding while importing DE-HDL sheets, z% d" t. s" x" l2 T
2212406 ADW PART_MANAGER Allegro System Capture: Part Manager is deleting properties from all instances upon Update
7 T7 n; w' b8 c9 l6 x) V2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name. `0 g4 A* X% E; h& T& C0 B9 H% a
2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to Team Design
( p4 J- r7 g" I2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object
/ r4 m$ L4 H. G) J$ n9 ^2048086 ALLEGRO_EDITOR 3D_CANVAS Wire bonds are not linked to die pad when component is embedded body down2 ]& T( K0 `8 r; _' Z) R
2051277 ALLEGRO_EDITOR 3D_CANVAS Vias are offset from board in Z direction in 3D Canvas* B/ N& b' U9 o* t0 M, i5 h
2054243 ALLEGRO_EDITOR 3D_CANVAS Plating is not shown on stacked vias in 3D canvas
. l& i7 T8 O2 u V. h2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation
, R! t7 p! F8 ?/ V* m2 [; @* X2079732 ALLEGRO_EDITOR 3D_CANVAS Enhance 3D Canvas to merge the lines segment and overlapping lines and shapes6 _# M8 \9 ~2 O* Y% @ Q
2206045 ALLEGRO_EDITOR ARTWORK Artwork Control Form fails to create film if Film record has a period (.) in the title: s2 [7 w, O s% [ ]# ?
2209200 ALLEGRO_EDITOR ARTWORK PCB Editor stops responding on rebuilding apertures without rotation
' X# K- }5 ]2 I2244407 ALLEGRO_EDITOR ARTWORK Automatic editing apertures with rotation takes time in the General Parameters tab of Artwork Control Form
( _8 r6 I$ P. Y2267942 ALLEGRO_EDITOR ARTWORK Allegro PCB Editor stops responding when generating apertures in HotFix 006
6 e2 n' ^* z7 x! U567342 ALLEGRO_EDITOR COLOR Add option under View menu for 'load color view'( t7 X* D- L! v! O9 }
637828 ALLEGRO_EDITOR COLOR Line highlights in 'shape select' command
1 O( y) s& m0 r720274 ALLEGRO_EDITOR COLOR Add menu option for the 'colorview load' command" v: c) r+ q6 H+ j- ]
1602652 ALLEGRO_EDITOR COLOR Color/Visibility behavior variation using "Enable Layer Select Mode"
8 X- P4 q6 X4 C* D1 ]& o2072695 ALLEGRO_EDITOR COLOR Clines of colored nets not colored when 'display_nohighlight_priority' is set3 l% C' X; ]6 a4 S- w. `
2207580 ALLEGRO_EDITOR COLOR Component color is inconsistent when display_nocolor_dynamics is set.; \3 U% V" _/ }2 z, B/ o, }- _7 c2 x! u
2056497 ALLEGRO_EDITOR DATABASE Place manual is slow
2 f$ K1 S" F* A& \) d) R2250988 ALLEGRO_EDITOR DATABASE Inner Layer keep out as illegal subclasses: Shape object may not exist on layer ROUTE KEEPOUT/INNER_SIGNAL_LAYERS9 U" s( o1 l+ [0 k7 f
2096958 ALLEGRO_EDITOR DFA Cannot launch Constraint Manager after assigning CSet and closing
# E' }9 w8 H/ e8 B: W% n2049681 ALLEGRO_EDITOR DFM DFF check for plating in via should not flag DRC for surface mount testpoint Via
& `: e1 l! c' D, A6 D0 X2155060 ALLEGRO_EDITOR DFM Inconsistent behavior in displaying DRCs for Via to Via spacing
& L; [* h- r3 k5 h+ H7 S7 ?' w2166431 ALLEGRO_EDITOR DFM DesignTrue annular ring thru pin pad to mask checks compared to smd pin to mask checks are inconsistent in behavior% n9 w- c) {' v$ o5 x3 a$ O
2221975 ALLEGRO_EDITOR DFM DFM missing mask check reporting mask is missing when pins have a mask geometry overlaying them.
$ L+ l9 W _5 m7 Z2249498 ALLEGRO_EDITOR DRAFTING When a Symbol with a Dimension is placed on the board, an extra Dimension is added to the Symbol origin.
+ m! F6 s( ? q7 W2250631 ALLEGRO_EDITOR DRC_CONSTR Cannot import netlist into design due to illegal DRC element: no DBDoctor error2 Q8 t/ [6 v5 n2 M
1794593 ALLEGRO_EDITOR EDIT_ETCH Unable to deselect return path vias selected when creating High-speed via structures
6 Z8 a* x; ]$ ?2099538 ALLEGRO_EDITOR EDIT_ETCH Gloss - Via Eliminate shifts traces to another layer8 z( v, |3 A a, z2 c8 K2 `7 A
2204339 ALLEGRO_EDITOR EDIT_ETCH Differential pair line lost during slide operation# p3 o( N% b, x+ @- d% m/ ?
2208938 ALLEGRO_EDITOR EDIT_ETCH Slide operation makes one of the differential pair cline invisible0 t I! _9 y8 s/ n
2222047 ALLEGRO_EDITOR EDIT_ETCH One of the traces disappear when sliding a differential pair in single trace mode
6 e( k y; Q/ T0 b2 ^1 F2233991 ALLEGRO_EDITOR EDIT_ETCH One cline of a differential pair disappears temporarily upon sliding the Differential Pair in Single Trace Mode
+ Z; Y, ?7 _& K9 j2 S0 R, u2240827 ALLEGRO_EDITOR EDIT_ETCH Cline of a Differential pair net disappears after sliding the other net of the Differential pair
4 {' N8 W9 L1 Y( u1 q& @ R2245775 ALLEGRO_EDITOR EDIT_ETCH Differential pair slide in single trace mode removes other trace
) u7 i" F" j& q" {2 s! r% a1813358 ALLEGRO_EDITOR GRAPHICS Allegro PCB Editor enables shape boundary when disabling etch layer in Visibility pane0 z4 Z) D& _1 u0 B# j4 T5 J: E5 q! H
1911613 ALLEGRO_EDITOR GRAPHICS The subclass for boundary class stays on, even if Subclass for Etch Class is turned off from Visibility tab0 n: m Q, ]4 K1 t
1966343 ALLEGRO_EDITOR GRAPHICS Shape boundary remains enabled even after turning off the etch layer visibility' ?2 {2 u6 u$ E1 z3 p* w' m% v
2195276 ALLEGRO_EDITOR GRAPHICS Selecting File view is slow# ]( }/ C2 T2 Q" D, K
2031883 ALLEGRO_EDITOR INTERACTIV Sub-Drawing: Clipboard origin point is not set correctly5 Y b$ D: Q$ `0 C1 L
2050177 ALLEGRO_EDITOR INTERACTIV Letters need to remain aligned and uniform after performing Shape ANDNOT operation% l8 S8 E1 D5 X3 ?3 c7 R
2069247 ALLEGRO_EDITOR INTERACTIV DFA bubble on wrong layer after mirroring the part* s9 g0 e4 ^ g1 r6 ~1 N1 @
2103711 ALLEGRO_EDITOR INTERACTIV Placement edit mode popup 'Rotate' leaves ghost image in the background
|4 y' o' R. @4 X1 D2136859 ALLEGRO_EDITOR INTERACTIV DFA Problem if we mirror component while placing# X5 x/ s s7 n- {( h
2165027 ALLEGRO_EDITOR INTERACTIV Different behavior in OrCAD Capture when using crossprobe to select Power nets
) R! l" Z5 r/ g- ?( e7 F, g2240235 ALLEGRO_EDITOR INTERACTIV The design file name changes automatically to board template name while creating new board (wizard).
w% W; i$ ~. `; X6 a, N3 I; O2244765 ALLEGRO_EDITOR INTERACTIV License 4150+226 does not have AiDT/AiPT in release 17.2-20165 O" Y, \0 ]; z" z
2259800 ALLEGRO_EDITOR INTERACTIV DFA DRC circle not shown on the layer of placement in Placement App Mode
3 K6 N" L. A% v+ t, G+ Y5 {2120420 ALLEGRO_EDITOR INTERFACES Drill figures missing in the exported PDF if drill legend deleted) \9 l* h1 o% l* C/ v# C
2136454 ALLEGRO_EDITOR INTERFACES Export - PDF output is not correct
) d; q: d0 X5 |4 G4 O+ B2116748 ALLEGRO_EDITOR IN_DESIGN_ANA Impedance vision data not available for cline segments for some nets) F% F" z! P3 K; Q
2138977 ALLEGRO_EDITOR IN_DESIGN_ANA Impedance check results are incorrect and Crosstalk analysis stops running after updating to 17.2-2016, HotFix 0573 y0 J k) s" x2 h0 S
2247167 ALLEGRO_EDITOR IN_DESIGN_ANA IDA Impedance Analysis: Add an option to export CSV automatically9 Q- F; c4 I+ W
2222638 ALLEGRO_EDITOR IPC Documentation Editor crashes with error: Failed to complete the job because of unspecified error
7 O4 z' T! s- t* F* N3 f7 V2106425 ALLEGRO_EDITOR NC Disable undersize regular pad and oversize soldermask pad for start layers in Backdrill Setup and Analysis
9 j6 p3 U/ s; W }+ B2091932 ALLEGRO_EDITOR OTHER Unsupported Prototypes command missing for the OrCAD licenses
7 X' Z9 B3 M& Q( w4 z1 C& w2221345 ALLEGRO_EDITOR OTHER Speed up Allegro PCB Editor startup by removing check for defunct PCB/Package co-design capability (NG_450)
* }1 W+ I$ H" w$ t! R" d. ? e2257934 ALLEGRO_EDITOR PLACEMENT Error (SPMHGE-626) on place component: Symbol not valid on any layer
1 w% r) j( t2 |: ?3 t& Q& X- M1001000 ALLEGRO_EDITOR PLOTTING File - Plot in PCB Editor does not plot more than one copy
$ x, t; I& U5 e! h. n5 F1 P! L2 l2234538 ALLEGRO_EDITOR REPORTS Allow Unused Blind/Buried Via report to run as Batch Process through the reports batch command: A: Y# X- |, G* E( w: w2 K" H$ ~. L
2222738 ALLEGRO_EDITOR SCHEM_FTB Netrev not completing, showing error for electrical constraints data (pstcmdb.dat) import
) U/ H' l2 a0 r4 K2255426 ALLEGRO_EDITOR SCHEM_FTB Netrev is running for hours without closing# B5 k* g7 o( W, M; p; d) a8 K$ o
1702190 ALLEGRO_EDITOR SCRIPTS Allegro PCB Editor script file: Some sub-classes not created and error for form field label; v7 j' y- O3 {0 u% t, c2 n$ U5 W
1791099 ALLEGRO_EDITOR SCRIPTS Allegro PCB Editor does not terminate when the script is run with '-nographic'2 p% P/ z$ U; ?; v* W8 P" n, g
1791267 ALLEGRO_EDITOR SCRIPTS Allegro PCB Editor script does not run with '-nograph' in release 17.2-2016. p6 M% H. l. `& G* }% z1 P" i
1892520 ALLEGRO_EDITOR SCRIPTS Allegro PCB Editor stops responding for script when run with '-nographic'
3 {3 Y* w, ?8 C3 S+ q1962010 ALLEGRO_EDITOR SCRIPTS Allegro PCB Editor stops responding for script when run with -nongraph option
9 o8 k- T0 Q, l7 k. y) p- ?1 A2056857 ALLEGRO_EDITOR SHAPE Shape boundary error by shape parameter
( y9 F5 h; r: O' W8 l8 d: j- p9 C2081946 ALLEGRO_EDITOR SHAPE Shape Update takes twice the time in release 17.2-2016, HotFix 053 as compared to HotFix 0475 b+ }# w- g. t3 b1 Y
2104559 ALLEGRO_EDITOR SHAPE PCB Editor crashes while performing shape operation 'andnot'; f- i g0 h# H, d- g, H7 q; b
2108207 ALLEGRO_EDITOR SHAPE No Void Overlap option is not working in Auto Metal Balancing (AMB). y- |. g& h' R! y D; D0 M, n" ~; Y
2240996 ALLEGRO_EDITOR SHAPE Detecting Shape Island: Ignored for copied or moved shape" L+ Y* c% ]- j9 B0 H) |
2258758 ALLEGRO_EDITOR SHAPE Allegro PCB Editor crashes when routing two signals together( i( u, D! D9 N* ^7 @6 d
717389 ALLEGRO_EDITOR skill Ability to set and return the application mode using SKILL7 U+ q* A) h# b& Q- U
853160 ALLEGRO_EDITOR SKILL Need ability to get and set application modes using SKILL6 y7 X/ V$ F& m) P, v. q1 m
981446 ALLEGRO_EDITOR SKILL Request the ability to get and set application modes using SKILL
3 K# d$ W1 J& i8 Q( U1235409 ALLEGRO_EDITOR SKILL SKILL option to get application mode# h; g1 {0 `% ~' h h
1316962 ALLEGRO_EDITOR SKILL SKILL option to switch between application modes( x% o0 N1 a& q( b8 ]
1553621 ALLEGRO_EDITOR SKILL Ability to change application modes using SKILL function/ Z* v( b7 {8 l4 I8 n& ?& i5 n
1885442 ALLEGRO_EDITOR SKILL Ability to change application modes using SKILL function.
- J+ Q* F9 N1 ]5 U4 m2080351 ALLEGRO_EDITOR SKILL SKILL to determine current application mode
" J' D, ~% L# Z2195645 ALLEGRO_EDITOR THIEVING Thieving pad cannot be added on some areas in the board in latest hotfix but could be added earlier
1 g) x, f5 n# E$ o x1721594 ALLEGRO_EDITOR UI_FORMS STEP name Filter for STEP Package mapping form should be case insensitive
0 e* ]5 M) v7 O$ Q# h" t8 O2090604 ALLEGRO_EDITOR UI_FORMS Undo/Redo UI grayed out when invoking Color192
' S1 n- A5 }! x O2203278 ALLEGRO_EDITOR UI_FORMS 'Width' keyword in Place Rectangle field is grayed out when Place Rectangle is selected) p2 y+ k4 ]) g) m4 H
2209172 ALLEGRO_EDITOR UI_FORMS Labels truncated by drop-down lists in Options ('Manufacture' - 'Drafting' - 'Relative Copy')
5 G' T3 w8 l! e8 i$ N; _2239426 ALLEGRO_EDITOR UI_FORMS Cannot start text size with decimal in 'Design Parameter Editor' - 'Text' for English (Denmark) regional settings" ?# N5 E1 l4 D% O3 b- d
2245035 ALLEGRO_EDITOR UI_FORMS The right edge of the default Define Grid form looks cut off in 17.4.
' a8 G1 o( ]- e( n$ ~1 V. c0 y5 Q2245955 ALLEGRO_EDITOR UI_FORMS Resizing of 'Reject Item Selection' window not possible in release 17.4-2019, HotFix 004& }0 q( K' ? W4 L4 u3 ?
2249202 ALLEGRO_EDITOR UI_FORMS Extra click required to activate Pass field in Autorouter form
. R5 |& T3 U( b5 v2259605 ALLEGRO_EDITOR UI_FORMS Add ability to resize Reject pop-up r/ N% i! z# O5 D; {( K9 F
2090517 ALLEGRO_EDITOR UI_GENERAL Shape visibility box is not being enabled with the Enable layer select mode option in the Visibility Pane. E# d3 ~( H& o2 H0 {3 G
2092436 ALLEGRO_EDITOR UI_GENERAL RefDes length of input string for Modify Design padstack is limited to 20 characters- h# v4 }' n0 L' Z' B# w5 [1 ~6 r
2134781 ALLEGRO_EDITOR UI_GENERAL The Pin Class is missing in Options tab when creating or opening a Mechanical Symbol
" l( ?7 R4 h/ H! r2168026 ALLEGRO_EDITOR UI_GENERAL Edit Properties UI slow to launch for boards with many drawing properties' h) Z/ e3 C7 P% S* u1 n/ V
2191267 ALLEGRO_EDITOR UI_GENERAL Changing Visibility of any object type disables links in Layer Select Mode in the Visibility pane
4 N0 z+ O- c. }2208018 ALLEGRO_EDITOR UI_GENERAL Text on BGA pins not visible in release 17.4-2019 if not zoomed to maximum
. R* Z; w* B) n" I# F7 f9 k2225753 ALLEGRO_EDITOR UI_GENERAL dark theme does not respect TRBICON size for 4K monitors$ g; o X K! ^: `: d
2256841 ALLEGRO_EDITOR UI_GENERAL Enlarge the Shape Copy to Layers form as the window is quite small and not resizable
, }) c4 V. w$ L2258019 ALLEGRO_EDITOR UI_GENERAL Canvas turns white after closing STEP Package Mapping window1 f5 M% `/ w1 P5 @1 o
2258167 ALLEGRO_EDITOR UI_GENERAL Enhance 'Shape copy to layers' window in release 17.4-2019 to expand or resize4 A2 S: C& F/ x
2262305 ALLEGRO_EDITOR UI_GENERAL Assign Differential Pair form list box size too small to add signals7 b; u) k9 }2 x1 l7 n! J8 ]: J
2086574 APD OTHER APD is showing duplicate layer text on the vias! x, R& q7 h7 _0 c; i6 w f5 ~6 A1 ~
1723825 APD SCRIPTS Allegro Package Designer in release 17.2 is not writing out to either jrl files or script files in real time.) O ~4 A G* F/ o+ a& b+ |9 Y/ z' D
2186363 APD UI_GENERAL Text on the Pin is not visible until zoomed in to certain extent5 m) ^: x! C+ b$ j% F6 _
2253484 APD WIREBOND APD stops responding when running 'wirebond soldermask create' with 'Measure from soldermask pad'
* d3 O" e6 r# y; l. n2241725 CAPTURE DRC Waive DRC option not working from batch DRC window0 |: ~4 Q5 b$ z/ e5 a% ^1 _
2243645 CAPTURE DRC Online DRC bug in release 17.4-2019, hotfix 004 - offpage connector does not have wire* Q5 D( Z, H( t; L) |
2250867 CAPTURE DRC Hanging wire custom DRC not working when selected standalone& b0 [2 ^3 t' d$ O; |% @- Y0 i# U
2252912 CAPTURE DRC Unable to create new DRC file using Browse button in DRC window
# t3 d3 h" _0 r4 v2047391 CAPTURE PART_EDITOR Pin type cannot be changed in release 17.2-2016, hotfix 051
( p* F) D# _4 @2183187 CAPTURE SCHEMATIC_EDI OrCAD Capture: Ctrl + N seems to call a legacy dialog that allows projects to be created with no name
$ U7 v2 A Q, V) Z# V" a2 b8 e2190602 CAPTURE SCHEMATIC_EDI Cascading options of Window menu not working in OrCAD Capture in release 17.4-2019* @" F% a, A9 C3 o4 ~
2194374 CAPTURE UX Design Sync issues: Session log does not report information about errors& z. g: |- m% v) n, b$ t
2183037 CIS LINK_DATABASE CTRL-L shortcut for Link DB-Parts for Query in CIS-Explorer not working
C9 O: M: U5 ^& Q4 W: ]! L2201323 CIS PLACE_DATABAS Capture CIS displays empty dialog on placing part from database in release 17.4-2019. u( X: i ^, q/ c6 Z& x
2216963 CIS PLACE_DATABAS Light Theme: Warning text not visible in Capture CIS dialog
) T& ^+ u/ C4 {$ ~; d4 V5 M0 K% [2246354 CIS PLACE_DATABAS Warning (ORCIS-6159) pop-up window is blank.( U% `2 ~6 m; D" l$ e# ^
2230651 concept_HDL CHECKPLUS Discrepancy in the 'checkplus' marker files
9 k9 D0 j! b# P {3 |2237145 CONCEPT_HDL CONSTRAINT_MG T-Points match groups get deleted after saving a design) P7 ?/ u4 l8 [7 C) h* i( Z
2246452 CONCEPT_HDL CORE Page information gets removed from 'master.tag' of the top-level design when subdesigns are read-only9 t6 L0 ]/ t/ b
2057490 CONSTRAINT_MGR CONCEPT_HDL Constraint Manager Worksheet flips after running hier_write when CM is open
) N( @* n4 i, P" j: y. g4 k6 ^2236329 CONSTRAINT_MGR CONCEPT_HDL Pin Pairs not added to Match Group2 w6 O# P6 @- N# \* M h: @6 k3 F
2214367 CONSTRAINT_MGR INTERACTIV CSet assignment matrix sorting in Net Class-class random in Capture to Constraint Manager flow8 o" J0 {9 W6 n4 D5 @
2243574 CONSTRAINT_MGR OTHER CM SKILL cmxlPutAttribute() cannot set constraint value
) X8 ~2 w! j% i- ]5 i( A4 J8 B" Z* z2259598 CONSTRAINT_MGR OTHER Importing netlist: Error for electrical constraint data (pstcmdb.dat) import0 X- |- ?1 M7 L% _
2207862 CONSTRAINT_MGR SYSCAP Save icon and 'File' - 'Save' menu in Constraint Manager is inactive
1 y \4 z f( s' {1 G, s2200316 CONSTRAINT_MGR UI_FORMS Expanding 'Analysis Mode' form resets column width8 t" Z% t/ `) }
2097479 PCB_LIBRARIAN CORE Symbol import in Part Developer does not show the correct pin shape.+ J h; G7 D, B" R X; U
2145385 PCB_LIBRARIAN CORE Error-SPLBPD-972 reports missing parentheses in the ALT_SYMBOLS property of a part/ D1 }( u; a$ L' d( B5 n' C4 g. U
2202622 PCB_LIBRARIAN CORE When adding a new pin to a symbol in Symbol Editor, the space between pins changes) k+ j v5 e1 E3 H2 k7 {
1955570 PCB_LIBRARIAN FLOW Using the PACK_SHORT property with more than 256 characters does not work or report an error on packaging
. m8 s- m3 J. P+ O2072190 PCB_LIBRARIAN FLOW Allow PACK_SHORT property value longer than 255 characters% P/ r. i: A8 A1 R
1720395 PCB_LIBRARIAN IMPORT_OTHER Converting OrCAD Capture OLB to Design Entry HDL library adds braces to pin number
# e6 T! d" m3 \9 g' J0 X% r; L8 ]7 g$ s2141340 PCB_LIBRARIAN SETUP SPLBPD-216 Error logged in PDV even when MAX_SIZE Sheet is defined
7 v! i' V& E5 z: d2214973 PCB_LIBRARIAN SETUP Unable to apply symbol property templates when PDV lock directives are set3 W6 L! k# v6 A2 r( `" y
2257527 PCB_LIBRARIAN SETUP Locking PDV directives prevents applying symbol property templates
`$ v }# |9 p) [: Y% n2033898 PCB_LIBRARIAN SYMBOL_EDITOR Running Symbol Editor with no arguments results in a background process, not an error.
% b% O; g3 H K3 J; y- r4 H2093849 PCB_LIBRARIAN SYMBOL_EDITOR Symbols and font sizes appear different when placed in designs
9 I6 A, J4 D7 N$ `! \2200399 PCB_LIBRARIAN SYMBOL_EDITOR Multiple issues observed when editing parts in the New Symbol Editor
! D% L9 E4 _: v+ i2218940 PCB_LIBRARIAN SYMBOL_EDITOR Duplicate pins cannot be removed7 H T7 d. s5 S
2230542 PCB_LIBRARIAN SYMBOL_EDITOR Bus pin location changes after expanding or collapsing pins in Symbol Editor
' ]( O' ?0 j9 H6 M s2239303 PCB_LIBRARIAN SYMBOL_EDITOR Expanding and collapsing a bus is changing the msb and lsb for the pin name
7 o0 S9 R" `0 G- ?+ k( {* A2243431 PCB_LIBRARIAN SYMBOL_EDITOR Group of pins that are not adjacent cannot be moved together2 }; A, A( ^' p2 O
2029056 PCB_LIBRARIAN SYMBOL_EDITOR Unable to change Grid Settings in Part Developer
' y# v1 p8 N3 x2149948 PCB_LIBRARIAN SYMBOL_EDITOR New Symbol Editor and System Capture moved pins from 0.01 grid to 0.05 grid.
& D) g! i% ?) z2 I2206975 Pspice MODELEDITOR PSpice Model Import Wizard symbol preview readability improvement requested5 a0 O; E6 S, S# s- O; u( [6 N8 j
2211187 PSPICE MODELEDITOR Model Editor color scheme not readable0 z' r& s7 K( y1 D Z. Z
2214415 PSPICE MODELEDITOR Symbol view in Model Import Wizard has a visibility problem- L8 ~* `" ~/ Q( r! q# _
2199570 PSPICE PROBE Unable to 'select sections' after Monte Carlo runs with Temperature
" `9 B5 ^" c9 b4 T+ c2244140 PSPICE PROBE Not able to select multiple sections to plot in probe3 u6 t* o9 k" X8 `" @" k
2249565 PSPICE PROBE Selecting multiple traces for PSpice A/D Monte Carlo run not working
9 u6 [. J& g+ E* u/ C2171626 PULSE CORE Pulse crashed with error related to third-party development kit platform issue- W$ V- E" y1 h% R
2221523 PULSE UNIFIED_SEARC Cannot log in to third-party search providers but can log in to Cadence Online Support
1 I0 f/ y# }) [ G: f( L2019229 RF_PCB OTHER Layer conversion file data does not update GDSII layer mapping using Package Symbol Wizard
+ d2 T' ^ P; h! \# o3 ]820288 SIP_LAYOUT COLOR Layer Priority command does not seem to be functioning
$ C( Q- ?0 p/ Q2 ^3 F820305 SIP_LAYOUT COLOR Layer Priority menus do not match the Color dialog in the package substrate tools2 @9 x) D& A" e1 \: ^: ?/ ]9 e
2256044 SIP_LAYOUT DATABASE Fix teardrop does not work for some situation: Deleting fixed fillets2 Y! t4 h Q' A E- A3 ^
2254932 SIP_LAYOUT DEGASSING APD Plus generating assertion failures when running degassing mode with script
& h4 d( p) }- y9 n2106314 SIP_LAYOUT INTERACTIVE Large design causing severe lag in Windows Server machine+ q; K9 `' [7 H& T& o- b: `1 f. I
2096239 SIP_LAYOUT STREAM_IF Database fails to create stream out file
% Z1 {! C' S) C% u3 i. N! K+ C2079071 SIP_LAYOUT SYMB_EDIT_APP Response very slow after Show IC Details on a very large co-design die
& L* i. `& B& P, L; S$ X0 Z3 n2251630 SIP_LAYOUT WIREBOND 'Change Profile' does not change the diameter of the wire bond: }# m( V0 Y! u- g9 y5 J
2253633 SIP_LAYOUT WLP Advanced degassing passing illegal arguments to dba routine
7 S8 ^% Y% q; U! X6 `2259630 SIP_LAYOUT WLP Advanced WLP: Import PVS DRC results in error+ n& M0 R0 m/ F4 z6 F5 j
1968437 SYSTEM_CAPTURE ASSIGN_SIGNAL Net name pasted in lower-case though uppercase input is enabled( F1 M" \6 T; Q- D7 R
2131976 SYSTEM_CAPTURE AUTOMATION syscap exits when run with the -tclfile argument and an invalid Tcl file
) ~( K* L" s% C' W1983063 SYSTEM_CAPTURE BLKDIAGRAM_AU Auto Shapes are being shown as part of components) S7 Y$ ~/ w' c, ~
1977673 SYSTEM_CAPTURE COMPONENT_BRO adding reference blocks through add component error when cell name matches design name
- v8 x& h4 t' {1 Y2247567 SYSTEM_CAPTURE COMPONENT_BRO Symbol property placeholder changes not updated on the canvas
' x/ d4 j3 h1 ?) b( o2027100 SYSTEM_CAPTURE COMPOSITE_FIL pstdedb.cdsz and netlist preview in System Capture is not being updated when individual netlist files are written
( J# @: k3 t; I7 b1863460 SYSTEM_CAPTURE DARK_THEME thumbnail preview of pages is in light them but dragging the page the previes is dark4 Y' q5 A& W$ w: ~) U: b1 T7 y
2168622 SYSTEM_CAPTURE EDIT_SEARCHRE Reports from Find Results are dumped even when the operation is canceled
4 w' u8 ]- ?/ X' Z1 ~" l- E2168625 SYSTEM_CAPTURE EDIT_SEARCHRE Sort icons for columns in 'Find Results' are incorrectly placed: appear to be in adjacent column
& l6 T7 Y& @% \/ z/ E x+ {& e6 l1895142 SYSTEM_CAPTURE EXPORT_PCB System Capture incorrectly reports unsaved changes when closing after running export physical
4 H, {3 p9 h/ l0 t. B1931660 SYSTEM_CAPTURE EXPORT_PCB SDA is non-responsive while Allegro launches and opens a board when launched from SDA
& c! Z; e6 a3 i0 A! z/ P9 [2087387 SYSTEM_CAPTURE EXPORT_PCB System Capture: After Export PCB completes, busy cursor shown for a while
3 O5 n! x9 @& T7 M! V2202179 SYSTEM_CAPTURE FIND_REPLACE Replacing a net name with the same name by using Find and Replace results in a crash+ k9 T$ j7 x# d3 o+ ?
1843885 SYSTEM_CAPTURE FORMAT_OBJECT Renaming a net causes it to lose custom color assignment; n: m: }: G) I. S
1993208 SYSTEM_CAPTURE FORMAT_OBJECT Setting font prior to placing text does not work, pop-up does not work, and bucket results in scrolling page- r. V. v7 }( R
2231399 SYSTEM_CAPTURE IMPORT_BLOCK 'importBlock' Tcl command not working when using a script
2 Y4 C7 ?) H/ k9 o1907729 SYSTEM_CAPTURE IMPORT_DEHDL_ Import DE-HDL sheets - differential pair properties on nets are lost
7 Y @3 P4 V3 ]1 {) z( o# }2025949 SYSTEM_CAPTURE IMPORT_DEHDL_ Title block and thick wires/lines of border in DE-HDL do not translate in System Capture: D4 A7 B0 L% a0 ~' C% R' [! K
1942542 SYSTEM_CAPTURE IMPORT_PCB System Capture - TDO backannotation overwrites net names with stale data in lower-level blocks% q% ~+ }1 [2 U# o; I5 v" |
1982320 SYSTEM_CAPTURE IMPORT_PCB View files are not created in the schematic-to-board flow: e+ [* T6 A0 t2 T) f# v$ Y B) j
2117532 SYSTEM_CAPTURE MENUS_AND_TOO Ability to customize menus for a site
5 d9 Y7 o- |. \, {2213478 SYSTEM_CAPTURE MENUS_AND_TOO Help - About menu item appears twice
6 O& T) x0 l# }) ^/ M1910941 SYSTEM_CAPTURE MISCELLANEOUS Parts that are not in any schematic page appear in netlist and BOM. @' }8 g$ s: n: p8 m4 C
1967614 SYSTEM_CAPTURE MISCELLANEOUS Dragging a circuit with net aliases does not move the net aliases with it2 k9 `, H, S$ m
2189846 SYSTEM_CAPTURE MISCELLANEOUS Inconsistent display of same font
* b! Q+ x$ A* B$ o! d7 J; a2178961 SYSTEM_CAPTURE NOTES Cannot add Japanese text in notes in release 17.4-2019 on Windows 101 D2 v, Q7 K$ t3 N& Q7 M( E+ t% _: ]
1973437 SYSTEM_CAPTURE OPEN_CLOSE_PR Opening a design crashes System Capture
% v4 O; w" h5 X0 M2079857 SYSTEM_CAPTURE OPEN_CLOSE_PR System Capture: Unable to select design to open if license selection box is canceled the first time
( e1 }+ W9 i2 |2065025 SYSTEM_CAPTURE PACKAGER Export to PCB Layout reports wrong path but exports correctly- O; {+ a% r, x
2229611 SYSTEM_CAPTURE PACKAGER Path for the 'packaged' folder shown in the 'Export Physical' is incorrect9 V' V: q' }$ i3 m5 h) R" U% a
1993146 SYSTEM_CAPTURE PROJECT_EXPLO Cannot move page up by only one position
& h2 K( |2 S) G1892120 SYSTEM_CAPTURE PROPERTY_EDIT Some parts are missing reference designators and some have two properties - RefDes and REFDES" A& [* v. Q+ @* z: G2 i
2201060 SYSTEM_CAPTURE PROPERTY_EDIT Some of the icons in the Properties window do not have tooltips
. b" o$ ?$ G7 p- K+ o+ \( M. u: [2246667 SYSTEM_CAPTURE SCRIPTING Running the 'replay.tcl' script gives an invalid command name error
# x6 \8 o9 F9 I. J0 q$ Q1 R2010032 SYSTEM_CAPTURE SHORTCUTS Cannot enter Page-Up/Page-Down as shortcuts4 q% @- Y& v# ]: P
2017985 SYSTEM_CAPTURE TDO Allegro System Capture ability for multiple users to open a design; n v- N3 R$ }& V) v
2106743 SYSTEM_CAPTURE TDO Ability for multi-user access to the same schematic
0 ^$ p. U, F# e, `$ o4 {+ B& x2209628 SYSTEM_CAPTURE UI Tooltips for Design Rule Checks are getting truncated6 d b( \5 y* h5 U# c
1990258 SYSTEM_CAPTURE VARIANT_MANAG Cannot paste copied preferred part to multiple parts with the same part number
+ b3 t) U8 j" U" o# \+ i2032005 SYSTEM_CAPTURE VARIANT_MANAG Custom variables not saved for variants
+ m% Q0 L; @* e2228299 SYSTEM_CAPTURE VARIANT_MANAG CAP parts should not show up in the Preferred Parts list when changing a RES
2 E2 _% ~* f) D$ z/ ^1627835 SYSTEM_CAPTURE WIRING Inconsistencies in wire movements5 s0 Q; |, p: B8 a$ w* r
1670888 SYSTEM_CAPTURE WIRING Rotation error when a component is connected to a power symbol0 M6 M6 N T" L8 q
1721863 SYSTEM_CAPTURE WIRING Net names move to random locations when components are moved around the canvas.+ e. @. |# h+ _ {5 W; L
1960130 SYSTEM_CAPTURE WIRING Disconnected nets when using the mirror option
" {- c! Z( b; y+ E+ l: r$ f1961274 SYSTEM_CAPTURE WIRING XNet removed during pin swapping
; h+ i1 w. W/ K3 \1968463 SYSTEM_CAPTURE WIRING System Capture should not allow illegal characters to be entered for net names4 J* X' _; O0 L6 u1 p. @1 J+ v
1973426 SYSTEM_CAPTURE WIRING Selecting multiple net names and trying to delete only deletes one net name.
' R0 {- y. S: B* W1978381 SYSTEM_CAPTURE WIRING 'oops' does not remove the first vertex placed/ I- h2 ?; A! [8 q; Q* J6 p
1985029 SYSTEM_CAPTURE WIRING Net aliases are not dragged with circuit, they appear to move after the circuit is dropped
) M0 t, x- G+ B- [# G2013647 SYSTEM_CAPTURE WIRING Replacing a vertically oriented RES with a horizontal CAP breaks the wire connections6 e2 T) z- [7 A7 K) [/ w
2014188 SYSTEM_CAPTURE WIRING Context menu not working in Variant mode2 @# O. V Q$ K
2041879 SYSTEM_CAPTURE WIRING XNets generated for nets with pull-up resistors
1 E7 u5 a7 ]2 Z2050533 SYSTEM_CAPTURE WIRING Need an option to increase junction dot size0 E% Q# N& c& { W. T
2061877 SYSTEM_CAPTURE WIRING Unable to add a power symbol with the Place - Special Symbol menu
) x5 c5 w4 d, J* r0 o2079409 SYSTEM_CAPTURE WIRING Increase the size of the wire connection dot in System Capture% I# R- H3 \& e; _
2081884 SYSTEM_CAPTURE WIRING Symbols take a long time to move, and results in DRCs and broken connections
) b/ V' ~" F( e: \& W2085263 SYSTEM_CAPTURE WIRING System Capture: Focus lost from the Format tab if font name starting with typed letter is not present8 q7 h& m$ q+ m
2089569 SYSTEM_CAPTURE WIRING Ability to specify the solder dot radius size
0 j I% @' A2 g! Q$ t& p2 M6 Z2 r+ I7 h
QIR1详细特性说明：
Hotfix_SPB17.40.007_README-Release_Notes.pdf
(2.51 MB, 下载次数: 55)
% `; v% l. l1 C& p
待我上传完后附上链接，这次QIR1比较大，4.59 GB * T) S4 Z6 `! B" Q; m/ D8 j
5 X- c6 a4 i3 F F6 k* U4 S
% u9 m7 e Y8 {: v N" a+ _$ h" c9 f5 T f' d; y+ d
' w: }' A$ M* M3 K0 t" f: O/ m7 R
$ J8 [7 f! F$ Q Y( H
; k" m6 w9 V0 p o4 S I: c' @, W6 B9 h/ p3 Q- R5 I) ?
) n* y0 Z C; B
3 {% c+ r7 T: G0 C1 T7 j! b+ [
( S. o% C: M: M/ Y, g, t
* U0 g& k& d: N5 H4 C
' @6 H7 T% }3 K2 o+ M0 e X7 G2 a9 X! j, X
* |6 ^: c& P' | W; T* f0 S' x" N/ ]5 o* L2 j6 H
8 u! e7 `9 p* L; z) F$ c, X! A; H
! C7 \4 {3 m) l% O& M |
|
/1 
发表于 2020-6-8 02:00
收藏
淘帖
支持！
反对！
发表于 2020-6-8 09:10
楼主
