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本帖最后由 金志峰 于 2020-6-8 03:33 编辑
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cadence orcad and allegro 17.4-2019 QIR1新特性 6 Q, e/ k* g' E- \
·焕然一新的图标及UI a b$ @1 \5 H- n: }
6 a8 _8 e$ X2 K* y/ VQIR1中全新启动界面 （点击图片放大）$ M1 U D* w4 C" b$ ?4 \ z ]3 K
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QIR1中全新启动界面（点击图片放大）5 L' j8 n5 A! K" ~4 n) L
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QIR1中capture官方Dark主题（点击图片放大）(QIR1中UI界面中所有图标也全部更换全新并统一了)
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QIR1中capture官方Light主题（点击图片放大）& h7 y" L" f m
(QIR1中UI界面中所有图标也全部更换全新并统一了)
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. \- a) Z! z0 |9 GQIR1中PCB Editor新增官方Dark主题（点击图片放大）
6 P3 ?; b) U2 j2 O* q3 ~(QIR1中UI界面中所有图标也全部更换全新并统一了)) k/ [4 d9 x g& {. k
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QIR1中PCB Editor官方Light主题（点击图片放大）! W4 m# n/ [. T8 p! d
(QIR1中UI界面中所有图标也全部更换全新并统一了)5 C8 K$ J8 C5 a6 T9 K/ v3 v
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+ } A( J* h( [2 {7 M$ X4 K( U# mFixed CCRs: SPB 17.4 HF0076 X w! G$ ~( H9 q# \
05-21-2020
& N* g/ Q, j- @ i8 A5 G+ d========================================================================================================================================================
; m8 O) T4 c+ ~: FCCRID Product ProductLevel2 Title
+ p* V7 K5 z. R========================================================================================================================================================
( S1 ?; g% Q/ H+ f2247686 ADW CORE Allegro EDM: Unable to create a project using a newly created flow8 H3 Q' ^+ ]; p& d7 c
2137594 ADW DBADMIN EDM is not allowing changes to STEP models \' v( k3 B; b
2135452 ADW DBEDITOR DBEditor poor peRFormance in high-latency networks
- I8 G0 N7 A g- f. `7 N2113265 ADW LIBDISTRIBUTI Various database operations take a long time; rebooting server seems to fix the problem
/ K. E# Z; } X3 n8 I* @2122941 ADW LIBDISTRIBUTI Lib_dist execution taking a long time to run; Capture CIS DBC file appears to be taking the most time
8 a! p( \& F' W* }9 ~2127319 ADW LIBDISTRIBUTI Library distribution fails at cisexport function with error (ORCIS-6250)" r2 Z# H0 j2 b# I
1975317 ADW PART_BROWSER Space at the end of the line in CDS.LIB results in zero libraries being shown in System Capture library search& _1 {4 s- Y" T0 q+ B9 T
2078057 ADW PART_BROWSER Symbol Graphics preview is not available in Designer Servers/ P; s9 h+ H! E7 u3 p; s4 n
2092863 ADW PART_BROWSER System Capture library search is not displaying the symbol and footprint preview
5 S0 F( _2 p2 ~6 I$ \2086463 ADW PART_MANAGER System Capture cannot add components when accessing remote machine via Citrix
: C3 e+ J" \5 z% S, y2 j; [( ^2092868 ADW PART_MANAGER Release 17.2-2016, HotFix 054: Empty cache.ptf causing injected properties to not flow from pstchip
' L* y% t$ |6 H3 B) E2092872 ADW PART_MANAGER System Capture stops responding when importing from DE-HDL# f0 e& E- s4 O9 b; t
2113226 ADW PART_MANAGER System Capture stops responding while importing DE-HDL sheets
# W$ \4 P2 x# {' C! T2212406 ADW PART_MANAGER Allegro System Capture: Part Manager is deleting properties from all instances upon Update
5 b" I0 ^) E6 k/ B7 V2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name4 X: k% I+ @% r" V) m
2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to Team Design# q' U. m8 x j$ \
2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object
7 Y% x6 p) p; g) n/ q* C$ C, v2048086 ALLEGRO_EDITOR 3D_CANVAS Wire bonds are not linked to die pad when component is embedded body down1 }( V# J- b( o/ H# B' v8 X/ z/ A
2051277 ALLEGRO_EDITOR 3D_CANVAS Vias are offset from board in Z direction in 3D Canvas
. Q! U) l3 }; j1 `1 z2054243 ALLEGRO_EDITOR 3D_CANVAS Plating is not shown on stacked vias in 3D canvas
$ b, Q, q: K, w- \: Q5 |. v2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation9 k- V% d1 Z8 {* y2 q$ _2 ]
2079732 ALLEGRO_EDITOR 3D_CANVAS Enhance 3D Canvas to merge the lines segment and overlapping lines and shapes
9 [6 U. [0 r4 ^( B! N+ B% i2206045 ALLEGRO_EDITOR ARTWORK Artwork Control Form fails to create film if Film record has a period (.) in the title( z' ~ u V0 V8 Q" d* ?' O1 @
2209200 ALLEGRO_EDITOR ARTWORK PCB Editor stops responding on rebuilding apertures without rotation+ A( b4 E8 ]) ^; ]' p
2244407 ALLEGRO_EDITOR ARTWORK Automatic editing apertures with rotation takes time in the General Parameters tab of Artwork Control Form
+ _4 e0 v9 w9 c2267942 ALLEGRO_EDITOR ARTWORK Allegro PCB Editor stops responding when generating apertures in HotFix 006
' o9 N9 E7 W+ F567342 ALLEGRO_EDITOR COLOR Add option under View menu for 'load color view'
9 v1 k4 s" I, \* o637828 ALLEGRO_EDITOR COLOR Line highlights in 'shape select' command/ m k" }7 B* B
720274 ALLEGRO_EDITOR COLOR Add menu option for the 'colorview load' command1 Z+ r$ z7 _3 S# e
1602652 ALLEGRO_EDITOR COLOR Color/Visibility behavior variation using "Enable Layer Select Mode"8 x! |: M% n! B8 a# d5 m3 Y
2072695 ALLEGRO_EDITOR COLOR Clines of colored nets not colored when 'display_nohighlight_priority' is set# ~/ e: q% g" ^6 a6 g
2207580 ALLEGRO_EDITOR COLOR Component color is inconsistent when display_nocolor_dynamics is set.# f0 Y F% G/ n& n4 h1 m1 K
2056497 ALLEGRO_EDITOR DATABASE Place manual is slow7 K9 y5 Y+ j" n0 v
2250988 ALLEGRO_EDITOR DATABASE Inner Layer keep out as illegal subclasses: Shape object may not exist on layer ROUTE KEEPOUT/INNER_SIGNAL_LAYERS0 D9 a3 ^8 K0 m; R, K! `
2096958 ALLEGRO_EDITOR DFA Cannot launch Constraint Manager after assigning CSet and closing$ ^: m9 d1 r) B$ b! S
2049681 ALLEGRO_EDITOR DFM DFF check for plating in via should not flag DRC for surface mount testpoint Via
: ^) [5 c! ]4 n2155060 ALLEGRO_EDITOR DFM Inconsistent behavior in displaying DRCs for Via to Via spacing
4 J$ ]* O' Y3 i, K' [$ S2166431 ALLEGRO_EDITOR DFM DesignTrue annular ring thru pin pad to mask checks compared to smd pin to mask checks are inconsistent in behavior
6 ]% i" }: Y$ d9 n; I: l2221975 ALLEGRO_EDITOR DFM DFM missing mask check reporting mask is missing when pins have a mask geometry overlaying them.3 y+ t& f6 J1 i1 P9 }/ ~
2249498 ALLEGRO_EDITOR DRAFTING When a Symbol with a Dimension is placed on the board, an extra Dimension is added to the Symbol origin.
4 a* f) k; w+ Z8 S; S# V2250631 ALLEGRO_EDITOR DRC_CONSTR Cannot import netlist into design due to illegal DRC element: no DBDoctor error" Z4 L# D' H, N3 C" P- G
1794593 ALLEGRO_EDITOR EDIT_ETCH Unable to deselect return path vias selected when creating High-speed via structures
+ t( N: j; Z, N- E' `2099538 ALLEGRO_EDITOR EDIT_ETCH Gloss - Via Eliminate shifts traces to another layer9 V& [$ o/ b8 \
2204339 ALLEGRO_EDITOR EDIT_ETCH Differential pair line lost during slide operation8 Q" p5 w; i8 c
2208938 ALLEGRO_EDITOR EDIT_ETCH Slide operation makes one of the differential pair cline invisible
; h% W, n: t; | ~2222047 ALLEGRO_EDITOR EDIT_ETCH One of the traces disappear when sliding a differential pair in single trace mode$ K+ X- x" ] t( U1 {! e% m
2233991 ALLEGRO_EDITOR EDIT_ETCH One cline of a differential pair disappears temporarily upon sliding the Differential Pair in Single Trace Mode! m. R f! X, U2 @- F
2240827 ALLEGRO_EDITOR EDIT_ETCH Cline of a Differential pair net disappears after sliding the other net of the Differential pair& n% Q! e& z8 Z' I( B( @; d) u
2245775 ALLEGRO_EDITOR EDIT_ETCH Differential pair slide in single trace mode removes other trace7 _$ f+ c z! w+ l( Y
1813358 ALLEGRO_EDITOR GRAPHICS Allegro PCB Editor enables shape boundary when disabling etch layer in Visibility pane: U7 Y! r( ~0 |2 h
1911613 ALLEGRO_EDITOR GRAPHICS The subclass for boundary class stays on, even if Subclass for Etch Class is turned off from Visibility tab, I3 F- S8 O) _. y N/ I$ E% ]
1966343 ALLEGRO_EDITOR GRAPHICS Shape boundary remains enabled even after turning off the etch layer visibility. `; M! H1 q% v0 X- H6 J
2195276 ALLEGRO_EDITOR GRAPHICS Selecting File view is slow4 ~' z R* Z$ D+ R$ I9 b
2031883 ALLEGRO_EDITOR INTERACTIV Sub-Drawing: Clipboard origin point is not set correctly
& W. s( v6 Y/ K M2050177 ALLEGRO_EDITOR INTERACTIV Letters need to remain aligned and uniform after performing Shape ANDNOT operation$ o# M: n% X! ?- p% j
2069247 ALLEGRO_EDITOR INTERACTIV DFA bubble on wrong layer after mirroring the part" s: H( g5 f5 V2 `9 t+ B
2103711 ALLEGRO_EDITOR INTERACTIV Placement edit mode popup 'Rotate' leaves ghost image in the background* ] ^) M* Y' C X$ w! {
2136859 ALLEGRO_EDITOR INTERACTIV DFA Problem if we mirror component while placing
: Q( ]3 X" N/ E+ \2165027 ALLEGRO_EDITOR INTERACTIV Different behavior in OrCAD Capture when using crossprobe to select Power nets
' ]8 S/ P8 l$ v0 P2240235 ALLEGRO_EDITOR INTERACTIV The design file name changes automatically to board template name while creating new board (wizard).2 a. O6 e1 t& ~ y, t
2244765 ALLEGRO_EDITOR INTERACTIV License 4150+226 does not have AiDT/AiPT in release 17.2-2016" h& a; E) N: G! ^! x% m+ M
2259800 ALLEGRO_EDITOR INTERACTIV DFA DRC circle not shown on the layer of placement in Placement App Mode; ?4 L2 i5 L* N" O8 q- N2 ]1 y" ^
2120420 ALLEGRO_EDITOR INTERFACES Drill figures missing in the exported PDF if drill legend deleted$ D' U& f( F6 B
2136454 ALLEGRO_EDITOR INTERFACES Export - PDF output is not correct
0 x8 P# _. C! r/ }( P, P- i2116748 ALLEGRO_EDITOR IN_DESIGN_ANA Impedance vision data not available for cline segments for some nets
2 r+ I% B& s' v! q. R6 M2138977 ALLEGRO_EDITOR IN_DESIGN_ANA Impedance check results are incorrect and Crosstalk analysis stops running after updating to 17.2-2016, HotFix 057
7 ?5 ^. q+ t \6 m* \* ?2247167 ALLEGRO_EDITOR IN_DESIGN_ANA IDA Impedance Analysis: Add an option to export CSV automatically# _+ p: L4 n: c# j* Y* c$ p- F1 [
2222638 ALLEGRO_EDITOR IPC Documentation Editor crashes with error: Failed to complete the job because of unspecified error; \- i7 ?: a7 W5 l
2106425 ALLEGRO_EDITOR NC Disable undersize regular pad and oversize soldermask pad for start layers in Backdrill Setup and Analysis6 C7 _9 V9 p; m7 l: X% Q1 F
2091932 ALLEGRO_EDITOR OTHER Unsupported Prototypes command missing for the OrCAD licenses
) d! f9 o6 F6 K: h2221345 ALLEGRO_EDITOR OTHER Speed up Allegro PCB Editor startup by removing check for defunct PCB/Package co-design capability (NG_450)2 u3 P% B4 N G/ h2 S; R" ^4 T
2257934 ALLEGRO_EDITOR PLACEMENT Error (SPMHGE-626) on place component: Symbol not valid on any layer
9 Q2 s; P0 f/ e- x/ ~5 b) b) _1001000 ALLEGRO_EDITOR PLOTTING File - Plot in PCB Editor does not plot more than one copy
# x: o7 [6 S3 X% ^2 k2234538 ALLEGRO_EDITOR REPORTS Allow Unused Blind/Buried Via report to run as Batch Process through the reports batch command4 }: r4 Q9 M9 r/ {
2222738 ALLEGRO_EDITOR SCHEM_FTB Netrev not completing, showing error for electrical constraints data (pstcmdb.dat) import
$ G$ x6 D# h9 W( \. X* k7 _4 ^% ^2255426 ALLEGRO_EDITOR SCHEM_FTB Netrev is running for hours without closing0 @& c! D' X" R, V% m
1702190 ALLEGRO_EDITOR SCRIPTS Allegro PCB Editor script file: Some sub-classes not created and error for form field label L. c l. _& N! B! n0 _' Z" F
1791099 ALLEGRO_EDITOR SCRIPTS Allegro PCB Editor does not terminate when the script is run with '-nographic'- _* b5 P; s+ }+ A3 e% j" U
1791267 ALLEGRO_EDITOR SCRIPTS Allegro PCB Editor script does not run with '-nograph' in release 17.2-2016
; Y# X/ h- d9 l {) ?2 ~5 ?1892520 ALLEGRO_EDITOR SCRIPTS Allegro PCB Editor stops responding for script when run with '-nographic'
# s- f6 b# \* {' T, y+ a* @1962010 ALLEGRO_EDITOR SCRIPTS Allegro PCB Editor stops responding for script when run with -nongraph option2 S: f s! D1 x5 e! a& i
2056857 ALLEGRO_EDITOR SHAPE Shape boundary error by shape parameter+ j* X, a5 Q G) j1 s9 k
2081946 ALLEGRO_EDITOR SHAPE Shape Update takes twice the time in release 17.2-2016, HotFix 053 as compared to HotFix 047, C5 o3 Q! ]! |0 I8 Z
2104559 ALLEGRO_EDITOR SHAPE PCB Editor crashes while performing shape operation 'andnot'
! r& p& z2 }) L9 w/ ~4 A2108207 ALLEGRO_EDITOR SHAPE No Void Overlap option is not working in Auto Metal Balancing (AMB)
0 Z1 Z/ C. i0 A2240996 ALLEGRO_EDITOR SHAPE Detecting Shape Island: Ignored for copied or moved shape2 q4 N( z3 R! y: p4 R1 i3 D
2258758 ALLEGRO_EDITOR SHAPE Allegro PCB Editor crashes when routing two signals together2 {! ~0 R4 J7 [, `
717389 ALLEGRO_EDITOR skill Ability to set and return the application mode using SKILL% o# J. S" b1 d1 g
853160 ALLEGRO_EDITOR SKILL Need ability to get and set application modes using SKILL
$ t6 T- W1 }- M6 n4 c# F6 v981446 ALLEGRO_EDITOR SKILL Request the ability to get and set application modes using SKILL; E& f9 g* u. G9 v- l) Q
1235409 ALLEGRO_EDITOR SKILL SKILL option to get application mode2 }- r$ `% @! n7 L* S
1316962 ALLEGRO_EDITOR SKILL SKILL option to switch between application modes( E# `: a& E. ]# r6 v) }3 v
1553621 ALLEGRO_EDITOR SKILL Ability to change application modes using SKILL function7 j5 A5 y& c! L9 }% b$ h" i" t
1885442 ALLEGRO_EDITOR SKILL Ability to change application modes using SKILL function.7 o, `6 N( ^' q5 M
2080351 ALLEGRO_EDITOR SKILL SKILL to determine current application mode5 g# ]: k# e3 E; A+ e
2195645 ALLEGRO_EDITOR THIEVING Thieving pad cannot be added on some areas in the board in latest hotfix but could be added earlier! [9 ~5 @9 w }) J, b
1721594 ALLEGRO_EDITOR UI_FORMS STEP name Filter for STEP Package mapping form should be case insensitive
5 W1 ], `2 E4 V2090604 ALLEGRO_EDITOR UI_FORMS Undo/Redo UI grayed out when invoking Color1920 {1 e4 ~) T, y! \
2203278 ALLEGRO_EDITOR UI_FORMS 'Width' keyword in Place Rectangle field is grayed out when Place Rectangle is selected7 {! [. }/ B: C
2209172 ALLEGRO_EDITOR UI_FORMS Labels truncated by drop-down lists in Options ('Manufacture' - 'Drafting' - 'Relative Copy')! y- D6 H$ b" |2 u& \, h: p- I
2239426 ALLEGRO_EDITOR UI_FORMS Cannot start text size with decimal in 'Design Parameter Editor' - 'Text' for English (Denmark) regional settings( O- \; a( H5 s8 s+ ~0 m- H
2245035 ALLEGRO_EDITOR UI_FORMS The right edge of the default Define Grid form looks cut off in 17.4.; W/ O4 n$ ^$ \' W" P B
2245955 ALLEGRO_EDITOR UI_FORMS Resizing of 'Reject Item Selection' window not possible in release 17.4-2019, HotFix 0046 b$ w' E+ _# b# d0 F8 d
2249202 ALLEGRO_EDITOR UI_FORMS Extra click required to activate Pass field in Autorouter form
/ |; g O" l0 x w$ Z. p/ F2259605 ALLEGRO_EDITOR UI_FORMS Add ability to resize Reject pop-up$ T E& u# S3 Z' \$ x! y* U8 S
2090517 ALLEGRO_EDITOR UI_GENERAL Shape visibility box is not being enabled with the Enable layer select mode option in the Visibility Pane
& f, r9 f* j9 z) R) l6 g9 D# Y" ~# W2092436 ALLEGRO_EDITOR UI_GENERAL RefDes length of input string for Modify Design padstack is limited to 20 characters
- [4 E5 m! T, x; H- X" a0 N1 n: `4 E2134781 ALLEGRO_EDITOR UI_GENERAL The Pin Class is missing in Options tab when creating or opening a Mechanical Symbol8 d" q5 z# d6 f) s! ?2 W) _9 B* `
2168026 ALLEGRO_EDITOR UI_GENERAL Edit Properties UI slow to launch for boards with many drawing properties( p' T2 g9 z8 k; V
2191267 ALLEGRO_EDITOR UI_GENERAL Changing Visibility of any object type disables links in Layer Select Mode in the Visibility pane
& O" M9 R- d" f2 q& A6 Y+ g2208018 ALLEGRO_EDITOR UI_GENERAL Text on BGA pins not visible in release 17.4-2019 if not zoomed to maximum
" B5 J& ?# u* M6 k5 _- p* Q2 S2225753 ALLEGRO_EDITOR UI_GENERAL dark theme does not respect TRBICON size for 4K monitors
) q4 `, C6 m" k2256841 ALLEGRO_EDITOR UI_GENERAL Enlarge the Shape Copy to Layers form as the window is quite small and not resizable
- g1 V6 I5 |" D" A8 q/ S2258019 ALLEGRO_EDITOR UI_GENERAL Canvas turns white after closing STEP Package Mapping window
* g$ _! J, t2 z- v' Y1 ^2258167 ALLEGRO_EDITOR UI_GENERAL Enhance 'Shape copy to layers' window in release 17.4-2019 to expand or resize
$ t! t" x, L: `6 T/ |% A2262305 ALLEGRO_EDITOR UI_GENERAL Assign Differential Pair form list box size too small to add signals
3 q e( ^) [* f2086574 APD OTHER APD is showing duplicate layer text on the vias
: z4 i' | f0 z9 _3 e! }) X6 X. O7 ?1723825 APD SCRIPTS Allegro Package Designer in release 17.2 is not writing out to either jrl files or script files in real time. s9 W$ H4 [4 t3 A
2186363 APD UI_GENERAL Text on the Pin is not visible until zoomed in to certain extent
; e" S) M; n# [% ~' O; j( ]# }2253484 APD WIREBOND APD stops responding when running 'wirebond soldermask create' with 'Measure from soldermask pad'
7 w5 e+ S6 t6 X; F2241725 CAPTURE DRC Waive DRC option not working from batch DRC window
1 q, c1 x8 n" _. D% k2243645 CAPTURE DRC Online DRC bug in release 17.4-2019, hotfix 004 - offpage connector does not have wire! {! I. {( F {* s
2250867 CAPTURE DRC Hanging wire custom DRC not working when selected standalone! B: D" ]& ^6 F
2252912 CAPTURE DRC Unable to create new DRC file using Browse button in DRC window* m- @7 n; t# F# H3 y) {
2047391 CAPTURE PART_EDITOR Pin type cannot be changed in release 17.2-2016, hotfix 051( K* Y+ w5 d) S1 X
2183187 CAPTURE SCHEMATIC_EDI OrCAD Capture: Ctrl + N seems to call a legacy dialog that allows projects to be created with no name
# I* t8 g L( M1 Y: J2190602 CAPTURE SCHEMATIC_EDI Cascading options of Window menu not working in OrCAD Capture in release 17.4-2019
0 u9 W4 `" M" Q4 f) ^. ^2194374 CAPTURE UX Design Sync issues: Session log does not report information about errors
z8 u$ v8 n0 C( w$ a% Q2183037 CIS LINK_DATABASE CTRL-L shortcut for Link DB-Parts for Query in CIS-Explorer not working
9 b0 W' b- y+ E: l3 i6 w+ Z& M2201323 CIS PLACE_DATABAS Capture CIS displays empty dialog on placing part from database in release 17.4-2019% p1 L- b- ? T3 c/ }
2216963 CIS PLACE_DATABAS Light Theme: Warning text not visible in Capture CIS dialog# |6 \0 v) ~; K% t
2246354 CIS PLACE_DATABAS Warning (ORCIS-6159) pop-up window is blank.' P9 S9 y/ W& Z2 k& |! S
2230651 concept_HDL CHECKPLUS Discrepancy in the 'checkplus' marker files$ H1 C: w5 ?9 D
2237145 CONCEPT_HDL CONSTRAINT_MG T-Points match groups get deleted after saving a design: }8 ?8 g q5 X! T1 _5 @
2246452 CONCEPT_HDL CORE Page information gets removed from 'master.tag' of the top-level design when subdesigns are read-only: w. [0 w, O0 y$ ]7 y# [
2057490 CONSTRAINT_MGR CONCEPT_HDL Constraint Manager Worksheet flips after running hier_write when CM is open0 d7 ]# A0 c9 G1 n8 j
2236329 CONSTRAINT_MGR CONCEPT_HDL Pin Pairs not added to Match Group
! A2 ^. f! B! \/ @1 g/ X; T- c2214367 CONSTRAINT_MGR INTERACTIV CSet assignment matrix sorting in Net Class-class random in Capture to Constraint Manager flow, K& V7 M' U* U* W, T( B
2243574 CONSTRAINT_MGR OTHER CM SKILL cmxlPutAttribute() cannot set constraint value
# i$ V( ~$ P5 I/ m2259598 CONSTRAINT_MGR OTHER Importing netlist: Error for electrical constraint data (pstcmdb.dat) import1 \+ t% M' L, o. z& _3 k6 d
2207862 CONSTRAINT_MGR SYSCAP Save icon and 'File' - 'Save' menu in Constraint Manager is inactive
" P1 W; l! Q$ K p! m2200316 CONSTRAINT_MGR UI_FORMS Expanding 'Analysis Mode' form resets column width" t% o+ v; p$ W8 G
2097479 PCB_LIBRARIAN CORE Symbol import in Part Developer does not show the correct pin shape.& _* k7 C" c$ ^3 y& A" `
2145385 PCB_LIBRARIAN CORE Error-SPLBPD-972 reports missing parentheses in the ALT_SYMBOLS property of a part
% T( Y7 f, O. [, X5 I9 r2202622 PCB_LIBRARIAN CORE When adding a new pin to a symbol in Symbol Editor, the space between pins changes8 N0 T( H3 X, k2 o- k
1955570 PCB_LIBRARIAN FLOW Using the PACK_SHORT property with more than 256 characters does not work or report an error on packaging
6 P7 K* q* c8 [6 n' a3 k2072190 PCB_LIBRARIAN FLOW Allow PACK_SHORT property value longer than 255 characters
: Z* s3 b# Q( V/ J4 q; }1720395 PCB_LIBRARIAN IMPORT_OTHER Converting OrCAD Capture OLB to Design Entry HDL library adds braces to pin number
9 e6 d% e0 b& K1 G2141340 PCB_LIBRARIAN SETUP SPLBPD-216 Error logged in PDV even when MAX_SIZE Sheet is defined/ ^6 j( Y% t6 K0 o
2214973 PCB_LIBRARIAN SETUP Unable to apply symbol property templates when PDV lock directives are set
& L" Z* H# x* s# u- d2257527 PCB_LIBRARIAN SETUP Locking PDV directives prevents applying symbol property templates4 E4 x# {# `) E* P) k9 f& T% B! A' c% v
2033898 PCB_LIBRARIAN SYMBOL_EDITOR Running Symbol Editor with no arguments results in a background process, not an error.
- s' @# c& h" A) p8 ?8 V4 t$ n2093849 PCB_LIBRARIAN SYMBOL_EDITOR Symbols and font sizes appear different when placed in designs4 H) t4 H* x h% P
2200399 PCB_LIBRARIAN SYMBOL_EDITOR Multiple issues observed when editing parts in the New Symbol Editor" U3 \$ l# a+ L
2218940 PCB_LIBRARIAN SYMBOL_EDITOR Duplicate pins cannot be removed
# j. _/ v }# |: l# U" `2230542 PCB_LIBRARIAN SYMBOL_EDITOR Bus pin location changes after expanding or collapsing pins in Symbol Editor
5 h8 f# H L+ G& A* g. Q& b) V7 C8 G2239303 PCB_LIBRARIAN SYMBOL_EDITOR Expanding and collapsing a bus is changing the msb and lsb for the pin name
9 _8 _' Z& D0 @5 ]2243431 PCB_LIBRARIAN SYMBOL_EDITOR Group of pins that are not adjacent cannot be moved together# n' h) F7 b: D5 f
2029056 PCB_LIBRARIAN SYMBOL_EDITOR Unable to change Grid Settings in Part Developer
$ L$ E5 J% U* [, w2149948 PCB_LIBRARIAN SYMBOL_EDITOR New Symbol Editor and System Capture moved pins from 0.01 grid to 0.05 grid.
: w" P: _+ R1 m2206975 Pspice MODELEDITOR PSpice Model Import Wizard symbol preview readability improvement requested
- @0 P) @" Y3 C2211187 PSPICE MODELEDITOR Model Editor color scheme not readable
n( C8 I* q. m- [+ r w3 t) D2214415 PSPICE MODELEDITOR Symbol view in Model Import Wizard has a visibility problem
7 V# L' g' F/ |2199570 PSPICE PROBE Unable to 'select sections' after Monte Carlo runs with Temperature
. G7 {# y2 h7 U* V3 Y1 Q& D2 f2244140 PSPICE PROBE Not able to select multiple sections to plot in probe! c7 ]2 I8 G. ~& v
2249565 PSPICE PROBE Selecting multiple traces for PSpice A/D Monte Carlo run not working
0 u, ?8 ?* K; D* K2171626 PULSE CORE Pulse crashed with error related to third-party development kit platform issue1 f$ S# \0 L% V" f4 ^# k, @
2221523 PULSE UNIFIED_SEARC Cannot log in to third-party search providers but can log in to Cadence Online Support
, O: H8 ^+ r, r1 G% D; ]2019229 RF_PCB OTHER Layer conversion file data does not update GDSII layer mapping using Package Symbol Wizard! ^5 j$ q* L7 T( J7 T+ \. ~4 c4 q
820288 SIP_LAYOUT COLOR Layer Priority command does not seem to be functioning
6 g: ?3 \( ?1 z2 [* B* [* g820305 SIP_LAYOUT COLOR Layer Priority menus do not match the Color dialog in the package substrate tools
2 m) ]) K, z' w7 j- A5 w2256044 SIP_LAYOUT DATABASE Fix teardrop does not work for some situation: Deleting fixed fillets# F; y3 k/ Z8 u/ M
2254932 SIP_LAYOUT DEGASSING APD Plus generating assertion failures when running degassing mode with script
+ [* H; r' L2 c( ^; V2106314 SIP_LAYOUT INTERACTIVE Large design causing severe lag in Windows Server machine
( Z( h" |$ x; s0 I) [+ `; L4 L" M2096239 SIP_LAYOUT STREAM_IF Database fails to create stream out file
3 W- r4 Y9 G7 u& G2079071 SIP_LAYOUT SYMB_EDIT_APP Response very slow after Show IC Details on a very large co-design die8 x R" Q$ `0 R1 K7 s* M; [
2251630 SIP_LAYOUT WIREBOND 'Change Profile' does not change the diameter of the wire bond
' o! u- n3 |4 \2 O4 U2253633 SIP_LAYOUT WLP Advanced degassing passing illegal arguments to dba routine' O! ~# p- }9 q+ o1 o. K X
2259630 SIP_LAYOUT WLP Advanced WLP: Import PVS DRC results in error
8 j6 S+ F8 ^! v; z; r6 d$ S1968437 SYSTEM_CAPTURE ASSIGN_SIGNAL Net name pasted in lower-case though uppercase input is enabled1 H0 @9 G* ~2 @8 O" r
2131976 SYSTEM_CAPTURE AUTOMATION syscap exits when run with the -tclfile argument and an invalid Tcl file$ g2 m3 [; s7 F0 p% f' m* M4 ]
1983063 SYSTEM_CAPTURE BLKDIAGRAM_AU Auto Shapes are being shown as part of components
' c3 E( _8 A/ m2 T0 b1977673 SYSTEM_CAPTURE COMPONENT_BRO adding reference blocks through add component error when cell name matches design name+ I' k& y7 X1 D. C# d/ D" n& h
2247567 SYSTEM_CAPTURE COMPONENT_BRO Symbol property placeholder changes not updated on the canvas0 `: e# R8 F- k4 l
2027100 SYSTEM_CAPTURE COMPOSITE_FIL pstdedb.cdsz and netlist preview in System Capture is not being updated when individual netlist files are written
7 R; @) w( u3 Y" p5 s0 h1863460 SYSTEM_CAPTURE DARK_THEME thumbnail preview of pages is in light them but dragging the page the previes is dark
6 L9 w+ X p* R8 c2168622 SYSTEM_CAPTURE EDIT_SEARCHRE Reports from Find Results are dumped even when the operation is canceled
. Q) v! H" X' R) o, `9 ?2168625 SYSTEM_CAPTURE EDIT_SEARCHRE Sort icons for columns in 'Find Results' are incorrectly placed: appear to be in adjacent column1 a- V: @5 z s' x$ l
1895142 SYSTEM_CAPTURE EXPORT_PCB System Capture incorrectly reports unsaved changes when closing after running export physical
1 z. N& Q6 C, M9 E1931660 SYSTEM_CAPTURE EXPORT_PCB SDA is non-responsive while Allegro launches and opens a board when launched from SDA
' T9 \$ Z0 l) E# e) f2087387 SYSTEM_CAPTURE EXPORT_PCB System Capture: After Export PCB completes, busy cursor shown for a while Y& O6 Z0 j& {0 d( p, x0 S3 `
2202179 SYSTEM_CAPTURE FIND_REPLACE Replacing a net name with the same name by using Find and Replace results in a crash+ [# H% X: }6 G' S* x& K3 Z
1843885 SYSTEM_CAPTURE FORMAT_OBJECT Renaming a net causes it to lose custom color assignment$ D0 C4 J( k2 h' P8 C' k J0 @
1993208 SYSTEM_CAPTURE FORMAT_OBJECT Setting font prior to placing text does not work, pop-up does not work, and bucket results in scrolling page/ X- h& I& q4 O8 C8 v: P J/ r
2231399 SYSTEM_CAPTURE IMPORT_BLOCK 'importBlock' Tcl command not working when using a script. l- l [1 ]$ x, h+ v+ W$ k W
1907729 SYSTEM_CAPTURE IMPORT_DEHDL_ Import DE-HDL sheets - differential pair properties on nets are lost1 T% }! i X9 b
2025949 SYSTEM_CAPTURE IMPORT_DEHDL_ Title block and thick wires/lines of border in DE-HDL do not translate in System Capture
# z/ k6 e/ W% |, F% x0 \- Y3 E# r* K1942542 SYSTEM_CAPTURE IMPORT_PCB System Capture - TDO backannotation overwrites net names with stale data in lower-level blocks1 J7 P7 w: I% p7 i0 P) j& T
1982320 SYSTEM_CAPTURE IMPORT_PCB View files are not created in the schematic-to-board flow
) G3 n, j& C) a, U9 ~) R! r2117532 SYSTEM_CAPTURE MENUS_AND_TOO Ability to customize menus for a site+ x# k4 s6 S. L6 [
2213478 SYSTEM_CAPTURE MENUS_AND_TOO Help - About menu item appears twice$ U( i0 S; r! s, \$ Z+ t
1910941 SYSTEM_CAPTURE MISCELLANEOUS Parts that are not in any schematic page appear in netlist and BOM
/ g, p: q' m* v: y1 ?0 M1967614 SYSTEM_CAPTURE MISCELLANEOUS Dragging a circuit with net aliases does not move the net aliases with it6 J9 N3 {0 ?+ C% p o3 h1 s+ Q
2189846 SYSTEM_CAPTURE MISCELLANEOUS Inconsistent display of same font
" T ^6 l+ {9 G1 P+ {2178961 SYSTEM_CAPTURE NOTES Cannot add Japanese text in notes in release 17.4-2019 on Windows 10 p6 t* k9 ~" |1 I% @9 m( ~
1973437 SYSTEM_CAPTURE OPEN_CLOSE_PR Opening a design crashes System Capture2 h8 i3 m) h+ _4 u, i4 u
2079857 SYSTEM_CAPTURE OPEN_CLOSE_PR System Capture: Unable to select design to open if license selection box is canceled the first time/ P* j; v8 O. Q9 D
2065025 SYSTEM_CAPTURE PACKAGER Export to PCB Layout reports wrong path but exports correctly# W! c! r: e1 G. a+ w
2229611 SYSTEM_CAPTURE PACKAGER Path for the 'packaged' folder shown in the 'Export Physical' is incorrect( e- a& L0 F3 m# ^9 n5 I P$ ~
1993146 SYSTEM_CAPTURE PROJECT_EXPLO Cannot move page up by only one position
; e6 Y7 }* j: U" x% A4 \1892120 SYSTEM_CAPTURE PROPERTY_EDIT Some parts are missing reference designators and some have two properties - RefDes and REFDES
! w, D! I- Z. N1 X6 v2201060 SYSTEM_CAPTURE PROPERTY_EDIT Some of the icons in the Properties window do not have tooltips/ j" p$ h( h" D' Y: O4 x7 p! P# i
2246667 SYSTEM_CAPTURE SCRIPTING Running the 'replay.tcl' script gives an invalid command name error
: @( j- I7 ]5 X l( {/ K* n2010032 SYSTEM_CAPTURE SHORTCUTS Cannot enter Page-Up/Page-Down as shortcuts: ^* i$ Q& w: i6 y6 J8 g1 o6 ^
2017985 SYSTEM_CAPTURE TDO Allegro System Capture ability for multiple users to open a design+ F' G6 c' O# O/ s
2106743 SYSTEM_CAPTURE TDO Ability for multi-user access to the same schematic
$ H; R9 y! B' x6 S2209628 SYSTEM_CAPTURE UI Tooltips for Design Rule Checks are getting truncated! x% u) q/ Z7 _8 z
1990258 SYSTEM_CAPTURE VARIANT_MANAG Cannot paste copied preferred part to multiple parts with the same part number
5 n" ]& N+ s$ G4 |6 V' N2032005 SYSTEM_CAPTURE VARIANT_MANAG Custom variables not saved for variants8 L2 [( t4 m5 M2 ]9 q4 {$ t+ V, U6 r
2228299 SYSTEM_CAPTURE VARIANT_MANAG CAP parts should not show up in the Preferred Parts list when changing a RES
) ?! X+ O* }, P/ ^ {- d& \1627835 SYSTEM_CAPTURE WIRING Inconsistencies in wire movements1 ]4 e" t- K I$ B
1670888 SYSTEM_CAPTURE WIRING Rotation error when a component is connected to a power symbol
" N- W {$ p4 j# v1721863 SYSTEM_CAPTURE WIRING Net names move to random locations when components are moved around the canvas.$ l$ T" m# s3 e7 j
1960130 SYSTEM_CAPTURE WIRING Disconnected nets when using the mirror option. l/ j# X2 o/ ^2 u+ ?
1961274 SYSTEM_CAPTURE WIRING XNet removed during pin swapping
: c0 i7 x0 O' f2 |; k1968463 SYSTEM_CAPTURE WIRING System Capture should not allow illegal characters to be entered for net names
) ?% C8 N3 p6 _+ Y, U1973426 SYSTEM_CAPTURE WIRING Selecting multiple net names and trying to delete only deletes one net name.4 P8 Y2 y% h9 S' \' E) I
1978381 SYSTEM_CAPTURE WIRING 'oops' does not remove the first vertex placed/ Q G5 [9 s7 b. C, c/ F
1985029 SYSTEM_CAPTURE WIRING Net aliases are not dragged with circuit, they appear to move after the circuit is dropped8 F' Y, U) C6 c& t% V# r% g
2013647 SYSTEM_CAPTURE WIRING Replacing a vertically oriented RES with a horizontal CAP breaks the wire connections* m4 G; ]: H( r6 g$ e0 B
2014188 SYSTEM_CAPTURE WIRING Context menu not working in Variant mode1 H6 @+ [: ^; J
2041879 SYSTEM_CAPTURE WIRING XNets generated for nets with pull-up resistors: Z8 O0 F7 k m
2050533 SYSTEM_CAPTURE WIRING Need an option to increase junction dot size
$ Z m, Y$ y5 r3 q2061877 SYSTEM_CAPTURE WIRING Unable to add a power symbol with the Place - Special Symbol menu
2 K' }0 x4 Z) \% G( ~9 z2079409 SYSTEM_CAPTURE WIRING Increase the size of the wire connection dot in System Capture+ [( ]& s0 P; u/ R- w. s
2081884 SYSTEM_CAPTURE WIRING Symbols take a long time to move, and results in DRCs and broken connections
; {2 b" S$ Y2 P3 P. t3 p2085263 SYSTEM_CAPTURE WIRING System Capture: Focus lost from the Format tab if font name starting with typed letter is not present- V* ?. q3 u* ?* P/ p0 W5 k o5 T
2089569 SYSTEM_CAPTURE WIRING Ability to specify the solder dot radius size
, D X# B% h- m& p6 M2 f) U9 }$ [2 Q. W) q2 ]
QIR1详细特性说明：
Hotfix_SPB17.40.007_README-Release_Notes.pdf
(2.51 MB, 下载次数: 55)
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待我上传完后附上链接，这次QIR1比较大，4.59 GB
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发表于 2020-6-8 02:00
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发表于 2020-6-8 09:10
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