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本帖最后由 金志峰 于 2020-6-8 03:33 编辑 4 _! n, q; H$ Z6 u- g9 V1 V
. [8 B8 j+ }2 y; F$ u/ U; f7 P cadence orcad and allegro 17.4-2019 QIR1新特性 " O' v. u! I8 R, C+ S
·焕然一新的图标及UI
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QIR1中全新启动界面 （点击图片放大）
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# x2 p* m" s6 O4 C* m- b( i% ?QIR1中全新启动界面（点击图片放大）
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QIR1中capture官方Dark主题（点击图片放大）(QIR1中UI界面中所有图标也全部更换全新并统一了)% }8 Z9 ?' Y; z4 d, M
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5 j3 b7 @+ v% |4 aQIR1中capture官方Light主题（点击图片放大）
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# W2 _* A. D% {8 E4 g6 A& @QIR1中PCB Editor新增官方Dark主题（点击图片放大）
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9 }3 t5 y m" K$ `QIR1中PCB Editor官方Light主题（点击图片放大）& L( l1 o( s& J( Z5 D) `
(QIR1中UI界面中所有图标也全部更换全新并统一了)
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Fixed CCRs: SPB 17.4 HF007
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========================================================================================================================================================
. O* Q& j4 n6 A$ A! c- v/ UCCRID Product ProductLevel2 Title6 P) t* Z0 N+ W9 D6 o
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2247686 ADW CORE Allegro EDM: Unable to create a project using a newly created flow
9 V/ J1 ]; j; x _. u2137594 ADW DBADMIN EDM is not allowing changes to STEP models
$ a- [% C0 d6 C: x, b2135452 ADW DBEDITOR DBEditor poor peRFormance in high-latency networks- T0 W5 g: y( {8 r7 g
2113265 ADW LIBDISTRIBUTI Various database operations take a long time; rebooting server seems to fix the problem
. S5 w5 x/ [$ j$ F$ p2122941 ADW LIBDISTRIBUTI Lib_dist execution taking a long time to run; Capture CIS DBC file appears to be taking the most time
" S) f: z7 S4 f: T! F0 _3 Y2127319 ADW LIBDISTRIBUTI Library distribution fails at cisexport function with error (ORCIS-6250)
2 g7 t& ]2 x& ?( X5 i+ \) T1975317 ADW PART_BROWSER Space at the end of the line in CDS.LIB results in zero libraries being shown in System Capture library search
% ~+ }/ b4 g# }- ]' }6 k) Q8 q2078057 ADW PART_BROWSER Symbol Graphics preview is not available in Designer Servers3 V/ W k; N: O& m& @5 ~8 x% W% X5 o
2092863 ADW PART_BROWSER System Capture library search is not displaying the symbol and footprint preview
" l3 D) p4 z1 d* ~! d# f2086463 ADW PART_MANAGER System Capture cannot add components when accessing remote machine via Citrix
/ Z$ `0 P0 Y( k) }2092868 ADW PART_MANAGER Release 17.2-2016, HotFix 054: Empty cache.ptf causing injected properties to not flow from pstchip
( j' j: k/ O' @& R& u2092872 ADW PART_MANAGER System Capture stops responding when importing from DE-HDL3 Q g0 O C5 g2 y- K, r$ P( H+ o3 F
2113226 ADW PART_MANAGER System Capture stops responding while importing DE-HDL sheets7 F" @6 Z; c' X: ]/ ?
2212406 ADW PART_MANAGER Allegro System Capture: Part Manager is deleting properties from all instances upon Update4 o2 U- p! B* Y1 B* \' r: \8 A
2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name0 ?* U# _/ C, g$ D. j! o _) [. _8 g7 b
2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to Team Design2 h) C) g5 r+ H
2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object
) S0 E% L3 \$ y: `$ u) _# `2048086 ALLEGRO_EDITOR 3D_CANVAS Wire bonds are not linked to die pad when component is embedded body down
: D1 h' r5 A8 C6 t5 x5 r" E2051277 ALLEGRO_EDITOR 3D_CANVAS Vias are offset from board in Z direction in 3D Canvas
_5 |2 x, M( E: o9 {; \2054243 ALLEGRO_EDITOR 3D_CANVAS Plating is not shown on stacked vias in 3D canvas; H: n" o, _# F& _
2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation
1 R* ^- `6 Z/ |9 H; f2079732 ALLEGRO_EDITOR 3D_CANVAS Enhance 3D Canvas to merge the lines segment and overlapping lines and shapes
0 W* S7 Z& V3 a2 w2206045 ALLEGRO_EDITOR ARTWORK Artwork Control Form fails to create film if Film record has a period (.) in the title. f& h/ E8 Y" Q0 g/ Q
2209200 ALLEGRO_EDITOR ARTWORK PCB Editor stops responding on rebuilding apertures without rotation
* H7 X- t+ D5 E9 F+ x( u& ?7 ^2244407 ALLEGRO_EDITOR ARTWORK Automatic editing apertures with rotation takes time in the General Parameters tab of Artwork Control Form! W9 b7 v. S3 a
2267942 ALLEGRO_EDITOR ARTWORK Allegro PCB Editor stops responding when generating apertures in HotFix 006
8 G- @/ X5 q/ V8 T$ Q! L7 U$ ?567342 ALLEGRO_EDITOR COLOR Add option under View menu for 'load color view'
S8 w4 f7 x' }3 J' g1 s. w637828 ALLEGRO_EDITOR COLOR Line highlights in 'shape select' command7 M0 K a3 G1 W6 S" L4 c- Y
720274 ALLEGRO_EDITOR COLOR Add menu option for the 'colorview load' command9 F! h7 ?6 j' ]& ~( L/ w d3 k. W: x/ Q
1602652 ALLEGRO_EDITOR COLOR Color/Visibility behavior variation using "Enable Layer Select Mode"; I: t* `5 @- W
2072695 ALLEGRO_EDITOR COLOR Clines of colored nets not colored when 'display_nohighlight_priority' is set$ \' @+ H9 O1 {' j( s
2207580 ALLEGRO_EDITOR COLOR Component color is inconsistent when display_nocolor_dynamics is set.
5 @9 _4 e6 Q4 i' K# y2056497 ALLEGRO_EDITOR DATABASE Place manual is slow% `* W# ^8 G/ o& D
2250988 ALLEGRO_EDITOR DATABASE Inner Layer keep out as illegal subclasses: Shape object may not exist on layer ROUTE KEEPOUT/INNER_SIGNAL_LAYERS
7 Q: c: X5 O9 v& R6 v# A+ b2096958 ALLEGRO_EDITOR DFA Cannot launch Constraint Manager after assigning CSet and closing
3 e4 O( {7 _5 K2049681 ALLEGRO_EDITOR DFM DFF check for plating in via should not flag DRC for surface mount testpoint Via# i+ G9 J( n" R5 f/ Q& B$ `1 l1 ]. V
2155060 ALLEGRO_EDITOR DFM Inconsistent behavior in displaying DRCs for Via to Via spacing7 k/ v" J* P6 x6 w
2166431 ALLEGRO_EDITOR DFM DesignTrue annular ring thru pin pad to mask checks compared to smd pin to mask checks are inconsistent in behavior
* h2 h$ b# u! [$ h" x2221975 ALLEGRO_EDITOR DFM DFM missing mask check reporting mask is missing when pins have a mask geometry overlaying them.2 x* H. t+ A7 t6 c8 J9 K
2249498 ALLEGRO_EDITOR DRAFTING When a Symbol with a Dimension is placed on the board, an extra Dimension is added to the Symbol origin.0 j* D0 I' K' f+ d. F
2250631 ALLEGRO_EDITOR DRC_CONSTR Cannot import netlist into design due to illegal DRC element: no DBDoctor error
, \$ T! ^% { x1 u) H1794593 ALLEGRO_EDITOR EDIT_ETCH Unable to deselect return path vias selected when creating High-speed via structures% j% P* l: U. Z O& H# K
2099538 ALLEGRO_EDITOR EDIT_ETCH Gloss - Via Eliminate shifts traces to another layer
4 x1 n% v4 A. D0 Y3 W2204339 ALLEGRO_EDITOR EDIT_ETCH Differential pair line lost during slide operation
8 J# q& X2 ^ D2208938 ALLEGRO_EDITOR EDIT_ETCH Slide operation makes one of the differential pair cline invisible! x- q1 Y6 Q4 L6 H3 ?' r
2222047 ALLEGRO_EDITOR EDIT_ETCH One of the traces disappear when sliding a differential pair in single trace mode
1 _7 v: C4 s! V( f* Q& M2233991 ALLEGRO_EDITOR EDIT_ETCH One cline of a differential pair disappears temporarily upon sliding the Differential Pair in Single Trace Mode' ~/ G! j5 l0 {1 A& x" t6 ]) J: H, J
2240827 ALLEGRO_EDITOR EDIT_ETCH Cline of a Differential pair net disappears after sliding the other net of the Differential pair& p2 V5 t5 s2 K6 x- x* j) X
2245775 ALLEGRO_EDITOR EDIT_ETCH Differential pair slide in single trace mode removes other trace$ `) m6 ?. |7 i8 K% o& b- b
1813358 ALLEGRO_EDITOR GRAPHICS Allegro PCB Editor enables shape boundary when disabling etch layer in Visibility pane
- E4 G6 R# i8 ?, k* ^3 ]3 L3 N1911613 ALLEGRO_EDITOR GRAPHICS The subclass for boundary class stays on, even if Subclass for Etch Class is turned off from Visibility tab
/ l! f/ b' J- x( C1966343 ALLEGRO_EDITOR GRAPHICS Shape boundary remains enabled even after turning off the etch layer visibility; a) A5 v6 M0 @
2195276 ALLEGRO_EDITOR GRAPHICS Selecting File view is slow" U$ y& h2 C9 Y( ~
2031883 ALLEGRO_EDITOR INTERACTIV Sub-Drawing: Clipboard origin point is not set correctly
5 Q. p$ s* e8 a: p2 \7 Z0 M2050177 ALLEGRO_EDITOR INTERACTIV Letters need to remain aligned and uniform after performing Shape ANDNOT operation y* x4 Q5 u5 T( [) U
2069247 ALLEGRO_EDITOR INTERACTIV DFA bubble on wrong layer after mirroring the part
% T4 Y" a. F- |- Y' g5 i! J2103711 ALLEGRO_EDITOR INTERACTIV Placement edit mode popup 'Rotate' leaves ghost image in the background
9 i7 r# R& N7 q2136859 ALLEGRO_EDITOR INTERACTIV DFA Problem if we mirror component while placing4 Q6 q4 f* P! U3 u' w* f" ^+ R Q
2165027 ALLEGRO_EDITOR INTERACTIV Different behavior in OrCAD Capture when using crossprobe to select Power nets! \$ Z0 h0 u9 `+ _- [1 }4 N; j
2240235 ALLEGRO_EDITOR INTERACTIV The design file name changes automatically to board template name while creating new board (wizard).+ a, H$ ^- g+ {$ D
2244765 ALLEGRO_EDITOR INTERACTIV License 4150+226 does not have AiDT/AiPT in release 17.2-2016
5 q3 U( n% d3 Q3 g0 D8 z2259800 ALLEGRO_EDITOR INTERACTIV DFA DRC circle not shown on the layer of placement in Placement App Mode7 J- |: N j/ U( x- t* |
2120420 ALLEGRO_EDITOR INTERFACES Drill figures missing in the exported PDF if drill legend deleted
0 e B) f5 Y% Z9 G1 d2 T( \2136454 ALLEGRO_EDITOR INTERFACES Export - PDF output is not correct
( q$ t* i+ Z# L/ ^. F2116748 ALLEGRO_EDITOR IN_DESIGN_ANA Impedance vision data not available for cline segments for some nets/ p/ J! p3 i5 X5 O1 r+ K
2138977 ALLEGRO_EDITOR IN_DESIGN_ANA Impedance check results are incorrect and Crosstalk analysis stops running after updating to 17.2-2016, HotFix 0572 Y! h8 m) T" D' ^
2247167 ALLEGRO_EDITOR IN_DESIGN_ANA IDA Impedance Analysis: Add an option to export CSV automatically
0 Y, F, h8 U. ^/ ~6 M. G2222638 ALLEGRO_EDITOR IPC Documentation Editor crashes with error: Failed to complete the job because of unspecified error
& t- X1 {" \2 G9 e6 k2106425 ALLEGRO_EDITOR NC Disable undersize regular pad and oversize soldermask pad for start layers in Backdrill Setup and Analysis
1 f3 a$ h. E9 V/ ]% h9 j% w7 s" | R4 `2091932 ALLEGRO_EDITOR OTHER Unsupported Prototypes command missing for the OrCAD licenses
9 a7 q) `# S0 [$ p. p2221345 ALLEGRO_EDITOR OTHER Speed up Allegro PCB Editor startup by removing check for defunct PCB/Package co-design capability (NG_450); ~- t y5 ?5 s1 ?0 d1 f; i9 K
2257934 ALLEGRO_EDITOR PLACEMENT Error (SPMHGE-626) on place component: Symbol not valid on any layer
) k) K0 ]& D" C1 J/ `! F+ W0 u! R- g) |1001000 ALLEGRO_EDITOR PLOTTING File - Plot in PCB Editor does not plot more than one copy7 T3 l0 K+ {6 o* K3 ?/ p
2234538 ALLEGRO_EDITOR REPORTS Allow Unused Blind/Buried Via report to run as Batch Process through the reports batch command
" n* o) e# _# P9 M5 l1 @: P2222738 ALLEGRO_EDITOR SCHEM_FTB Netrev not completing, showing error for electrical constraints data (pstcmdb.dat) import# K$ R5 l; F8 H J4 l0 t0 _* I
2255426 ALLEGRO_EDITOR SCHEM_FTB Netrev is running for hours without closing
& M, r/ B" |. C1702190 ALLEGRO_EDITOR SCRIPTS Allegro PCB Editor script file: Some sub-classes not created and error for form field label" q' `: I( T* G) m' e
1791099 ALLEGRO_EDITOR SCRIPTS Allegro PCB Editor does not terminate when the script is run with '-nographic'" V6 l- O; B g7 `. R
1791267 ALLEGRO_EDITOR SCRIPTS Allegro PCB Editor script does not run with '-nograph' in release 17.2-20164 R9 C. D5 S9 S* Q# `) D
1892520 ALLEGRO_EDITOR SCRIPTS Allegro PCB Editor stops responding for script when run with '-nographic'
% ]6 u; z% ~' W5 s- D; ]0 B1 `1962010 ALLEGRO_EDITOR SCRIPTS Allegro PCB Editor stops responding for script when run with -nongraph option
7 ?# I0 s* x+ V! ^/ `/ R; S- a2056857 ALLEGRO_EDITOR SHAPE Shape boundary error by shape parameter8 u" G, V$ g& c! n$ n2 x
2081946 ALLEGRO_EDITOR SHAPE Shape Update takes twice the time in release 17.2-2016, HotFix 053 as compared to HotFix 0473 [/ o3 v! n2 K% S6 i/ a! _
2104559 ALLEGRO_EDITOR SHAPE PCB Editor crashes while performing shape operation 'andnot'
; T* n% _* u; y. k* ^2108207 ALLEGRO_EDITOR SHAPE No Void Overlap option is not working in Auto Metal Balancing (AMB)
# ^2 z8 T3 ?. ]4 n3 `2240996 ALLEGRO_EDITOR SHAPE Detecting Shape Island: Ignored for copied or moved shape5 ?& j5 t& j) J, Y! h$ Y
2258758 ALLEGRO_EDITOR SHAPE Allegro PCB Editor crashes when routing two signals together/ ^* L6 S$ w' q& L
717389 ALLEGRO_EDITOR skill Ability to set and return the application mode using SKILL
6 u4 e H0 V# ]) y853160 ALLEGRO_EDITOR SKILL Need ability to get and set application modes using SKILL
9 e: w" Z, w, o% W- J981446 ALLEGRO_EDITOR SKILL Request the ability to get and set application modes using SKILL
& A. g l: z! D: g6 Z- r; b1235409 ALLEGRO_EDITOR SKILL SKILL option to get application mode2 C3 K" z! Y E# r& _3 c7 R8 _) o
1316962 ALLEGRO_EDITOR SKILL SKILL option to switch between application modes
( m6 h, p/ x. V& Z) D1553621 ALLEGRO_EDITOR SKILL Ability to change application modes using SKILL function- c' Q2 Z$ R2 @
1885442 ALLEGRO_EDITOR SKILL Ability to change application modes using SKILL function.% ~: _3 b: Q' N& }
2080351 ALLEGRO_EDITOR SKILL SKILL to determine current application mode
. V o. z9 E# X0 F3 d' N. Y2195645 ALLEGRO_EDITOR THIEVING Thieving pad cannot be added on some areas in the board in latest hotfix but could be added earlier6 E8 Y6 F0 z4 `& O3 I
1721594 ALLEGRO_EDITOR UI_FORMS STEP name Filter for STEP Package mapping form should be case insensitive
; h8 x6 T/ H* t. P3 `& k6 N2090604 ALLEGRO_EDITOR UI_FORMS Undo/Redo UI grayed out when invoking Color192# H0 R9 i& v4 `* P' g& v* X
2203278 ALLEGRO_EDITOR UI_FORMS 'Width' keyword in Place Rectangle field is grayed out when Place Rectangle is selected
) Q' ?% N0 a& {/ E/ L- Z# @2209172 ALLEGRO_EDITOR UI_FORMS Labels truncated by drop-down lists in Options ('Manufacture' - 'Drafting' - 'Relative Copy')
8 @4 z( ~. V- o; l) O' ^* j2239426 ALLEGRO_EDITOR UI_FORMS Cannot start text size with decimal in 'Design Parameter Editor' - 'Text' for English (Denmark) regional settings
: _6 E9 l. ~' u' [2245035 ALLEGRO_EDITOR UI_FORMS The right edge of the default Define Grid form looks cut off in 17.4.
/ w/ Q: r/ ?, {! b) Q2245955 ALLEGRO_EDITOR UI_FORMS Resizing of 'Reject Item Selection' window not possible in release 17.4-2019, HotFix 0041 E; [- G$ `2 H
2249202 ALLEGRO_EDITOR UI_FORMS Extra click required to activate Pass field in Autorouter form
, e0 D, K0 u. ?. F7 G0 }2259605 ALLEGRO_EDITOR UI_FORMS Add ability to resize Reject pop-up$ ?) {7 Y: _* r- o. L' p
2090517 ALLEGRO_EDITOR UI_GENERAL Shape visibility box is not being enabled with the Enable layer select mode option in the Visibility Pane
2 S" P4 b; E; d, I2 C. ~! a2092436 ALLEGRO_EDITOR UI_GENERAL RefDes length of input string for Modify Design padstack is limited to 20 characters) t$ r9 H% Y5 m2 U- v( B2 a/ q
2134781 ALLEGRO_EDITOR UI_GENERAL The Pin Class is missing in Options tab when creating or opening a Mechanical Symbol; U( m4 {& @' e, w) M1 ?. F
2168026 ALLEGRO_EDITOR UI_GENERAL Edit Properties UI slow to launch for boards with many drawing properties
! t t9 W/ [; [: o5 h; E2191267 ALLEGRO_EDITOR UI_GENERAL Changing Visibility of any object type disables links in Layer Select Mode in the Visibility pane
* O' N1 ~6 F$ [4 r) r' A6 j/ C( q2208018 ALLEGRO_EDITOR UI_GENERAL Text on BGA pins not visible in release 17.4-2019 if not zoomed to maximum; W8 M# h2 W }. B3 B$ X9 q! L
2225753 ALLEGRO_EDITOR UI_GENERAL dark theme does not respect TRBICON size for 4K monitors: g! [' C+ @+ ?5 ]9 ?7 ]1 b
2256841 ALLEGRO_EDITOR UI_GENERAL Enlarge the Shape Copy to Layers form as the window is quite small and not resizable
4 r' ^; p+ e( U2258019 ALLEGRO_EDITOR UI_GENERAL Canvas turns white after closing STEP Package Mapping window
9 r8 D8 A6 T2 r* a4 ] U& U2258167 ALLEGRO_EDITOR UI_GENERAL Enhance 'Shape copy to layers' window in release 17.4-2019 to expand or resize
6 K) f( v& u7 L2262305 ALLEGRO_EDITOR UI_GENERAL Assign Differential Pair form list box size too small to add signals
4 V0 C2 U. Y' _( J: y i2086574 APD OTHER APD is showing duplicate layer text on the vias
3 f" F# S+ A& p$ t2 ~& G1723825 APD SCRIPTS Allegro Package Designer in release 17.2 is not writing out to either jrl files or script files in real time.
) ~" G1 q" g, B6 J4 V& G2186363 APD UI_GENERAL Text on the Pin is not visible until zoomed in to certain extent9 H! c7 z- m, _" V2 `. `" v
2253484 APD WIREBOND APD stops responding when running 'wirebond soldermask create' with 'Measure from soldermask pad'
3 l( h. Q. Y+ R) |5 J$ b+ n# ?2241725 CAPTURE DRC Waive DRC option not working from batch DRC window k. L7 y, u4 ]9 R
2243645 CAPTURE DRC Online DRC bug in release 17.4-2019, hotfix 004 - offpage connector does not have wire
# I' j* K) r7 C9 v* O W! `2250867 CAPTURE DRC Hanging wire custom DRC not working when selected standalone
9 o M- _! z9 _( f1 K2252912 CAPTURE DRC Unable to create new DRC file using Browse button in DRC window
7 J' M% ~" f0 V" v& `1 x3 r. s3 ~' C2047391 CAPTURE PART_EDITOR Pin type cannot be changed in release 17.2-2016, hotfix 051
0 y6 |+ A E7 U; g. p5 j$ n$ }. [( n2183187 CAPTURE SCHEMATIC_EDI OrCAD Capture: Ctrl + N seems to call a legacy dialog that allows projects to be created with no name
- J/ Q9 m% W5 S( ]/ u2190602 CAPTURE SCHEMATIC_EDI Cascading options of Window menu not working in OrCAD Capture in release 17.4-2019& s4 R) L% k( s9 N- e4 C) C
2194374 CAPTURE UX Design Sync issues: Session log does not report information about errors
# L( ]$ l' N/ j- u; ?2183037 CIS LINK_DATABASE CTRL-L shortcut for Link DB-Parts for Query in CIS-Explorer not working
# v' n# ]6 L7 _9 q( c9 |; p) Z2201323 CIS PLACE_DATABAS Capture CIS displays empty dialog on placing part from database in release 17.4-2019, F2 P3 S1 X2 T, l* s |! J' ^5 U
2216963 CIS PLACE_DATABAS Light Theme: Warning text not visible in Capture CIS dialog
+ y2 h, G$ o1 O- e# P' B/ E2246354 CIS PLACE_DATABAS Warning (ORCIS-6159) pop-up window is blank.
; w7 [0 w* _9 P7 f. j2230651 concept_HDL CHECKPLUS Discrepancy in the 'checkplus' marker files- u! R' {; M* u( u( V. z
2237145 CONCEPT_HDL CONSTRAINT_MG T-Points match groups get deleted after saving a design
1 P( @: V8 s: U$ B. d' X2246452 CONCEPT_HDL CORE Page information gets removed from 'master.tag' of the top-level design when subdesigns are read-only Z3 m4 c; w$ |5 L) u8 w6 B" b, f
2057490 CONSTRAINT_MGR CONCEPT_HDL Constraint Manager Worksheet flips after running hier_write when CM is open) h, C2 A& E; U$ z
2236329 CONSTRAINT_MGR CONCEPT_HDL Pin Pairs not added to Match Group
1 E1 b0 L! P+ x( S, P2214367 CONSTRAINT_MGR INTERACTIV CSet assignment matrix sorting in Net Class-class random in Capture to Constraint Manager flow$ j' G0 n! x9 v" F6 m
2243574 CONSTRAINT_MGR OTHER CM SKILL cmxlPutAttribute() cannot set constraint value- q3 I) a2 Z8 o
2259598 CONSTRAINT_MGR OTHER Importing netlist: Error for electrical constraint data (pstcmdb.dat) import6 I! [7 X/ T) F2 X0 ]' ?
2207862 CONSTRAINT_MGR SYSCAP Save icon and 'File' - 'Save' menu in Constraint Manager is inactive
( B1 W- u8 [1 C: c' K2200316 CONSTRAINT_MGR UI_FORMS Expanding 'Analysis Mode' form resets column width
2 z* A0 l1 t' j* e9 v* E* |8 _& t2097479 PCB_LIBRARIAN CORE Symbol import in Part Developer does not show the correct pin shape.' \- }% R4 W0 d
2145385 PCB_LIBRARIAN CORE Error-SPLBPD-972 reports missing parentheses in the ALT_SYMBOLS property of a part$ _; m$ A, Q7 t8 `. _
2202622 PCB_LIBRARIAN CORE When adding a new pin to a symbol in Symbol Editor, the space between pins changes' j! u. ]! f# @0 m
1955570 PCB_LIBRARIAN FLOW Using the PACK_SHORT property with more than 256 characters does not work or report an error on packaging
! ]* B. I- y' T, v. @2072190 PCB_LIBRARIAN FLOW Allow PACK_SHORT property value longer than 255 characters
7 i) N4 a) [$ C' ~3 c+ f1720395 PCB_LIBRARIAN IMPORT_OTHER Converting OrCAD Capture OLB to Design Entry HDL library adds braces to pin number
4 ^4 c) R6 r; M# j N2141340 PCB_LIBRARIAN SETUP SPLBPD-216 Error logged in PDV even when MAX_SIZE Sheet is defined% ~& h. r1 Z; _ t2 E. V. [
2214973 PCB_LIBRARIAN SETUP Unable to apply symbol property templates when PDV lock directives are set1 ]& q0 J+ V/ P
2257527 PCB_LIBRARIAN SETUP Locking PDV directives prevents applying symbol property templates
6 r" |4 S2 t3 Q& I& w* i8 ^2033898 PCB_LIBRARIAN SYMBOL_EDITOR Running Symbol Editor with no arguments results in a background process, not an error.- l! ^* w/ I" a3 H7 K) m, t
2093849 PCB_LIBRARIAN SYMBOL_EDITOR Symbols and font sizes appear different when placed in designs. t( A6 x. y3 }# J6 p: C
2200399 PCB_LIBRARIAN SYMBOL_EDITOR Multiple issues observed when editing parts in the New Symbol Editor
9 U' K. D) K) c, H4 u2218940 PCB_LIBRARIAN SYMBOL_EDITOR Duplicate pins cannot be removed
" p, _- n0 S. X! F& |2230542 PCB_LIBRARIAN SYMBOL_EDITOR Bus pin location changes after expanding or collapsing pins in Symbol Editor
9 g% C" e; A' R7 {2239303 PCB_LIBRARIAN SYMBOL_EDITOR Expanding and collapsing a bus is changing the msb and lsb for the pin name+ `- J; I& c2 a! M4 l
2243431 PCB_LIBRARIAN SYMBOL_EDITOR Group of pins that are not adjacent cannot be moved together( l2 V! s; a4 n1 W
2029056 PCB_LIBRARIAN SYMBOL_EDITOR Unable to change Grid Settings in Part Developer4 v8 T/ y) |( @+ n
2149948 PCB_LIBRARIAN SYMBOL_EDITOR New Symbol Editor and System Capture moved pins from 0.01 grid to 0.05 grid." R* |8 q. Z5 c7 V+ q [
2206975 Pspice MODELEDITOR PSpice Model Import Wizard symbol preview readability improvement requested
2 P( C3 ^" E4 C2211187 PSPICE MODELEDITOR Model Editor color scheme not readable
, q' p+ Z! w/ b) Y8 `2214415 PSPICE MODELEDITOR Symbol view in Model Import Wizard has a visibility problem4 U6 ^$ R7 `5 [# x$ A
2199570 PSPICE PROBE Unable to 'select sections' after Monte Carlo runs with Temperature
+ Z! z; S2 e. N" |2244140 PSPICE PROBE Not able to select multiple sections to plot in probe) L1 N5 N7 s" _9 q* a
2249565 PSPICE PROBE Selecting multiple traces for PSpice A/D Monte Carlo run not working' Z, W3 t* {( X; v; R
2171626 PULSE CORE Pulse crashed with error related to third-party development kit platform issue
2 y/ H! j# N2 x1 \2221523 PULSE UNIFIED_SEARC Cannot log in to third-party search providers but can log in to Cadence Online Support% @8 j2 g1 P! G6 h1 m
2019229 RF_PCB OTHER Layer conversion file data does not update GDSII layer mapping using Package Symbol Wizard
8 @" _0 p q3 a# w: C8 f, Z820288 SIP_LAYOUT COLOR Layer Priority command does not seem to be functioning
1 g7 p E" e7 ?2 c1 h. A820305 SIP_LAYOUT COLOR Layer Priority menus do not match the Color dialog in the package substrate tools
% ^% q& B: G- x* F& C2256044 SIP_LAYOUT DATABASE Fix teardrop does not work for some situation: Deleting fixed fillets
( T2 p! ~. L& J: L3 M. z2254932 SIP_LAYOUT DEGASSING APD Plus generating assertion failures when running degassing mode with script
) N6 Y, `# [0 M* D2106314 SIP_LAYOUT INTERACTIVE Large design causing severe lag in Windows Server machine
2 ]) X$ u8 A0 [5 [% r3 g7 ]2 s# |; t$ f2096239 SIP_LAYOUT STREAM_IF Database fails to create stream out file
5 d$ ^" g. P2 D; F) N3 ^2079071 SIP_LAYOUT SYMB_EDIT_APP Response very slow after Show IC Details on a very large co-design die
( P" r, a) x, B& H9 }. A0 m2 C2251630 SIP_LAYOUT WIREBOND 'Change Profile' does not change the diameter of the wire bond9 X4 c& v/ G9 ~# k
2253633 SIP_LAYOUT WLP Advanced degassing passing illegal arguments to dba routine& o$ }, _6 `+ C% C5 ?) s
2259630 SIP_LAYOUT WLP Advanced WLP: Import PVS DRC results in error
, _/ f: C9 p( p/ L9 H1 d7 j- \2 d1968437 SYSTEM_CAPTURE ASSIGN_SIGNAL Net name pasted in lower-case though uppercase input is enabled
9 ?+ G" G7 Y' c" V/ ]2131976 SYSTEM_CAPTURE AUTOMATION syscap exits when run with the -tclfile argument and an invalid Tcl file
' ~3 E+ d7 S& T4 Q; g1983063 SYSTEM_CAPTURE BLKDIAGRAM_AU Auto Shapes are being shown as part of components
8 x9 {; [6 D# s0 K1977673 SYSTEM_CAPTURE COMPONENT_BRO adding reference blocks through add component error when cell name matches design name
4 P0 ^4 E$ g+ t. @2247567 SYSTEM_CAPTURE COMPONENT_BRO Symbol property placeholder changes not updated on the canvas
& O! r1 w4 J* K0 j2 w3 h- |2027100 SYSTEM_CAPTURE COMPOSITE_FIL pstdedb.cdsz and netlist preview in System Capture is not being updated when individual netlist files are written8 _3 i7 P8 _5 {$ e' A
1863460 SYSTEM_CAPTURE DARK_THEME thumbnail preview of pages is in light them but dragging the page the previes is dark$ F9 @+ [/ s8 `) X% P1 o2 S
2168622 SYSTEM_CAPTURE EDIT_SEARCHRE Reports from Find Results are dumped even when the operation is canceled
( k; p& x+ K& u( O2 p2168625 SYSTEM_CAPTURE EDIT_SEARCHRE Sort icons for columns in 'Find Results' are incorrectly placed: appear to be in adjacent column
) `. p: B7 @9 s% [. H1895142 SYSTEM_CAPTURE EXPORT_PCB System Capture incorrectly reports unsaved changes when closing after running export physical: k |) a" d8 Y3 F5 A
1931660 SYSTEM_CAPTURE EXPORT_PCB SDA is non-responsive while Allegro launches and opens a board when launched from SDA9 Y" y' |1 v- S$ O4 {4 `
2087387 SYSTEM_CAPTURE EXPORT_PCB System Capture: After Export PCB completes, busy cursor shown for a while
" [+ f2 u0 E5 m* \6 _2 e' S, ^2202179 SYSTEM_CAPTURE FIND_REPLACE Replacing a net name with the same name by using Find and Replace results in a crash
) r/ {/ t3 I- Z2 w* p* ?3 _1843885 SYSTEM_CAPTURE FORMAT_OBJECT Renaming a net causes it to lose custom color assignment
3 ^- L; k" {( w; N) o, n( ]0 }6 t1993208 SYSTEM_CAPTURE FORMAT_OBJECT Setting font prior to placing text does not work, pop-up does not work, and bucket results in scrolling page
% h, P `; `) C4 P0 F+ R: j2231399 SYSTEM_CAPTURE IMPORT_BLOCK 'importBlock' Tcl command not working when using a script. L7 f+ K( z5 Y6 B Q
1907729 SYSTEM_CAPTURE IMPORT_DEHDL_ Import DE-HDL sheets - differential pair properties on nets are lost
# C& s3 I6 j9 B* x s6 y) C- A2025949 SYSTEM_CAPTURE IMPORT_DEHDL_ Title block and thick wires/lines of border in DE-HDL do not translate in System Capture V- v' }0 T6 g) l& d& G
1942542 SYSTEM_CAPTURE IMPORT_PCB System Capture - TDO backannotation overwrites net names with stale data in lower-level blocks
3 H" ~5 A( D) N( `& B+ Q) c9 V1982320 SYSTEM_CAPTURE IMPORT_PCB View files are not created in the schematic-to-board flow& [& I2 E) U+ `3 B
2117532 SYSTEM_CAPTURE MENUS_AND_TOO Ability to customize menus for a site
: ]9 I7 {. O( R, q( I7 W! A2213478 SYSTEM_CAPTURE MENUS_AND_TOO Help - About menu item appears twice
H3 `0 k5 W: O) c. U2 U8 L5 D5 A E1910941 SYSTEM_CAPTURE MISCELLANEOUS Parts that are not in any schematic page appear in netlist and BOM0 v' K* N- M+ q
1967614 SYSTEM_CAPTURE MISCELLANEOUS Dragging a circuit with net aliases does not move the net aliases with it
0 W$ u; `* Q+ a6 @2189846 SYSTEM_CAPTURE MISCELLANEOUS Inconsistent display of same font
% b# b# \1 O" f$ [2178961 SYSTEM_CAPTURE NOTES Cannot add Japanese text in notes in release 17.4-2019 on Windows 10: k* W1 Z4 T1 {5 Y2 i# L
1973437 SYSTEM_CAPTURE OPEN_CLOSE_PR Opening a design crashes System Capture
% i: r* R! U: y j( ]5 z7 O( p2079857 SYSTEM_CAPTURE OPEN_CLOSE_PR System Capture: Unable to select design to open if license selection box is canceled the first time
2 b6 {* h- J5 T0 h% U2065025 SYSTEM_CAPTURE PACKAGER Export to PCB Layout reports wrong path but exports correctly3 e! y1 a2 }, ~$ r- ]
2229611 SYSTEM_CAPTURE PACKAGER Path for the 'packaged' folder shown in the 'Export Physical' is incorrect
6 M6 ?% y% j, d, f' V0 p1993146 SYSTEM_CAPTURE PROJECT_EXPLO Cannot move page up by only one position \; r% f" T/ s6 V% _% @( b0 I3 i8 R
1892120 SYSTEM_CAPTURE PROPERTY_EDIT Some parts are missing reference designators and some have two properties - RefDes and REFDES% r8 g/ v3 I' j) z5 I
2201060 SYSTEM_CAPTURE PROPERTY_EDIT Some of the icons in the Properties window do not have tooltips
) M1 j: y' B$ o; B4 n2246667 SYSTEM_CAPTURE SCRIPTING Running the 'replay.tcl' script gives an invalid command name error2 O9 O" S+ T2 D2 ~
2010032 SYSTEM_CAPTURE SHORTCUTS Cannot enter Page-Up/Page-Down as shortcuts5 X- \! m: t4 s2 v: i
2017985 SYSTEM_CAPTURE TDO Allegro System Capture ability for multiple users to open a design3 [! d0 K5 C/ m" f' n
2106743 SYSTEM_CAPTURE TDO Ability for multi-user access to the same schematic
1 |1 y. d7 Y* }6 p; W7 s4 r3 P2209628 SYSTEM_CAPTURE UI Tooltips for Design Rule Checks are getting truncated
+ O$ j/ q4 A1 O" o3 R1 v1990258 SYSTEM_CAPTURE VARIANT_MANAG Cannot paste copied preferred part to multiple parts with the same part number3 c' O* n. y% ]. t
2032005 SYSTEM_CAPTURE VARIANT_MANAG Custom variables not saved for variants
. w7 X0 s3 m3 A0 V3 m" s% C2228299 SYSTEM_CAPTURE VARIANT_MANAG CAP parts should not show up in the Preferred Parts list when changing a RES+ O: U$ R d4 [4 x/ f4 K% ]$ G
1627835 SYSTEM_CAPTURE WIRING Inconsistencies in wire movements, r, y& D7 c% P) P) x5 h7 N8 R: R
1670888 SYSTEM_CAPTURE WIRING Rotation error when a component is connected to a power symbol
5 B8 `! P6 T0 u- ?& O! x4 h$ |/ T; j1721863 SYSTEM_CAPTURE WIRING Net names move to random locations when components are moved around the canvas.
. \* t# {# \' r/ X1960130 SYSTEM_CAPTURE WIRING Disconnected nets when using the mirror option9 Q0 I; L8 S' L* t$ E1 D$ a
1961274 SYSTEM_CAPTURE WIRING XNet removed during pin swapping3 m+ |+ s9 f: y1 i t9 g0 }. d
1968463 SYSTEM_CAPTURE WIRING System Capture should not allow illegal characters to be entered for net names
* G& \ ~2 m1 u7 B, K1973426 SYSTEM_CAPTURE WIRING Selecting multiple net names and trying to delete only deletes one net name.8 O# L' s8 ^; N2 B
1978381 SYSTEM_CAPTURE WIRING 'oops' does not remove the first vertex placed
4 e, h6 ?7 ]) t5 r1985029 SYSTEM_CAPTURE WIRING Net aliases are not dragged with circuit, they appear to move after the circuit is dropped4 V' I {) }$ a( I
2013647 SYSTEM_CAPTURE WIRING Replacing a vertically oriented RES with a horizontal CAP breaks the wire connections( o3 S' h- N8 \6 B" `3 M" ]
2014188 SYSTEM_CAPTURE WIRING Context menu not working in Variant mode
! {, C w" M4 T2041879 SYSTEM_CAPTURE WIRING XNets generated for nets with pull-up resistors
; M( I, ~8 n7 D6 a% m1 i9 D2050533 SYSTEM_CAPTURE WIRING Need an option to increase junction dot size
' o6 X! @' G. _! P- x5 x2061877 SYSTEM_CAPTURE WIRING Unable to add a power symbol with the Place - Special Symbol menu, K6 K/ q0 v+ U
2079409 SYSTEM_CAPTURE WIRING Increase the size of the wire connection dot in System Capture
9 y% ~! D! k8 ]2 ^5 {/ j2081884 SYSTEM_CAPTURE WIRING Symbols take a long time to move, and results in DRCs and broken connections! p ~$ w t; Q4 H; C$ y' [. [
2085263 SYSTEM_CAPTURE WIRING System Capture: Focus lost from the Format tab if font name starting with typed letter is not present
! [) n1 j, c) ~2089569 SYSTEM_CAPTURE WIRING Ability to specify the solder dot radius size
! `, z3 M* d( X8 k' I! U" e8 O: i, X* m4 [% ]# j% ~
QIR1详细特性说明：
Hotfix_SPB17.40.007_README-Release_Notes.pdf
(2.51 MB, 下载次数: 55)
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待我上传完后附上链接，这次QIR1比较大，4.59 GB
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发表于 2020-6-8 02:00
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