|
|
EDA365欢迎您登录！
您需要 登录 才可以下载或查看，没有帐号？注册
x
本帖最后由 金志峰 于 2020-6-8 03:33 编辑 / o- }1 X9 r! N! o. S, _4 I
( m6 y2 ?$ D$ {" G
cadence orcad and allegro 17.4-2019 QIR1新特性
, \# Y9 i7 x. p+ V& f·焕然一新的图标及UI
) C: ]) k; T9 p: m$ d: Y6 ?9 M7 a' O5 _2 S) V* I7 H
QIR1中全新启动界面 （点击图片放大）) i1 a# M2 t4 C
: K8 b7 |/ p' H0 z) M" } R/ h
: f. d: Y8 f6 a! e$ w EQIR1中全新启动界面（点击图片放大）
/ J+ k7 J0 F. d) K1 b
5 k. {. |/ `' p/ T9 t6 g
9 c9 U+ k, B- [: S5 ]! G , ~! M1 d/ U. R- }% L N' d( E; I
QIR1中capture官方Dark主题（点击图片放大）(QIR1中UI界面中所有图标也全部更换全新并统一了)
; |* P- e* S' ~0 X# n
' z3 L; }8 I, W! ]7 l& t- t* {
+ y$ \ L" b! }QIR1中capture官方Light主题（点击图片放大）
* h {$ e7 K/ m1 l' n C8 p" }(QIR1中UI界面中所有图标也全部更换全新并统一了)
2 s+ l% G- S* D% r
6 a" k- Y6 E7 ~, H4 I. b5 I% S1 k3 H1 V/ L/ [
QIR1中PCB Editor新增官方Dark主题（点击图片放大）- H3 X- z0 Z0 p3 B ^
(QIR1中UI界面中所有图标也全部更换全新并统一了)6 V3 P9 N) j5 {$ u7 V% a: A, |
: t4 J- t# s5 p5 z5 z, ]) ~' ~' } t% C# w% K- X+ E+ |/ f. f
QIR1中PCB Editor官方Light主题（点击图片放大）
/ I! w" R S4 O, c: M( f0 y, K(QIR1中UI界面中所有图标也全部更换全新并统一了)2 @$ M* }0 Q9 @" O! D# o: ^
; |3 y( P- d. m! E0 |& ^3 z5 ^/ v) h6 v9 R
2 D7 y; Y% ?! g/ x: R0 c- a/ p
" M3 p1 Z& f: g9 E, C6 _: A
7 e! R- j: Q3 Y9 c7 i: |Fixed CCRs: SPB 17.4 HF0070 s5 u& M0 r( Z8 i
05-21-2020 B P" H( z& H0 l) C, b
========================================================================================================================================================
% @5 f, d2 G+ b' L2 b1 G- w" ~CCRID Product ProductLevel2 Title. i4 ?5 w7 w: |$ n: j
========================================================================================================================================================1 W" X C3 e# L; S
2247686 ADW CORE Allegro EDM: Unable to create a project using a newly created flow
: ?) L: x" E2 ]1 _$ D; B: o. B2137594 ADW DBADMIN EDM is not allowing changes to STEP models
8 M6 E) {$ k$ y+ t! O2135452 ADW DBEDITOR DBEditor poor peRFormance in high-latency networks
# i& Z/ d, W4 q2113265 ADW LIBDISTRIBUTI Various database operations take a long time; rebooting server seems to fix the problem; W, e6 Y( H/ y5 ^& W
2122941 ADW LIBDISTRIBUTI Lib_dist execution taking a long time to run; Capture CIS DBC file appears to be taking the most time
9 z5 k; v8 p7 _( F1 x2127319 ADW LIBDISTRIBUTI Library distribution fails at cisexport function with error (ORCIS-6250)1 H: S0 C+ \9 d; W2 G
1975317 ADW PART_BROWSER Space at the end of the line in CDS.LIB results in zero libraries being shown in System Capture library search
: y: i& r( C3 S, u2078057 ADW PART_BROWSER Symbol Graphics preview is not available in Designer Servers
* I$ O$ G. }# q7 Z; H* l2092863 ADW PART_BROWSER System Capture library search is not displaying the symbol and footprint preview
" C* h7 X" @: n/ l+ e+ p2086463 ADW PART_MANAGER System Capture cannot add components when accessing remote machine via Citrix9 y' j7 d& S# ?; h9 ?1 i: |
2092868 ADW PART_MANAGER Release 17.2-2016, HotFix 054: Empty cache.ptf causing injected properties to not flow from pstchip
1 ^( Q- E5 Q- m2 j! l, ]9 Q5 O2092872 ADW PART_MANAGER System Capture stops responding when importing from DE-HDL
3 H9 | i- \1 D* p) [1 o2113226 ADW PART_MANAGER System Capture stops responding while importing DE-HDL sheets- n z$ ?9 {) n. M. l& ~, N
2212406 ADW PART_MANAGER Allegro System Capture: Part Manager is deleting properties from all instances upon Update
" \& F$ O6 w: t' g, m/ r, f2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name1 a+ w& u- V0 e3 q& e4 p
2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to Team Design; h! _9 }# D) s6 I. B4 n
2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object
* V1 y1 Y0 f0 d' h2048086 ALLEGRO_EDITOR 3D_CANVAS Wire bonds are not linked to die pad when component is embedded body down
- e1 `3 F7 V9 w5 T2051277 ALLEGRO_EDITOR 3D_CANVAS Vias are offset from board in Z direction in 3D Canvas
+ \% d' `' Z6 d5 m$ |2054243 ALLEGRO_EDITOR 3D_CANVAS Plating is not shown on stacked vias in 3D canvas
9 o1 L" L/ M; {; C2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation
0 r9 J( @7 p9 {' _5 e! v2079732 ALLEGRO_EDITOR 3D_CANVAS Enhance 3D Canvas to merge the lines segment and overlapping lines and shapes
l* \- R. C- X; j0 b2206045 ALLEGRO_EDITOR ARTWORK Artwork Control Form fails to create film if Film record has a period (.) in the title, I X# s* v6 K+ G0 x' I
2209200 ALLEGRO_EDITOR ARTWORK PCB Editor stops responding on rebuilding apertures without rotation
, N( [. e8 g* g5 h4 R/ X3 B2244407 ALLEGRO_EDITOR ARTWORK Automatic editing apertures with rotation takes time in the General Parameters tab of Artwork Control Form0 Q$ c0 w6 j4 x. V u
2267942 ALLEGRO_EDITOR ARTWORK Allegro PCB Editor stops responding when generating apertures in HotFix 0063 m" @3 R3 n. z, \! Y/ K) v. y w
567342 ALLEGRO_EDITOR COLOR Add option under View menu for 'load color view'
6 R; B4 ?3 Z6 ]8 f' l; W( E637828 ALLEGRO_EDITOR COLOR Line highlights in 'shape select' command4 B+ W, J6 X7 L, A
720274 ALLEGRO_EDITOR COLOR Add menu option for the 'colorview load' command9 d b8 K3 M8 \* V3 d
1602652 ALLEGRO_EDITOR COLOR Color/Visibility behavior variation using "Enable Layer Select Mode"
7 X) P, n* y, N2 b; W7 i5 e2072695 ALLEGRO_EDITOR COLOR Clines of colored nets not colored when 'display_nohighlight_priority' is set
( W) ^6 g4 w) j6 L2 p& x2207580 ALLEGRO_EDITOR COLOR Component color is inconsistent when display_nocolor_dynamics is set.; h5 O, e! b s; a! A: C
2056497 ALLEGRO_EDITOR DATABASE Place manual is slow
. d# Z8 H+ M( r( @& \2250988 ALLEGRO_EDITOR DATABASE Inner Layer keep out as illegal subclasses: Shape object may not exist on layer ROUTE KEEPOUT/INNER_SIGNAL_LAYERS
1 C+ R. ]7 s8 d! [; K5 Z2096958 ALLEGRO_EDITOR DFA Cannot launch Constraint Manager after assigning CSet and closing% h& I2 Y$ {3 z ]0 w. I. Y
2049681 ALLEGRO_EDITOR DFM DFF check for plating in via should not flag DRC for surface mount testpoint Via- N2 ?7 N' C- a$ h& l/ M: f9 J
2155060 ALLEGRO_EDITOR DFM Inconsistent behavior in displaying DRCs for Via to Via spacing
# f9 _9 K" A, ?# R! U2166431 ALLEGRO_EDITOR DFM DesignTrue annular ring thru pin pad to mask checks compared to smd pin to mask checks are inconsistent in behavior
' _) ?4 j. J! e- X4 _2221975 ALLEGRO_EDITOR DFM DFM missing mask check reporting mask is missing when pins have a mask geometry overlaying them.
9 E- {4 P; L/ i1 H2249498 ALLEGRO_EDITOR DRAFTING When a Symbol with a Dimension is placed on the board, an extra Dimension is added to the Symbol origin.
2 F: |; l* O( E: t* E6 K8 G) f2250631 ALLEGRO_EDITOR DRC_CONSTR Cannot import netlist into design due to illegal DRC element: no DBDoctor error
# D" g8 c: |/ S9 P1794593 ALLEGRO_EDITOR EDIT_ETCH Unable to deselect return path vias selected when creating High-speed via structures
) O5 i0 A$ _' S; t2099538 ALLEGRO_EDITOR EDIT_ETCH Gloss - Via Eliminate shifts traces to another layer
( k3 Q% c, }" Z# e* {2204339 ALLEGRO_EDITOR EDIT_ETCH Differential pair line lost during slide operation
- ]* n& W/ n: @ f- T$ u2208938 ALLEGRO_EDITOR EDIT_ETCH Slide operation makes one of the differential pair cline invisible
# u) g1 n. Z/ |& |) Z8 [2222047 ALLEGRO_EDITOR EDIT_ETCH One of the traces disappear when sliding a differential pair in single trace mode
' i# z- }9 K# U/ f: r3 ]& Y2233991 ALLEGRO_EDITOR EDIT_ETCH One cline of a differential pair disappears temporarily upon sliding the Differential Pair in Single Trace Mode0 Z# [/ b4 p: B9 p
2240827 ALLEGRO_EDITOR EDIT_ETCH Cline of a Differential pair net disappears after sliding the other net of the Differential pair
( E! s) u9 {6 \) @$ q; H0 u2245775 ALLEGRO_EDITOR EDIT_ETCH Differential pair slide in single trace mode removes other trace
: I$ G9 @6 a/ C: H1813358 ALLEGRO_EDITOR GRAPHICS Allegro PCB Editor enables shape boundary when disabling etch layer in Visibility pane
3 K" t( q/ D- Y1911613 ALLEGRO_EDITOR GRAPHICS The subclass for boundary class stays on, even if Subclass for Etch Class is turned off from Visibility tab9 s, u F5 `1 W5 S; I
1966343 ALLEGRO_EDITOR GRAPHICS Shape boundary remains enabled even after turning off the etch layer visibility9 [% l; @ |4 W0 }4 k
2195276 ALLEGRO_EDITOR GRAPHICS Selecting File view is slow
* U9 h' ?! S& ^$ J) W! m4 y0 H- z2031883 ALLEGRO_EDITOR INTERACTIV Sub-Drawing: Clipboard origin point is not set correctly3 _4 R) F4 D' h: j$ X3 c- [ {) k) E
2050177 ALLEGRO_EDITOR INTERACTIV Letters need to remain aligned and uniform after performing Shape ANDNOT operation
- t- Z# Y& k6 y# E' ~. c: Y2069247 ALLEGRO_EDITOR INTERACTIV DFA bubble on wrong layer after mirroring the part
) E0 P y2 D2 L9 g+ h2103711 ALLEGRO_EDITOR INTERACTIV Placement edit mode popup 'Rotate' leaves ghost image in the background8 n+ q, O( R' r e" l; w" b6 ]
2136859 ALLEGRO_EDITOR INTERACTIV DFA Problem if we mirror component while placing" i4 H9 W. v" Z: C
2165027 ALLEGRO_EDITOR INTERACTIV Different behavior in OrCAD Capture when using crossprobe to select Power nets0 z" K* m& z9 D* _! {
2240235 ALLEGRO_EDITOR INTERACTIV The design file name changes automatically to board template name while creating new board (wizard)., G8 {& r/ g1 ]) P% B- ~0 q! V3 e
2244765 ALLEGRO_EDITOR INTERACTIV License 4150+226 does not have AiDT/AiPT in release 17.2-2016
; K% h2 X9 h G9 j6 A2 c$ Q2259800 ALLEGRO_EDITOR INTERACTIV DFA DRC circle not shown on the layer of placement in Placement App Mode5 h) |! X9 x4 H2 g* ~ S. L4 P2 B
2120420 ALLEGRO_EDITOR INTERFACES Drill figures missing in the exported PDF if drill legend deleted
4 g3 {3 u5 a7 j0 u$ v, D2136454 ALLEGRO_EDITOR INTERFACES Export - PDF output is not correct- A; X4 }' j7 i1 {: a: P
2116748 ALLEGRO_EDITOR IN_DESIGN_ANA Impedance vision data not available for cline segments for some nets, t1 M9 p* d- ~9 `' k/ p
2138977 ALLEGRO_EDITOR IN_DESIGN_ANA Impedance check results are incorrect and Crosstalk analysis stops running after updating to 17.2-2016, HotFix 057+ E" D" K1 L* L
2247167 ALLEGRO_EDITOR IN_DESIGN_ANA IDA Impedance Analysis: Add an option to export CSV automatically% t3 [% I4 g! y9 P Y
2222638 ALLEGRO_EDITOR IPC Documentation Editor crashes with error: Failed to complete the job because of unspecified error
- q; U0 _+ S7 ]! ~2106425 ALLEGRO_EDITOR NC Disable undersize regular pad and oversize soldermask pad for start layers in Backdrill Setup and Analysis
+ \0 T) g0 R# Y6 n% ~2091932 ALLEGRO_EDITOR OTHER Unsupported Prototypes command missing for the OrCAD licenses# `& b" j$ K+ M4 m# P9 ?
2221345 ALLEGRO_EDITOR OTHER Speed up Allegro PCB Editor startup by removing check for defunct PCB/Package co-design capability (NG_450), ?/ e# u: }+ r' J# r
2257934 ALLEGRO_EDITOR PLACEMENT Error (SPMHGE-626) on place component: Symbol not valid on any layer
0 z& U, w- q/ B5 j1001000 ALLEGRO_EDITOR PLOTTING File - Plot in PCB Editor does not plot more than one copy
) z+ ^- W: N Z* N+ b2234538 ALLEGRO_EDITOR REPORTS Allow Unused Blind/Buried Via report to run as Batch Process through the reports batch command% R# m, _0 h6 W" s( ~! W( c
2222738 ALLEGRO_EDITOR SCHEM_FTB Netrev not completing, showing error for electrical constraints data (pstcmdb.dat) import
2 M4 J; t# e2 E2255426 ALLEGRO_EDITOR SCHEM_FTB Netrev is running for hours without closing* F G+ |0 D7 X, y/ A4 n8 Q5 s
1702190 ALLEGRO_EDITOR SCRIPTS Allegro PCB Editor script file: Some sub-classes not created and error for form field label3 u! F) w/ t* o, V" e
1791099 ALLEGRO_EDITOR SCRIPTS Allegro PCB Editor does not terminate when the script is run with '-nographic'" B* z) r" b7 n2 t F# b
1791267 ALLEGRO_EDITOR SCRIPTS Allegro PCB Editor script does not run with '-nograph' in release 17.2-2016- T$ F" z6 R- p ~
1892520 ALLEGRO_EDITOR SCRIPTS Allegro PCB Editor stops responding for script when run with '-nographic'8 O J" l3 H, \/ M
1962010 ALLEGRO_EDITOR SCRIPTS Allegro PCB Editor stops responding for script when run with -nongraph option5 }! k2 k1 G8 D! q: W1 O
2056857 ALLEGRO_EDITOR SHAPE Shape boundary error by shape parameter
( ?5 b. h% S# n8 _2081946 ALLEGRO_EDITOR SHAPE Shape Update takes twice the time in release 17.2-2016, HotFix 053 as compared to HotFix 047
8 `, g! i" a6 u" ?9 x+ M1 V) l2104559 ALLEGRO_EDITOR SHAPE PCB Editor crashes while performing shape operation 'andnot'
/ W) z7 Z. W6 U q2108207 ALLEGRO_EDITOR SHAPE No Void Overlap option is not working in Auto Metal Balancing (AMB)) Y* P) _# G5 d0 g4 d7 m
2240996 ALLEGRO_EDITOR SHAPE Detecting Shape Island: Ignored for copied or moved shape
1 E; O0 C1 G+ t9 Q5 a2258758 ALLEGRO_EDITOR SHAPE Allegro PCB Editor crashes when routing two signals together9 f/ N# _& I+ R
717389 ALLEGRO_EDITOR skill Ability to set and return the application mode using SKILL
2 _( }# Q% i5 v2 n853160 ALLEGRO_EDITOR SKILL Need ability to get and set application modes using SKILL" F1 b- g( S9 |
981446 ALLEGRO_EDITOR SKILL Request the ability to get and set application modes using SKILL; P* F R: E, n% C- X; t
1235409 ALLEGRO_EDITOR SKILL SKILL option to get application mode
& R! F' Y. ]. H. P1316962 ALLEGRO_EDITOR SKILL SKILL option to switch between application modes* U9 s( ~6 Z2 K0 P
1553621 ALLEGRO_EDITOR SKILL Ability to change application modes using SKILL function6 k, h# K5 x" t) Z! v
1885442 ALLEGRO_EDITOR SKILL Ability to change application modes using SKILL function.& K7 c2 g) _! [5 E5 T7 T
2080351 ALLEGRO_EDITOR SKILL SKILL to determine current application mode
$ X ?4 w3 L: e; L4 z; Y! u8 _2195645 ALLEGRO_EDITOR THIEVING Thieving pad cannot be added on some areas in the board in latest hotfix but could be added earlier
: g! Z* e: ?$ D7 d1721594 ALLEGRO_EDITOR UI_FORMS STEP name Filter for STEP Package mapping form should be case insensitive
- `( t" m3 Q5 g4 z! _2090604 ALLEGRO_EDITOR UI_FORMS Undo/Redo UI grayed out when invoking Color192( `. t, \' A5 ^; ]+ M2 G
2203278 ALLEGRO_EDITOR UI_FORMS 'Width' keyword in Place Rectangle field is grayed out when Place Rectangle is selected) s. z1 [& e9 I) O& j/ `# d
2209172 ALLEGRO_EDITOR UI_FORMS Labels truncated by drop-down lists in Options ('Manufacture' - 'Drafting' - 'Relative Copy')
- L1 T7 i7 |. v8 k9 [8 C8 Y9 u5 Z2239426 ALLEGRO_EDITOR UI_FORMS Cannot start text size with decimal in 'Design Parameter Editor' - 'Text' for English (Denmark) regional settings
5 ~ F0 Z& i5 Q8 c) v E2245035 ALLEGRO_EDITOR UI_FORMS The right edge of the default Define Grid form looks cut off in 17.4.$ ?: {/ M+ ?' j# u
2245955 ALLEGRO_EDITOR UI_FORMS Resizing of 'Reject Item Selection' window not possible in release 17.4-2019, HotFix 004
! \7 N4 l+ ^0 n! p( c. W2249202 ALLEGRO_EDITOR UI_FORMS Extra click required to activate Pass field in Autorouter form
$ j" J8 E4 Q% Z* }$ ^2259605 ALLEGRO_EDITOR UI_FORMS Add ability to resize Reject pop-up$ |/ h, \4 L) U) }) N7 n! s; g
2090517 ALLEGRO_EDITOR UI_GENERAL Shape visibility box is not being enabled with the Enable layer select mode option in the Visibility Pane
9 v- W$ m! z$ O+ k2092436 ALLEGRO_EDITOR UI_GENERAL RefDes length of input string for Modify Design padstack is limited to 20 characters; h# m( }* _& n, d1 A% L
2134781 ALLEGRO_EDITOR UI_GENERAL The Pin Class is missing in Options tab when creating or opening a Mechanical Symbol
* d, |7 q& E6 c2 w# V7 U/ i) Z! q% F2168026 ALLEGRO_EDITOR UI_GENERAL Edit Properties UI slow to launch for boards with many drawing properties
- _% J8 r4 k: q3 Y) c2191267 ALLEGRO_EDITOR UI_GENERAL Changing Visibility of any object type disables links in Layer Select Mode in the Visibility pane
9 h, S, [6 }5 _% q9 J* `, z% f2208018 ALLEGRO_EDITOR UI_GENERAL Text on BGA pins not visible in release 17.4-2019 if not zoomed to maximum! @2 G( r/ y8 O( l2 P* h8 ~ t8 b
2225753 ALLEGRO_EDITOR UI_GENERAL dark theme does not respect TRBICON size for 4K monitors
. j$ e' Q. y- h8 l2256841 ALLEGRO_EDITOR UI_GENERAL Enlarge the Shape Copy to Layers form as the window is quite small and not resizable
0 N% t" \* T1 r, n4 w; c/ m2258019 ALLEGRO_EDITOR UI_GENERAL Canvas turns white after closing STEP Package Mapping window
2 I, l! n0 E" z( G; B0 _1 Y2258167 ALLEGRO_EDITOR UI_GENERAL Enhance 'Shape copy to layers' window in release 17.4-2019 to expand or resize
/ g* c& Z, a3 d2262305 ALLEGRO_EDITOR UI_GENERAL Assign Differential Pair form list box size too small to add signals
! O$ T& S3 d0 F% N7 B2086574 APD OTHER APD is showing duplicate layer text on the vias7 p$ f; m0 p0 I1 f% B/ h
1723825 APD SCRIPTS Allegro Package Designer in release 17.2 is not writing out to either jrl files or script files in real time./ E: E# k% m* H# D+ g3 Y B* E
2186363 APD UI_GENERAL Text on the Pin is not visible until zoomed in to certain extent: N# M' V: s8 L" Q. F
2253484 APD WIREBOND APD stops responding when running 'wirebond soldermask create' with 'Measure from soldermask pad'
, G/ n) n8 h: @1 R( M( `6 W2241725 CAPTURE DRC Waive DRC option not working from batch DRC window$ i. B0 R! y9 R& u
2243645 CAPTURE DRC Online DRC bug in release 17.4-2019, hotfix 004 - offpage connector does not have wire2 z- h, u, Q) Q* |- C' o- ]- E. `
2250867 CAPTURE DRC Hanging wire custom DRC not working when selected standalone, ~+ `! p* k2 P1 M1 E3 K
2252912 CAPTURE DRC Unable to create new DRC file using Browse button in DRC window: B" E+ x: `5 Z- O$ P9 ]8 m
2047391 CAPTURE PART_EDITOR Pin type cannot be changed in release 17.2-2016, hotfix 051+ f, h" ^7 j9 k8 X d& ?8 T
2183187 CAPTURE SCHEMATIC_EDI OrCAD Capture: Ctrl + N seems to call a legacy dialog that allows projects to be created with no name+ }+ M9 n9 f9 p+ e" ~
2190602 CAPTURE SCHEMATIC_EDI Cascading options of Window menu not working in OrCAD Capture in release 17.4-2019
3 E, ]4 N3 m' v. q r2194374 CAPTURE UX Design Sync issues: Session log does not report information about errors
. b" `9 h& V. p2183037 CIS LINK_DATABASE CTRL-L shortcut for Link DB-Parts for Query in CIS-Explorer not working
! m) }3 @9 a3 f$ i3 c* R! J2201323 CIS PLACE_DATABAS Capture CIS displays empty dialog on placing part from database in release 17.4-2019
& n8 U; @% m/ P1 g& f. _2216963 CIS PLACE_DATABAS Light Theme: Warning text not visible in Capture CIS dialog. k- g& V8 R' T! q6 ^6 F, D& N ?
2246354 CIS PLACE_DATABAS Warning (ORCIS-6159) pop-up window is blank.$ U& i& M8 s6 J. z& W/ s+ f
2230651 concept_HDL CHECKPLUS Discrepancy in the 'checkplus' marker files# G2 p6 A- O7 A9 N' V0 o
2237145 CONCEPT_HDL CONSTRAINT_MG T-Points match groups get deleted after saving a design
, d! |) u& n/ a2246452 CONCEPT_HDL CORE Page information gets removed from 'master.tag' of the top-level design when subdesigns are read-only6 P9 z/ N7 h% c) M |: P9 m
2057490 CONSTRAINT_MGR CONCEPT_HDL Constraint Manager Worksheet flips after running hier_write when CM is open" z: G# }: K* C3 l) f0 h
2236329 CONSTRAINT_MGR CONCEPT_HDL Pin Pairs not added to Match Group
4 N/ _ h" c6 D. s0 s& J2214367 CONSTRAINT_MGR INTERACTIV CSet assignment matrix sorting in Net Class-class random in Capture to Constraint Manager flow
: x0 R( M0 x$ \4 f P5 [2243574 CONSTRAINT_MGR OTHER CM SKILL cmxlPutAttribute() cannot set constraint value7 {7 N+ j4 _: X: g8 t5 B; p
2259598 CONSTRAINT_MGR OTHER Importing netlist: Error for electrical constraint data (pstcmdb.dat) import6 A8 `, e; Z% Z9 U- w3 n$ C
2207862 CONSTRAINT_MGR SYSCAP Save icon and 'File' - 'Save' menu in Constraint Manager is inactive3 }8 l. {& `- z( z3 D- u
2200316 CONSTRAINT_MGR UI_FORMS Expanding 'Analysis Mode' form resets column width
2 o+ n ?8 R5 w# f) I9 q2097479 PCB_LIBRARIAN CORE Symbol import in Part Developer does not show the correct pin shape.+ P/ e# z' l- {! [1 b
2145385 PCB_LIBRARIAN CORE Error-SPLBPD-972 reports missing parentheses in the ALT_SYMBOLS property of a part3 |. ]4 Y. `; _3 v4 N q
2202622 PCB_LIBRARIAN CORE When adding a new pin to a symbol in Symbol Editor, the space between pins changes9 k+ W$ g) a+ W; Q) z' O# e% {$ B
1955570 PCB_LIBRARIAN FLOW Using the PACK_SHORT property with more than 256 characters does not work or report an error on packaging
5 V0 g9 A5 q6 M* T* R7 h7 |2072190 PCB_LIBRARIAN FLOW Allow PACK_SHORT property value longer than 255 characters. k) ^% h3 f7 q
1720395 PCB_LIBRARIAN IMPORT_OTHER Converting OrCAD Capture OLB to Design Entry HDL library adds braces to pin number o4 T$ K! _+ N: O) G
2141340 PCB_LIBRARIAN SETUP SPLBPD-216 Error logged in PDV even when MAX_SIZE Sheet is defined
" u. Z( s* Q) z, Q; G) Z K2214973 PCB_LIBRARIAN SETUP Unable to apply symbol property templates when PDV lock directives are set
1 x5 G3 V3 u4 S( y5 N2257527 PCB_LIBRARIAN SETUP Locking PDV directives prevents applying symbol property templates
6 l. A1 ?/ I" G+ ~6 w* x4 m6 B2033898 PCB_LIBRARIAN SYMBOL_EDITOR Running Symbol Editor with no arguments results in a background process, not an error.8 J$ D3 K9 S8 i b0 R
2093849 PCB_LIBRARIAN SYMBOL_EDITOR Symbols and font sizes appear different when placed in designs, e' T, y |1 m- Q% k6 i+ B
2200399 PCB_LIBRARIAN SYMBOL_EDITOR Multiple issues observed when editing parts in the New Symbol Editor. K/ m: V! W5 m1 Z. C
2218940 PCB_LIBRARIAN SYMBOL_EDITOR Duplicate pins cannot be removed
0 }% N5 `) K2 S8 C5 D5 C+ [! [2230542 PCB_LIBRARIAN SYMBOL_EDITOR Bus pin location changes after expanding or collapsing pins in Symbol Editor
- A# u: i& {+ J4 A) d# m) v. i2239303 PCB_LIBRARIAN SYMBOL_EDITOR Expanding and collapsing a bus is changing the msb and lsb for the pin name
* h/ ?' V/ f9 s! j+ s2243431 PCB_LIBRARIAN SYMBOL_EDITOR Group of pins that are not adjacent cannot be moved together
, e, E5 R" U4 p5 S; p, }: \2 M2029056 PCB_LIBRARIAN SYMBOL_EDITOR Unable to change Grid Settings in Part Developer, h U/ C$ `; d2 ~
2149948 PCB_LIBRARIAN SYMBOL_EDITOR New Symbol Editor and System Capture moved pins from 0.01 grid to 0.05 grid.& m& J+ C9 e. i
2206975 Pspice MODELEDITOR PSpice Model Import Wizard symbol preview readability improvement requested
; {" a9 i6 s1 p' f% Y( P* U2211187 PSPICE MODELEDITOR Model Editor color scheme not readable
( k( {4 A( O- R$ E( \2214415 PSPICE MODELEDITOR Symbol view in Model Import Wizard has a visibility problem
' W9 D3 T1 O. i* o: G( p2199570 PSPICE PROBE Unable to 'select sections' after Monte Carlo runs with Temperature( L: c# l2 [$ U3 [ b3 H
2244140 PSPICE PROBE Not able to select multiple sections to plot in probe
. I w/ I! G2 s2249565 PSPICE PROBE Selecting multiple traces for PSpice A/D Monte Carlo run not working
# B+ l9 f6 X0 [( t3 f2171626 PULSE CORE Pulse crashed with error related to third-party development kit platform issue
5 W; q& R- e# ^# L Y2221523 PULSE UNIFIED_SEARC Cannot log in to third-party search providers but can log in to Cadence Online Support
5 D8 w6 P/ B" `0 c! \2019229 RF_PCB OTHER Layer conversion file data does not update GDSII layer mapping using Package Symbol Wizard
5 ]% ]( `* \) s+ K' R. ]9 G5 ^820288 SIP_LAYOUT COLOR Layer Priority command does not seem to be functioning: e9 w a' R' i1 T* V/ z1 [
820305 SIP_LAYOUT COLOR Layer Priority menus do not match the Color dialog in the package substrate tools
8 K/ i2 X2 e% Y5 l: H2256044 SIP_LAYOUT DATABASE Fix teardrop does not work for some situation: Deleting fixed fillets
6 E- F, [2 ]- S9 w3 }' W2 I5 d2254932 SIP_LAYOUT DEGASSING APD Plus generating assertion failures when running degassing mode with script
; K2 a5 a7 b P5 w! j2106314 SIP_LAYOUT INTERACTIVE Large design causing severe lag in Windows Server machine
! d# X( d. ^. v$ U2096239 SIP_LAYOUT STREAM_IF Database fails to create stream out file+ |" I+ n6 o/ Y
2079071 SIP_LAYOUT SYMB_EDIT_APP Response very slow after Show IC Details on a very large co-design die
- a+ ^4 J I3 O! o$ ?: N, |2251630 SIP_LAYOUT WIREBOND 'Change Profile' does not change the diameter of the wire bond) b. c% x$ P0 ]3 G) a; U
2253633 SIP_LAYOUT WLP Advanced degassing passing illegal arguments to dba routine! ^3 f# }% N# B1 j ?
2259630 SIP_LAYOUT WLP Advanced WLP: Import PVS DRC results in error4 H' L! U* F5 ?9 s. s' ]; I
1968437 SYSTEM_CAPTURE ASSIGN_SIGNAL Net name pasted in lower-case though uppercase input is enabled7 W; O7 a- i. J
2131976 SYSTEM_CAPTURE AUTOMATION syscap exits when run with the -tclfile argument and an invalid Tcl file
2 k& c7 A3 J$ f; D& Q1983063 SYSTEM_CAPTURE BLKDIAGRAM_AU Auto Shapes are being shown as part of components
/ C3 X. [5 s% K# F& r( h- M1977673 SYSTEM_CAPTURE COMPONENT_BRO adding reference blocks through add component error when cell name matches design name
* t6 x# r% |! C+ B. R; [4 f: @+ J/ _2247567 SYSTEM_CAPTURE COMPONENT_BRO Symbol property placeholder changes not updated on the canvas0 ^4 Y* A+ z7 r `7 f' A
2027100 SYSTEM_CAPTURE COMPOSITE_FIL pstdedb.cdsz and netlist preview in System Capture is not being updated when individual netlist files are written9 y6 u9 D6 C' k; Z7 c/ f
1863460 SYSTEM_CAPTURE DARK_THEME thumbnail preview of pages is in light them but dragging the page the previes is dark H4 `! P4 M" R; j8 n6 l
2168622 SYSTEM_CAPTURE EDIT_SEARCHRE Reports from Find Results are dumped even when the operation is canceled* C8 l( P5 M5 W6 M5 {" E% l7 {! W
2168625 SYSTEM_CAPTURE EDIT_SEARCHRE Sort icons for columns in 'Find Results' are incorrectly placed: appear to be in adjacent column
1 Q; l$ D' G1 h' V1895142 SYSTEM_CAPTURE EXPORT_PCB System Capture incorrectly reports unsaved changes when closing after running export physical. {5 Y5 c$ C3 j9 j3 M
1931660 SYSTEM_CAPTURE EXPORT_PCB SDA is non-responsive while Allegro launches and opens a board when launched from SDA; ?# M7 J# z% u7 g" c$ W
2087387 SYSTEM_CAPTURE EXPORT_PCB System Capture: After Export PCB completes, busy cursor shown for a while3 P* q. v7 M2 _! |: U
2202179 SYSTEM_CAPTURE FIND_REPLACE Replacing a net name with the same name by using Find and Replace results in a crash7 ~7 @5 X4 t- q! s0 b
1843885 SYSTEM_CAPTURE FORMAT_OBJECT Renaming a net causes it to lose custom color assignment' |6 b2 c( Z) H: J# o2 o1 f
1993208 SYSTEM_CAPTURE FORMAT_OBJECT Setting font prior to placing text does not work, pop-up does not work, and bucket results in scrolling page
+ r0 F8 p( A, r# I2231399 SYSTEM_CAPTURE IMPORT_BLOCK 'importBlock' Tcl command not working when using a script
# F4 \- c% T1 j) c1907729 SYSTEM_CAPTURE IMPORT_DEHDL_ Import DE-HDL sheets - differential pair properties on nets are lost
8 Q$ }, T" w8 o' ?& _3 H* d2025949 SYSTEM_CAPTURE IMPORT_DEHDL_ Title block and thick wires/lines of border in DE-HDL do not translate in System Capture% Z$ G1 G, o2 K
1942542 SYSTEM_CAPTURE IMPORT_PCB System Capture - TDO backannotation overwrites net names with stale data in lower-level blocks# M& W2 }4 K# N$ o* h
1982320 SYSTEM_CAPTURE IMPORT_PCB View files are not created in the schematic-to-board flow* M+ e) G, F* j# I3 }( j
2117532 SYSTEM_CAPTURE MENUS_AND_TOO Ability to customize menus for a site' B: ?$ m6 r+ r4 P( X; G/ D( m9 H
2213478 SYSTEM_CAPTURE MENUS_AND_TOO Help - About menu item appears twice
$ j2 S) v- _, v s' ^: V* h! n1910941 SYSTEM_CAPTURE MISCELLANEOUS Parts that are not in any schematic page appear in netlist and BOM Z; d' A# ~9 k- A5 o
1967614 SYSTEM_CAPTURE MISCELLANEOUS Dragging a circuit with net aliases does not move the net aliases with it! N& |# P; [$ D2 [: ?: F8 T) I s
2189846 SYSTEM_CAPTURE MISCELLANEOUS Inconsistent display of same font5 K! a& p8 L" s8 ^
2178961 SYSTEM_CAPTURE NOTES Cannot add Japanese text in notes in release 17.4-2019 on Windows 10
/ P: ?. M+ b' ^+ n" i1973437 SYSTEM_CAPTURE OPEN_CLOSE_PR Opening a design crashes System Capture
2 N+ }7 _- [; D3 M4 O' F( a& h2079857 SYSTEM_CAPTURE OPEN_CLOSE_PR System Capture: Unable to select design to open if license selection box is canceled the first time; ~' \8 B$ X8 g+ x$ n' ] u
2065025 SYSTEM_CAPTURE PACKAGER Export to PCB Layout reports wrong path but exports correctly' o/ `' {$ k) Y6 o. B
2229611 SYSTEM_CAPTURE PACKAGER Path for the 'packaged' folder shown in the 'Export Physical' is incorrect
( z7 Z' Y( Y6 b: D8 I E2 ~) m; W1993146 SYSTEM_CAPTURE PROJECT_EXPLO Cannot move page up by only one position
% h' b7 Z' Q' J' B7 h! i1892120 SYSTEM_CAPTURE PROPERTY_EDIT Some parts are missing reference designators and some have two properties - RefDes and REFDES4 t f6 b2 F7 p' S# r
2201060 SYSTEM_CAPTURE PROPERTY_EDIT Some of the icons in the Properties window do not have tooltips$ C* d8 T/ K" z1 T; Y% Z- u+ v
2246667 SYSTEM_CAPTURE SCRIPTING Running the 'replay.tcl' script gives an invalid command name error
# f( o$ {) W! @* l) G2010032 SYSTEM_CAPTURE SHORTCUTS Cannot enter Page-Up/Page-Down as shortcuts
# M9 J6 ]) T( S/ z/ A2017985 SYSTEM_CAPTURE TDO Allegro System Capture ability for multiple users to open a design
$ _9 E5 s+ m8 A* ^* l$ q: v$ j1 |2106743 SYSTEM_CAPTURE TDO Ability for multi-user access to the same schematic
& {* e& x$ s/ p3 ^6 ]; j# e |2209628 SYSTEM_CAPTURE UI Tooltips for Design Rule Checks are getting truncated* I& `4 e3 F" @& o1 Z" Y8 M
1990258 SYSTEM_CAPTURE VARIANT_MANAG Cannot paste copied preferred part to multiple parts with the same part number
3 M* o' E. e! q# p# e2032005 SYSTEM_CAPTURE VARIANT_MANAG Custom variables not saved for variants
) K/ t3 `$ C7 C7 C" m' f n2228299 SYSTEM_CAPTURE VARIANT_MANAG CAP parts should not show up in the Preferred Parts list when changing a RES0 g4 a1 a3 O0 \* ]- f! F( w5 N
1627835 SYSTEM_CAPTURE WIRING Inconsistencies in wire movements7 o! n$ _$ y7 e+ J, }
1670888 SYSTEM_CAPTURE WIRING Rotation error when a component is connected to a power symbol
: {+ `1 [& I3 t. [( C5 b: x' ^1721863 SYSTEM_CAPTURE WIRING Net names move to random locations when components are moved around the canvas.
8 H7 N; Y$ i+ `1960130 SYSTEM_CAPTURE WIRING Disconnected nets when using the mirror option
( b# h& ]: g+ J9 Q; w) b) }; {1961274 SYSTEM_CAPTURE WIRING XNet removed during pin swapping
2 o0 g3 {) s; ]1968463 SYSTEM_CAPTURE WIRING System Capture should not allow illegal characters to be entered for net names5 v( J9 L. i7 a. B3 | d
1973426 SYSTEM_CAPTURE WIRING Selecting multiple net names and trying to delete only deletes one net name.
- i' J) S: i8 }. V, p, o1978381 SYSTEM_CAPTURE WIRING 'oops' does not remove the first vertex placed
9 C# P5 _, h( x- F; g3 G# c1985029 SYSTEM_CAPTURE WIRING Net aliases are not dragged with circuit, they appear to move after the circuit is dropped
1 O; \/ D7 \- A0 z7 H0 [5 B2013647 SYSTEM_CAPTURE WIRING Replacing a vertically oriented RES with a horizontal CAP breaks the wire connections
" R3 E" B+ o3 g5 a$ K0 g5 l% Q2014188 SYSTEM_CAPTURE WIRING Context menu not working in Variant mode0 S8 G/ j( ?4 J8 B; C4 k
2041879 SYSTEM_CAPTURE WIRING XNets generated for nets with pull-up resistors
+ D. e3 B% f4 Y- k2050533 SYSTEM_CAPTURE WIRING Need an option to increase junction dot size
$ q8 ]! l$ [4 M: D0 c2061877 SYSTEM_CAPTURE WIRING Unable to add a power symbol with the Place - Special Symbol menu
& S+ M4 @- a$ Z. y0 t2079409 SYSTEM_CAPTURE WIRING Increase the size of the wire connection dot in System Capture
2 ?$ y0 ~4 B1 T( i- L3 G& G8 L2081884 SYSTEM_CAPTURE WIRING Symbols take a long time to move, and results in DRCs and broken connections! k0 D& j. P/ q$ }7 `- ]9 S
2085263 SYSTEM_CAPTURE WIRING System Capture: Focus lost from the Format tab if font name starting with typed letter is not present. p" q) f* \2 p- @9 A8 z# \$ H
2089569 SYSTEM_CAPTURE WIRING Ability to specify the solder dot radius size8 R" d5 x, `! Q n& V
* ]$ C* P1 _- b. gQIR1详细特性说明：
Hotfix_SPB17.40.007_README-Release_Notes.pdf
(2.51 MB, 下载次数: 55)
' t' u- |4 q5 p* Y待我上传完后附上链接，这次QIR1比较大，4.59 GB
M3 S' q/ P) Y0 O' q, O8 k2 g2 S& Y! O' ^$ U
* l" i% w( z! H/ M# ], B5 ^
- m0 T- _* {+ }5 J
8 A. z$ I% v1 n2 C$ l6 A4 P7 u; ~; T3 h" P
5 B# A$ I% Q$ Q7 Q
; n0 e$ b6 H4 {! S6 \
1 o! S6 b- {% J0 g# d) z/ C& ~- o# E& g; j0 v x( M- W* o
_2 j; T4 k4 ~7 D$ B: M" Z7 D
* O; ^6 h7 J% x! q, w4 X3 L7 c8 H2 j9 D( u. S
, H" u) W; y# E) L( Y
4 ?9 e: t+ \! _# _6 \% k+ [2 R- \& m, g! G- K
% p, [3 g. @5 a, U
( z( U" H% K8 Q7 F% G1 ?6 N5 U# |, j4 V" B. |9 g' Y: r2 [2 h
|
|
/1 
发表于 2020-6-8 02:00
收藏
淘帖
支持！
反对！
发表于 2020-6-8 09:10
楼主
