初用altium Designer 6,画ARM9的6层板,想做一下信号完整性分析,点“设计>信号完整性”后,出现如下错误提示: . K, _+ I, Q2 K$ J, @PCB components were not all linked to source schematic components.Run components links to link components or 8 Z) U m! y: u
see messages for details.3 Y0 g( E; T) C7 L) Q9 J8 W
/ Z4 y& X* Z3 l1 c7 t
不知道是怎么回事,一直解决不了,急需知原委的各位高手指点,先谢过了。 _5 f @6 j& r n4 M