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1 o t1 o% o; R- P+ v6 a1 K9 e5 A6 u/ E# Mendling with Feature lines will only invalidate them!
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' l I1 t9 q9 f3 c: ~- [2 |0 Q* \PACKAGE EFA-CDS-01 cdslmd 2019.12 50D0C0F14EEEF46F0FE0 \
$ X' m! d: s3 a* X COMPONENTS="A2dxf ABIT actomd adv_package_designer_expert \
9 e( H$ I( O2 ?3 n* \: C4 M" l9 H adv_package_engineer_expert ADV_USUPUC_ALL \
3 ?( y/ U6 F8 b+ z( J3 ]0 Q Advanced_Package_Designer Affirma_NC_Simulator \
( G& H2 ~/ \; y2 y' @+ A Affirma_sim_analysis_env Affirma_transaction_analysis \
, E; R/ |: P4 t Affirma_verification_cpit_rtim Allegro_CAD_Interface \
5 |4 w4 B, I9 w7 i, B7 C Allegro_design_expert Allegro_Designer Allegro_designer_suite \
8 R' X5 K; G3 B+ ] allegro_dfa allegro_dfa_att Allegro_Expert Allegro_Librarian \
$ b. g3 r; {- s+ ^( j allegro_non_partner Allegro_PCB Allegro_PCB_Interface \
! Q9 B7 G! ~' K. P Allegro_performance Allegro_studio Allegro_Symbol \# t: l/ G) L% s: ]2 @
Allegro_Viewer_Plus allegroprance ANALOG_WORKBENCH APD \
* l; y+ C* o1 f5 b9 l archiver arouter AWB_Batch AWB_BEHAVIOR AWB_DIST_SIM \
0 t7 q5 s# y( Y AWB_MAGAZINE AWB_MAGNETICS AWB_MIX AWB_PPLOT AWB_RESOLV_OPT \
0 P6 l2 W* E' \ [. Z6 a: n AWB_RESOLVE_OPT"
4 ]. T6 Y- ]% kPACKAGE EFA-CDS-02 cdslmd 2019.12 006030C10306920F9721 \
7 A0 p; i8 Q* B; F5 }/ a/ V COMPONENTS="AWB_SIMULATOR AWB_SMOKE AWB_SPICEPLUS AWB_STATS \
S( w: G1 _" B+ r# S AWBAA AWBSimulator Base_Digital_Body_Lib Base_Verilog_Lib \8 F2 [$ R( @0 n! I! }! K2 V
BOARDQUEST BoardQuest_Designer BoardQuest_Team BOGUS \6 f5 f b! i7 \/ _3 X
Cadence_chip_assembly_rtr_ALL Cadence_chip_assembly_rtrEngr \
* X7 Q D& }( }0 D4 u caeviews cals_out Capture Capture_CIS_Studio CaptureCIS \& l- r9 k; {% Q$ G8 V
cbds_in cdxe_in CHDL_DesignAccess CheckADV_ALL CheckFST_ALL \
; e' I+ R+ `4 d9 ?; H Checkplus_Expert CISoption comp Concept_HDL_expert \
6 S! B) ]1 v; [ Concept_HDL_rules_checker Concept_HDL_studio ConceptHDL \% P1 E* Z- F' A7 C% s8 r$ c
CP_Ele_Checks cpe crefer cvtomd CWAVES debug DFM_USUPUC_ALL \
" H. W1 |( j! C! f- T DISCRETE_LIB dracula_in". n7 |& D! k3 g8 U: O: Y
PACKAGE EFA-CDS-03 cdslmd 2019.12 40A0708139C03D1415F7 \
( E" s; q Q6 T2 \5 r COMPONENTS="dxf2a EB_4SUPUC_ALL EB_USUPUC_ALL eCapture \
X2 Q3 F9 T k4 z( i* | EDIF_Netlist_Interface EDIF_Schematic_Interface EditBase_ALL \; Q* Q1 ?7 f) }; f
EditFST_ALL EditPlace_ALL EditRoute_ALL EMCdisplay EMControl \
; P4 J: m9 _, z6 C0 w) H EMControl_Float EMI_ALL expert expgen explorer Express \: E: m2 m% a2 t7 o3 h" w% t
ExpressPlus Extended_Digital_Body_Lib Extended_Verilog_Lib \
( M0 U: v/ B! A0 }. a$ N8 a; E fethman fetsetup FloatPC_ALL floorplan Framework \4 _& b4 h% S# M9 O2 C5 U
fst_Usupuc_all FUNCTION_LIB gbom glib gloss gphysdly gscald \
* p( A0 I' W1 U# S4 w8 ?3 M' i S gspares HDL-DESKTOP hp3070 HYB_USUPUC_ALL IC_autoroute_ALL \
8 B, T0 M- N& V- h IC_device_place_ALL IC_devicegen_ALL"
2 u# `! b5 T. Q" c) xPACKAGE EFA-CDS-04 cdslmd 2019.12 30801091DAE1B711FC58 \, C& i: B; O, e- K1 O9 f" J
COMPONENTS="IC_deviceplace_ALL IC_edit_ALL IC_editfast_ALL \
5 A& H# n- O1 ]: l; U3 y& \2 O* L IC_gcell_route_ALL IC_hsrules_ALL IC_Inspector_ALL \5 Y+ q8 Y4 U( T' d& v* u3 ^. W
IC_InspectorEngr IC_InspectorEngr_ALL IC_mp_route_ALL \, Y' `/ r; K6 D0 C0 d5 o
IC_power_route_ALL IDF_Bi_Directional_Interface \
- q$ c3 u9 F+ @/ ~ @; G iges_electrical intrgloss Intrica_powerplane_builder intrroute \
4 f! e6 o" v" H1 u( G' E) \+ ` intrsignoise IPB_4SUPUC_ALL IPB_USUPUC_ALL ipc_in ipc_out \
% o+ u* d2 }) H/ p' a. o IPlaceBase_ALL Layout LayoutEE LayoutEngEd LayoutPlus \7 ^4 e& v5 r6 s& B
LEAPFROG-BV LEAPFROG-CV LEAPFROG-SLAVE LEAPFROG-SV \2 N8 i& h( \2 M7 O3 |
LEAPFROG-SYS LID11 LINEAR_LIB LSE lwb MAG_LIB MASTERTAG mdin \
+ K9 q6 E, X3 ], l- e* u mdout mdtoac mdtocv"$ B3 W; F* l+ G% t
PACKAGE EFA-CDS-05 cdslmd 2019.12 709080B1B225997E86A8 \
& @( W/ [. q3 o/ ^ COMPONENTS="MIXAD_LIB modelIntegrity multiwire \
; [& x' {0 @: ~2 d NC_VHDL_Simulator NC_SystemC_Simulator Nihongoconcept \* s& q0 |; b+ j
OpenModeler OpenModeler_SFI OpenModeler_SWIFT OpenSim \
3 ]5 {7 A. i) x+ E1 | OpenWaves Optimizer OptimizerAA OrCAD OrCAD_Capture_CIS_option \1 ~' Y' B1 c7 V4 \) M1 o
( C2 V" X6 {2 G" H9 r PB_USUPUC_ALL PCB_design_expert PCB_design_studio PCB_designer \1 [% P4 h- ^/ @% }; M
pcb_editor pcb_interactive PCB_librarian_expert pcb_prep \
1 o; H, P. i& P. j3 p. } PCB_studio_variants pcomp PE_Librarian PlaceBase_ALL placement \
5 k6 R1 o" V# x: \7 L6 z6 ^ PlaceOrIPlace_ALL plotVersa PO1100 PO1110 PO1300 PO1310 PO1320 \
9 }7 d3 R0 E4 \) L+ o( _" z/ I+ |! { PO1330"1 ?9 w; c7 t: u
PACKAGE EFA-CDS-06 cdslmd 2019.12 4030F0D1DDB23CB51B53 \
+ Q7 \/ ~/ g; I ^* D7 l COMPONENTS="PO1340 PO1400 PO1410 PO1420 PowerIntegrity \
( T6 S o* H1 d1 Y PPRoute_ALL Prevail_Board_Designer Prevail_Designer PS2010 \, N* C' H% z; z; p" v4 z4 j
PS2200 PS3010 PSpice PSpiceAA PSpiceAAOptimizer PSpiceAAStudio \$ {1 P+ b% {2 h
PSpiceAD PSpiceADAA PSpiceADStudio PSpiceBasics PSpiceStudio \6 G4 T# J/ m4 y! }
ptc_in ptc_out PWM_LIB PX3500 PX3710 PX3910 quanticout \
- H9 P7 M( M, o- H RapidPART rapidsim RB_4SUPUC_ALL RB_6SUPUC RB_6SUPUC_ALL \4 s8 b: @+ p8 ]" n2 n
RB_USUPUC RB_USUPUC_ALL realchiplm RouteADV RouteADV_ALL \! B. Z- b7 m4 A; }, n6 G
RouteBase RouteBase_ALL RouteDF"+ _% r/ B, ^( S* |) e
PACKAGE EFA-CDS-07 cdslmd 2019.12 40F0106176E4BBB2D3D1 \& j# R. M" g* M
COMPONENTS="RouteDFM_ALL RouteFST RouteFST_ALL RouteHYB_ALL \3 W% ^6 D1 ]( J+ I7 A
RouteMin_ALL RouteMVIA_ALL RouteOrEdit_ALL rt sdrc_in sdrc_out \
; N6 N! ?" y4 t shapefill signal_explorer signoise SigNoise_Float SigNoiseCS \ W, \5 ^4 j7 z J4 q) Z3 z
SigNoiseEngineer SigNoiseStdDigLib Sigxp sigxp_explorer \/ {( g# h" C) v$ ]1 {% O
Sigxp_tier Sigxp_tier_EXPERT SimVision skillDev SPECCTRA_256U \2 P0 F6 u- t% l, l% p
SPECCTRA_6U SPECCTRA_ADV SPECCTRA_APD SPECCTRA_autoroute \. b' e8 c8 K; }, z% s6 F
SPECCTRA_autoroute_ALL SPECCTRA_autorouteEngr \
- K; y# F; q$ t SPECCTRA_designer SPECCTRA_designer_ALL SPECCTRA_designerEngr \' n- x$ i* ^ a2 q0 p, |
SPECCTRA_DFM SPECCTRA_expert SPECCTRA_expert_ALL \
, G4 e# |1 _, L$ ? SPECCTRA_expert_system SPECCTRA_expert_system_ALL \
[. D% Y" y# @% Y SPECCTRA_expert_systemEngr SPECCTRA_expertEngr". \# x8 c V. _* s8 E
PACKAGE EFA-CDS-08 cdslmd 2019.12 4010E001C03C574EA29E \
. H$ ~+ s! v0 O* J0 M COMPONENTS="SPECCTRA_HP SPECCTRA_PCB SPECCTRA_PCB_ALL \& @. }+ S) \8 d0 s! U" ]# |- V+ H, [
SPECCTRA_PCBEngr SPECCTRA_performance SPECCTRA_performance_ALL \
- L2 b! L+ ?6 E# |: p/ u( Z! E SPECCTRA_QE SPECCTRA_VT SPECCTRAQuest SPECCTRAQuest_expert \
4 r" _" Z. ~: C1 N SPECCTRAQuest_Planner SPECCTRAQuest_SI_expert \
( N2 J: s. q% t7 A) ]: k7 q SPECCTRAQuest_signal_expert SPECCTRAQuest_signal_explorer \# d8 W* v. H- A2 U" @* \1 R
SQ_Digital_Logic_SI_Lib SQ_FPGA_SI_Lib SQ_Memory_SI_Lib \8 T: _1 a& B% `: F& s: ?
SQ_Microprocessor_SI_Lib stream_in stream_out StudioPSpiceAD \
1 U& q+ N/ E7 [8 i: H( v9 C swap SWIFT sx Synlink_Interface Team_EFA tscr tune tw01 tw02 \
; w8 e) ]6 W$ B' h* k, Q+ [: H UET ULMdelta ULMecho ULMhotel ULMindia ULMjuliette ULMmike \
; N9 t6 J" ]% e/ t9 \ Unison_SPECCTRA_4U VB_4SUPUC_ALL VB_6SUPUC"
, `, U# X( ]8 A% ~# u5 u" pPACKAGE EFA-CDS-09 cdslmd 2019.12 B0800091DEDE2463C4D0 \7 }3 u d3 x' m2 g9 k
COMPONENTS="VB_6SUPUC_ALL VB_USUPUC VB_USUPUC_ALL \* b& I8 P) _7 J1 F8 [- W5 r
VERILOG-SLAVE VERILOG-XL vgen VHDLLink viable ViewBase \" J! F# r7 ^6 c- l8 A9 l0 q
ViewBase_ALL ViewBaseEngr ViewBaseEngr_ALL \
( Z9 [; `9 L/ n. v& h) U Virtuoso_custom_router_ALL Virtuoso_custom_routerEngr \
* w2 M9 }; J; Q8 K/ I* r! o visula_in vloglink VXL-LMC-HW-IF VXL-TURBO VXL-VCW VXL-VET \
, B6 F- @8 D* @: K# a VXL-VLS VXL-VRA WinActel WinAltera WinAMDMACH WinAtmel \
% V# F5 \; }) b8 r, k. J5 { WinAutoRouteU WinCapture WinCaptureCIS WinDesignLab WinDevEqu \% Y1 p3 y: u: C- g7 Q: x
WinEditRouteU WinExpress WinExpressPlus WinLayout WinLayoutEE \
# s: f; _# c' E. S! \0 G1 p0 U WinLayoutPlus WinMACHfiveVP WinMicroSim WinMinc": I! l5 ?/ t- g6 V
PACKAGE EFA-CDS-10 cdslmd 2019.12 D0303001C3A577CFA14E \
+ f9 L( B0 l4 M0 h COMPONENTS="WinOptimizer WinOrCAD WinParts WinPCBoards WinPLD \) C; o1 g1 X1 j% c
WinPLSyn WinPLSynPart WinProbe WinPSpice WinPSpiceAD WinStmEd \3 \4 I q( x. u& h& q/ }
WinXilinx"
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INCREMENT EFA-CDS-01 cdslmd 2019.12 23-dec-2019 uncounted AD8107572717EEA50D97 "" ANY
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INCREMENT EFA-CDS-04 cdslmd 2019.12 23-dec-2019 uncounted BDB107572A17EEA52094 "" ANY
1 ?0 O& d* Z. b$ s0 {INCREMENT EFA-CDS-05 cdslmd 2019.12 23-dec-2019 uncounted BDC107572B17EEA52193 "" ANY
: d1 E$ t' }2 }, Y: U, v& lINCREMENT EFA-CDS-06 cdslmd 2019.12 23-dec-2019 uncounted BDD107572017EEA5229E "" ANY6 m& ^& n3 S. p3 e! y0 H
INCREMENT EFA-CDS-07 cdslmd 2019.12 23-dec-2019 uncounted BDE107572117EEA5239D "" ANY
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INCREMENT EFA-CDS-10 cdslmd 2019.12 23-dec-2019 uncounted AD810787261AEEA50D98 "" ANY
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4 [! X4 F0 L1 h# License generated by Team EFA 2004 Keygen
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