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General
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% x; q2 B* C. p, W. z% E Tablet, two mcu subsystems architecture/ N6 V2 O; h6 `
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( z2 T1 {+ v$ T& P# c Supports eMMC/uFS boot/ \- w+ |: j7 J- z. x5 V
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Supports LPDDR3! I2 y; p p7 Q2 u! |. ]
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5 @. ?1 u4 U" T7 B Supports LPDDR4X1 Q/ U$ `- B$ Q. g: w% t& n
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AP MCU subsystem( F0 x% T" i3 [
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* Y' M8 V' @! X6 d" B2 ^& |/ x Quad-core ARM® 2.0GHz Cortex-A73 MPCoreTM with 64KB L1 I-cache, 64KB L1 D-cache and 1MB unified L2 cache( t) }" C% r- t& M4 ?5 V, o
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3 B% R* m: t1 \/ }* c Quad-core ARM® 2.0GHz Cortex-A53 MPCoreTM with 32KB L1 I-cache, 32KB L1 D-cache and 1MB unified L2 cache
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NEON multimedia processing engine with SIMDv2/VFPv4 ISA support
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DVFS technology with adaptive operating voltage from 0.6V to 1.12V T0 w9 `+ k c: Z+ J4 f" y) ~) ?
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MD MCU subsystem
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# }7 w8 |! l! B; C. x/ F Imagination MIPS32® InterAptive processor with max. 864MHz operation frequency
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High-peRFormance multi-core and multithread processor architecture (two cores and two threads)
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32KB L1 I-cache and 32KB L1 D-cache per core9 w) T& B% N( a( _" X
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) B% q9 `; A! ?! N: r# `8 U 384KB SPRAM (Scratchpad memory, Two-Core’s ISPRAM and DSPRAM)8 ]6 L2 ?; `6 J( O; k- \ q# P
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1 z: q/ F- X/ P: e* J z5 A/ U 256KB L2 Cache (share L2 cache for two cores)& u- @" Y, z5 V
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High-performance AXI bus Interfaces5 g$ Z( e0 w9 c
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- Q5 x6 C* v- [, [ Power management for clock gating control
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FD216 DSP for running GSM modem with max. 312MHz operation frequency( P7 T3 ]( d% o; N+ T$ ?& f; U
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( k; v3 t& }3 b- HMD external interfaces
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Dual SIM/USIM interface5 s4 ?4 q/ U' U. f
Interface pins with RF and radio-related peripherals (antenna tuner, PA, etc.)
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ARM® TrustZone® Security
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External memory interface
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LPDDR3 up to 4GB (single channel with 32-bit data bus width)
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LPDDR4X up to 8GB (dual channels with 16-bit data bus width)
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Memory clock up to LPDDR3-1866 or LPDDR4X-36006 X0 Y2 v' F% @6 }
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Self-refresh/partial self-refresh mode
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& c/ f2 x! E, E( A( { Low-power operation
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Programmable slew rate for memory controller’s IO pads
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Dual rank memory device) x9 s) k! N' L4 y# y) w
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Advanced bandwidth arbitration control r0 j/ g7 z7 O/ u6 O
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Peripherals C; J2 u& v3 [
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0 P% d- ^5 X7 o+ w/ G) ~0 I USB one port with USB3.0 device mode or USB2.0 OTG mode
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eMMC5.18 }9 ]: _2 z! y1 V9 A
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uFS 2.1- ]0 l) Z# U! Q3 p+ h
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3 UART for debugging and applications
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4 @/ O2 K4 u8 v) B 6 SPI masters for external devices' O, @1 J! Q9 T& `& {8 F
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! X& k' C( o6 n+ ^# l* q- P! T 6 I2C/3 I3C to control peripheral devices, e.g. CMOS image sensor, LCM or FM receiver module% g+ p& @4 O( }
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# Z8 k, ^) i* t9 y0 d Max. 3 PWM channels (depending on system configuration/IO usage)
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0 x6 [4 ~/ i. B( P/ w I2S for connection with optional external hi-end audio codec
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GPIOs7 c, I& n3 {7 `, D. F( N$ L
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1 v9 Q8 n+ {7 }5 q% Q+ u 2 sets of memory card controllers supporting SD/SDHC/MS/MSPRO/MMC and SDIO2.0/3.0 protocols
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Operating conditions/ @5 q7 C- H6 [. i( A
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Core voltage: 0.7V/0.8V
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I/O voltage: 1.8V/2.8V/3.3V
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N" I+ Z2 U' F: G$ e Memory: 1.1V/0.6V
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LCM interface: 1.8V
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% Q$ d# R4 [* Z% ~) u: D4 |" Z Clock source: 26MHz, 32.768kHz$ \6 g) E+ T% ]& l' M
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Package
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Type: VFBGA
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1 g- [6 r, h X* Q, L& P 11.8mm*11.0mm
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z9 W/ k) x1 ]: d- d/ d# D& w Height: Max. 0.9mm0 T; s0 N4 g* B5 v- I
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Ball count: 599 balls* `. N& C4 L' [3 }
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( Z3 J2 P' @0 C( n$ L" @, l Ball pitch: 0.4mm
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2 f* g' {1 k: @! b+ Z- SLTE
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! S4 l* F/ c# _% y5 M( _; O FDD/TDD Up to 300Mbps downlink, 150Mbps uplink
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8 H; \/ z/ q+ a1 i# B2 a/ A Downlink carrier aggregation (CA) ability; 1.4 to 20MHz RF bandwidth per component carrier (CC) and up to 2 CCs; I& E( x1 y: Q
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8*2 downlink SU-MIMO per component carrier
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, L9 ^ }9 o4 A7 i Downlink MU-MIMO per component carrier# \$ ?: r, w0 Y: g; }: ]: C4 X' _
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* `% S8 [& x6 J4 i9 X Supports feICIC
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2 [6 c! v4 o/ u2 r Supports MBMS
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3 ]! Q5 `5 M: Z# M4 ?' A: m1 H Uplink CoMP ability' h: u# U3 c; R+ _% j
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9 n; z" Q0 @% }1 ~ Advanced Interference Cancellation- n& {7 `; H4 |$ a V% B; S
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/ o! H. u! N) T; a* n Transmit Atenna Selection
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& R! X* p: B; A- a. w2 v' [" @3G UMTS FDD supported features
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3G modem supports most main features in 3GPP Release 7 and Release 8
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/ n3 m$ q' {* b; z CPC (DTX in CELL_DCH, UL DRX DL DRX), HS-SCCH-less, HS-DSCH0 `/ n: ?( C5 s0 i( j! r( E. p K
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) A/ m5 r( L4 i) n Dual cell operation
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" E; @: y3 A$ w$ }2 S) m; Q MAC-ehs
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7 T( E4 { \9 Q w. {5 \ 2 DRX (receiver diversity) schemes in URA_PCH and CELL_PCH
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Uplink Cat. 7 (16QAM), throughput up to 11.5Mbps
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! k3 X B) _- X3 y/ a Downlink Cat. 24 (64QAM, dual-cell HSDPA), throughput up to 42.2Mbps
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Fast dormancy
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3 O8 N5 K5 d# q2 Z$ N ETWS) M' i A( O: {
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# c' |" |4 w ?5 _ Network selection enhancements6 p6 @& v$ S# u/ O y
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F+ S' X& d: ^. M% ~ Transmit Atenna Selection
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/ t3 _6 [% o3 V- X8 k- OTD-SCDMA
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CDMA/HSDPA/HSUPA baseband
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TD-SCDMA Bands 34, 39 & 40 and Quad band GSM/EDGE
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Circuit-switched voice and data; packet switched data
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384/384Kbps class in UL/DL for TD SCDMA( |4 u' D' g3 c E4 |4 ?
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TD-HSDPA: 2.8Mbps DL (Cat.14)
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TD-HSUPA: 2.2Mbps UL (Cat.6)6 C4 x9 X$ Z/ W& w3 d
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F8/F9 ciphering/integrity protection8 O- _: s$ d% s* V, w1 R
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* k( \: G# W7 q7 l# a Transmit Atenna Selection
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Radio interface and baseband front end
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5 Z7 z% n/ V1 I& \ High dynamic range delta-sigma ADC converts the downlink analog I and Q signals to digital baseband.5 @1 R4 N6 z- L7 H* R9 i$ @
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10-bit D/A converter for Automatic Power Control (APC)2 P R! H) }0 ^0 |* Y
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9 D* L+ I/ |" `( q# Z" p- F6 s Programmable radio Rx filter with adaptive gain control
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2 X p- m6 M2 O4 {! ]8 N9 E Dedicated Rx filter for FB acquisition
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Baseband Parallel Interface (BPI) with programmable driving strength* f7 c5 c- ^; P8 G' _) h6 e
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) X8 c' f3 a) i6 R4 g% D$ ^ Supports multi-band5 K7 B& g* U' ?$ j) w
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; r7 J# u. z, X9 IGSM modem and voice CODEC
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Noise reduction
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6 D/ n% G# T- H; a# E. k# |! z* T" F Echo suppression
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Advanced side-tone oscillation reduction Y, m: B0 Z3 s1 a4 R
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- C* t' W9 x Y- s6 ^7 N" }6 I Digital side-tone generator with programmable gain N1 L2 s" m/ O' M! a6 l' o
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2 programmable acoustic compensation filters
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5 L Y! q+ i- D GSM quad vocoders for adaptive multi rate (AMR), enhanced full rate (EFR), full rate (FR) and half rate (HR)
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GSM channel coding, equalization and A5/1, A5/2 and A5/3 ciphering7 f- {0 b# |* e+ E
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/ j5 G! a! K3 M! N0 h GPRS GEA1, GEA2 and GEA3 ciphering4 ]8 @" G* X8 \! }5 G
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Programmable GSM/GPRS/EDGE modem. P: `# R. ^' {& u5 m
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9 r2 {0 B2 @, F8 t4 N8 B Packet switched data with CS1/CS2/CS3/CS4 coding schemes7 H% M% {# D. C3 G' h1 E
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GSM circuit switch data
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GPRS/EDGE Class 12- i1 J% a9 _% w) H6 d
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CDMA2000 modem interfaces
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Supports CDMA2000 1xRTT (releases 0) and CDMA2000 HRPD/1xEV-DO Revision 0 and A/ x0 e; K. D: f# `6 M3 y( T5 |& G. Z
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Supports maximum 1x data rates of 153.6kbps for forward and reverse links and DO data rates of 3.1Mbps for forward link and 1.8Mbps for reverse link
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Hybrid operation between 1x and HRPD
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3 u+ N% {, W8 {4 C9 ]9 a Simultaneous Hybrid Dual Receiver (SHDR) support6 {, ~6 w4 t, F4 x
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Supports 1x Diversity
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Supports SRLTE7 v; X8 S/ a% F/ C# C
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t7 N6 X7 `* U7 S; y" P! W Transmit Atenna Selection1 X; y- i* s1 N
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更多芯片参数特点，可参考MT8788规格书资料
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发表于 2019-11-27 15:28
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淘帖
支持！
反对！