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General
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) L' Z6 }0 Y- S) `7 p Tablet, two mcu subsystems architecture s6 j1 j' q/ Q: x
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Supports eMMC/uFS boot E/ M M* S0 Z8 q- @, U
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/ Y9 z. ^- M+ w' N Q3 X; [ Supports LPDDR3
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5 B$ a& A- \! d% D7 v Supports LPDDR4X8 K. U$ f0 B; D
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; M# S& O. ~7 A+ V& f+ i3 tAP MCU subsystem
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2 I% O# F/ ^# M9 B Quad-core ARM® 2.0GHz Cortex-A73 MPCoreTM with 64KB L1 I-cache, 64KB L1 D-cache and 1MB unified L2 cache& m: Y) G; Q3 P8 F& M
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Quad-core ARM® 2.0GHz Cortex-A53 MPCoreTM with 32KB L1 I-cache, 32KB L1 D-cache and 1MB unified L2 cache
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NEON multimedia processing engine with SIMDv2/VFPv4 ISA support, T( h, H( z! b
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% w+ G, }5 O0 \) ]! T DVFS technology with adaptive operating voltage from 0.6V to 1.12V1 ?6 ^! `7 M; R6 d9 |9 _" ^3 E" Y
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2 L8 W% e+ I J& sMD MCU subsystem, x. o3 |& v6 x! S
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* B9 Q1 M" A$ f Imagination MIPS32® InterAptive processor with max. 864MHz operation frequency+ e5 v' v# k! k9 g$ {/ {
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4 K% J% L$ r; ~: i" m/ t o2 t High-peRFormance multi-core and multithread processor architecture (two cores and two threads)/ d7 q- g. M# X+ J1 C5 ?3 U
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32KB L1 I-cache and 32KB L1 D-cache per core/ t0 f& p: m7 N6 n7 D; L
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384KB SPRAM (Scratchpad memory, Two-Core’s ISPRAM and DSPRAM)
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( \: }7 N& s: ?2 H* P4 f0 ] 256KB L2 Cache (share L2 cache for two cores)
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High-performance AXI bus Interfaces& i" }+ f8 a c$ }
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Power management for clock gating control' K7 _& U- f2 C2 D4 @& D* _) _% j
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* N( q! ?$ V! u* Q9 \ FD216 DSP for running GSM modem with max. 312MHz operation frequency
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MD external interfaces
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Dual SIM/USIM interface' d: N& z4 L( q+ M; e( x( F
Interface pins with RF and radio-related peripherals (antenna tuner, PA, etc.)
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Security
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( t. o5 j( j9 y0 i7 [2 o! C ARM® TrustZone® Security
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External memory interface& r/ w: b x0 L* l% S7 Y
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LPDDR3 up to 4GB (single channel with 32-bit data bus width)0 s$ A8 o5 ?1 } ^. Z
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LPDDR4X up to 8GB (dual channels with 16-bit data bus width)" G, I0 ^. o# x
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Memory clock up to LPDDR3-1866 or LPDDR4X-3600' I9 h& u& B! g3 {
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. {% h" M% B' U5 E# r8 ` Self-refresh/partial self-refresh mode) X* \0 o [. Y0 P
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P3 {' S" G2 b+ y5 ^' ~' o Low-power operation
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1 u$ L3 N3 W. P1 a Programmable slew rate for memory controller’s IO pads
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Dual rank memory device
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0 U1 f; K" N) f4 _' Y Advanced bandwidth arbitration control3 u, [+ _# x0 O" ^4 m; ]: t+ F- v5 Z
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Peripherals
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USB one port with USB3.0 device mode or USB2.0 OTG mode
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eMMC5.10 {4 J) d$ h& V. [9 J6 P3 ]* ` V
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uFS 2.1
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, x9 _! `! k- k$ l& V' @8 L 3 UART for debugging and applications+ ^( m: m) o6 A/ T
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6 SPI masters for external devices$ _4 Q/ C( p# X3 l8 z
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4 U0 Q3 I0 t9 O: p# d/ q8 h A 6 I2C/3 I3C to control peripheral devices, e.g. CMOS image sensor, LCM or FM receiver module! T8 E. J5 k' y$ t* |; a) i; X# Z
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- v; x1 M0 g/ v$ F8 k: O- x Max. 3 PWM channels (depending on system configuration/IO usage)3 f& r+ u) O) @! I5 B
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1 H' [9 t& B' [/ V5 j- m8 L I2S for connection with optional external hi-end audio codec& z5 p8 X' Z3 o+ ~4 D4 C3 X" _
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GPIOs
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2 sets of memory card controllers supporting SD/SDHC/MS/MSPRO/MMC and SDIO2.0/3.0 protocols
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% K$ q* x& m F$ p( M0 ?0 ?Operating conditions; V% z' L# q1 g
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Core voltage: 0.7V/0.8V' P; b( D6 ~( l; z* Z0 L4 j
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0 g+ Z, P6 A9 Q$ _. Q2 n# t; O I/O voltage: 1.8V/2.8V/3.3V
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Memory: 1.1V/0.6V# b9 f/ E. {0 D8 q
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LCM interface: 1.8V' a% q8 Z5 [- q- V- e4 q
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Clock source: 26MHz, 32.768kHz1 S% @ S2 \5 V. X) _5 _3 }
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Package, y. X4 A+ `- t6 F" U; b
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/ A5 \3 c, J$ a' J9 \ Type: VFBGA
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% _5 H" i1 W0 @- \' x 11.8mm*11.0mm
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( c( @' Z8 |& t5 _5 A# i Height: Max. 0.9mm
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Ball count: 599 balls7 }- H( O' j0 e
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/ B9 m7 }5 L+ F Ball pitch: 0.4mm
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9 v4 v: A, \6 G FDD/TDD Up to 300Mbps downlink, 150Mbps uplink3 o& g8 ~, q4 ~- q [& {* j
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Downlink carrier aggregation (CA) ability; 1.4 to 20MHz RF bandwidth per component carrier (CC) and up to 2 CCs# [ W; C$ a |# w6 A H8 [
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8*2 downlink SU-MIMO per component carrier
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5 }1 N8 C2 _; p1 W# A$ b) }4 o Downlink MU-MIMO per component carrier5 Z. q E3 J) C. ?0 \
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Supports feICIC
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Supports MBMS
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+ f0 s" I4 I: R$ ^+ B Uplink CoMP ability
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, C9 M; Q1 _1 D7 t+ W9 t2 R, e2 d Advanced Interference Cancellation( @$ u; W/ ?$ H, Y
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Transmit Atenna Selection/ H% z% v, S% `0 N0 h( q
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1 V* e% n7 y7 g$ n3G UMTS FDD supported features) e( U& r- T/ k% |" _
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( F# x& H1 y. E7 L2 b2 Z. e 3G modem supports most main features in 3GPP Release 7 and Release 8 u, a- r* ]8 W7 [0 X# l$ g, ~4 b1 {
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CPC (DTX in CELL_DCH, UL DRX DL DRX), HS-SCCH-less, HS-DSCH
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a% }7 h1 R+ E% \) _$ |" n Dual cell operation$ I* g2 {2 w# M& c- n) V5 W* _
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3 M6 c# c+ d# R* ]5 {8 Z MAC-ehs# e, [1 X3 t2 g( T
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, I$ C3 J7 a5 k6 a! o2 _& { 2 DRX (receiver diversity) schemes in URA_PCH and CELL_PCH; r) t7 }) Z0 x6 l! o
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/ {: ?1 \$ @4 E G) [. |/ z Uplink Cat. 7 (16QAM), throughput up to 11.5Mbps5 b: U9 [9 _' L
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Downlink Cat. 24 (64QAM, dual-cell HSDPA), throughput up to 42.2Mbps
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* O$ `: v" W* `% \8 t' { Fast dormancy8 [( ~3 w2 B+ H7 `: c, ^
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8 l( X) o/ O) Q9 l% X/ g ETWS
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4 H: u7 v' \$ Y9 T3 n' d Network selection enhancements
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5 t8 G2 i A9 U5 d. F3 Y Transmit Atenna Selection
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TD-SCDMA
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CDMA/HSDPA/HSUPA baseband$ w. R5 O- z8 p; R
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TD-SCDMA Bands 34, 39 & 40 and Quad band GSM/EDGE- Q. c* n$ w/ H& N4 J2 H
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6 V, |3 ^/ v* C2 v. D Circuit-switched voice and data; packet switched data
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! W/ O# z# @: H6 G0 G 384/384Kbps class in UL/DL for TD SCDMA2 I& k m+ v+ u! k- J' e
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$ V0 O/ w6 h, a% H8 _ TD-HSDPA: 2.8Mbps DL (Cat.14)" B3 W9 F3 ?" L3 |! I- G* Q/ o' m
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3 t+ C" J+ f& y% o9 @4 {# } J0 `7 }: }6 c TD-HSUPA: 2.2Mbps UL (Cat.6), h& D: K" ~' Q( H' ]6 n( L
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) {( g4 {/ c$ \& k! y' q+ t4 R F8/F9 ciphering/integrity protection' [ F# K/ x9 l
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: I5 g! n4 ], d/ l; {# z1 Q$ x! I. Y Transmit Atenna Selection+ G3 g" i) H" Y: B
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& C( T! T2 S$ CRadio interface and baseband front end
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High dynamic range delta-sigma ADC converts the downlink analog I and Q signals to digital baseband.5 M& V( C2 Z$ S0 j$ q2 R. e& {
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. u* N- M% m4 K: x' Z- k 10-bit D/A converter for Automatic Power Control (APC)
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6 u$ F% W D6 r1 ^1 C Programmable radio Rx filter with adaptive gain control8 f+ u& u l/ h8 j
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Dedicated Rx filter for FB acquisition( g, j# T9 b5 F" Q
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' _7 I5 P3 ?$ F9 W Baseband Parallel Interface (BPI) with programmable driving strength
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Supports multi-band+ R8 X# n3 Y7 l( B* U
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5 O. `" J5 m; |8 O1 Q( zGSM modem and voice CODEC
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Dial tone generation
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Noise reduction
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Echo suppression
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) ]; o/ p8 q0 L. g( w Advanced side-tone oscillation reduction
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: a- r" O7 I/ l; Y- Z, { Digital side-tone generator with programmable gain( I, M( M5 S3 h, i
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2 programmable acoustic compensation filters
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: @9 O% C( }% x6 a GSM quad vocoders for adaptive multi rate (AMR), enhanced full rate (EFR), full rate (FR) and half rate (HR)/ N! s, n! r( d; a: N0 ]5 D" m! |
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! s d* _) ~. d GSM channel coding, equalization and A5/1, A5/2 and A5/3 ciphering
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& s" q9 F. O* _' V$ Z" n& E GPRS GEA1, GEA2 and GEA3 ciphering
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Programmable GSM/GPRS/EDGE modem
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Packet switched data with CS1/CS2/CS3/CS4 coding schemes
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GSM circuit switch data3 {* r% r! ]9 d, \9 F
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0 |4 k# c- F6 a/ O GPRS/EDGE Class 12
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CDMA2000 modem interfaces
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, p6 \# _. B( k; ~: S! W Supports CDMA2000 1xRTT (releases 0) and CDMA2000 HRPD/1xEV-DO Revision 0 and A" S6 g; S& M5 t7 p: u
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2 q# a( W* O/ c# A$ X# t: N4 U. ` Supports maximum 1x data rates of 153.6kbps for forward and reverse links and DO data rates of 3.1Mbps for forward link and 1.8Mbps for reverse link
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Hybrid operation between 1x and HRPD
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/ ^! K. s* y& \3 [0 m5 ] Simultaneous Hybrid Dual Receiver (SHDR) support1 g* V% j2 D! ]( [7 J& I
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2 x, m7 C5 @7 ?, m0 M Supports 1x Diversity
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Supports SRLTE3 ?8 w/ p8 R; W) z; P
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Transmit Atenna Selection6 L% J6 z% L; R Y: b" \3 A
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, p2 w, [, c- ~* d更多芯片参数特点，可参考MT8788规格书资料* P3 k# S5 k: a! q" p
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发表于 2019-11-27 15:28
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淘帖
支持！
反对！