JZ4775芯片参数详细说明，快看过来

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JZ4775是一款针对平板电脑、电子书、移动数字电视等多媒体丰富移动设备的移动应用处理器。该SOC引入了一种创新的架构，既满足了移动多媒体设备对高性能移动计算和高质量视频解码的要求。JZ4775提供高速CPU计算能力和流畅的720p视频重放。

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CPU
$ ?6 z2 W& A8 T9 P2 i5 k) v0 ] XBurst® CPU
+ h. z( h8 C4 N, l6 @* E– XBurst®
, t* v1 b* z9 c RISC instruction set
! ]9 t1 n  P& l& d# E– XBurst® SIMD instruction set
– XBurst®
FPU instruction set supporting both single and double floating point format which are IEEE754 compatible
0 B+ H  U: F, `6 n– XBurst®
& }. S4 }# E/ w) u 9-stage pipeline micro-architecture, the maximum frequency is 1G

! T& m; j, x' c$ i% @# ^& ]- A( [3 [MMU
– 32-entry joint-TLB
– 4 entry Instruction TLB
5 d7 V7 |# p6 B/ i3 F2 a0 w3 N– 4 entry data TLB
* _* z7 x. U1 P3 S7 u
L1 Cache
( C: f) J/ @4 h2 q& V– 16kB instruction cache
1 m# `) N& B0 k1 k: O  Y7 t– 16kB data cache

9 H8 k: w9 v" a! eHardware debug support
16kB tight coupled memory

1 I1 J1 `* O' g0 A+ u' _# EL2 Cache
# ^  C$ i$ b, G$ X( p& @- n# l– 256kB unify cache
2 A; z* i+ ~. O- u$ x: B
$ f" f* M* `0 p9 Y' f# }! ^8 y1 ]VPU
- S; {5 I9 ^, ~' R0 L MPEG-1/2 decoding up to 720P 30fps
 VC-1 decoding up to 720P 30fps
 H.264 decoding up to 720P 30fps
  ?: `/ E* ~' D! t0 e5 ~ VP8 decoding up to 720P 30fps
 MPEG-4 decoding up to 720P 30fps
 RV9 decoding up to 720P 30fps

GPU
 X2D
– Location: AHB bus
  B# k! |- @6 _; `– Input format
# w8 |2 h, D: Z; I% j Separate frame: YUV /YCbCr (4:2:0)
 Packaged data: RGB888, RGB565, RGB555, NV12, NV21,TileYUV
– Output data format
 ARGB888，XRGB888, RGB555, RGB565
– Color convention coefficient: configurable (CSC enable)
4 r/ G  b" {# A9 B– Minimum input image size (pixel): 4x4
* d' q/ e# w4 N: n& p1 s" M1 G– Maximum input image size (pixel): 12288x12288 (12k x 12k )
– Maximum output image size (pixel)
  M. d, w) ^. u0 \' u Width : up to 12288
 Height: up to 12288
– Image resizing
6 O1 `3 R* p  @8 H" o bi-cube zooming mode
, ^  h3 T$ a7 d& b– Image Clockwise 90, 180, 270 rotation
– Image horizontal and vertical mirror , same time with rotation
– 5 layers OSD

& Q, O5 V2 B1 e. zDisplay/Camera/Audio
 LCD controller(compress must with IPU direct display )
– Basic Features
 Support panel(TFT, SLCD)
 Display size up to 1280*720@60Hz(BPP24)
– Colors Supports
' l3 V9 V3 F" r/ D1 \! r7 Z' v Encoded pixel data of 16, 18 or 24 BPP in TFT mode
 Support up to 16,777,216 (16M) colors in TFT mode
1 t! }3 b8 V5 x3 S Support 24 BPP packed data
6 j! ^, ~# z0 M3 e3 ~$ {6 j) s
– Panel Supports
 Support 16-bit parallel TFT panel
  R" i9 `; L7 F. M9 v( x, @ Support 18-bit parallel TFT panel
 Support 24-bit serial TFT panel with 8 data output pins
" w- d' m0 l, x6 P' L Support 24-bit parallel TFT panel
, d/ G  n/ W4 K- r; d Support Delta RGB panel
 Support SLCD panel
% }2 ~- t/ N' C- c0 w
% m$ h, ], ~1 }  K* N( [% d  – OSD Supports
4 O& W! t* n9 {! }; K3 j2 m2 m* w8 E Supports one single color background
- G& H! `4 z0 v, L5 j  Y Supports two foregrounds, and every size can be set for each foreground
& }$ y1 d4 E4 E& p/ e& {; I8 `2 f; U Supports one transparency for the whole graphic
 Supports one transparency for each pixel in one graphic
 Supports color key and mask color key
2 J, W5 i2 }3 G, ~' c" ?6 a Supports porter-duff blending

! v' ^" N% J# A- r) o3 `1 yEPD Controller
– Supports multiple types of compatible EPD panels
! I/ {, Y- d3 ~" [; Y– Supports different size up to 4096x4096@20Hz
– Supports 2/3/4 bits grayscale and color display
– Pixel base updating
/ M" l4 C& q% X8 A+ g9 R( P2 {; V– Supports hand-writing mode
– Supports SW LUT algorithm
– Supports AUTO-DU, AUTO-GC4 mode

EPD Color Engine
6 e3 {4 p, W% t/ X8 n+ l: I) f/ O– Input data format is RGB565
  ~1 m/ B2 h$ O7 e; d2 R" C$ A– Maximum image direction is 4096x4096
( d+ H1 d) x9 l* ~. L# x– Includes CSC between RGB888 and YUV444
– CSC supports 601 or 709, Wide or Narrow mode
+ _4 |' J! [3 w* n5 m' D: h– Includes 3x3 Color Filter modules for RGB.R, RGB.B, RGB.B and YUV.Y.
, B4 ]& s6 \  D4 y$ c( k– Includes Color Linearization(VEE) for YUV.Y using 256-grade LUT
– Supports Color Correction(HUE) for YUV.UV, and the coefficients are configurable
! E+ G- k+ J2 f) [$ K– Supports Color Saturation for YUV.UV, and the coefficients are configurable
- Y2 b. _& m- e& G: W# q– Supports Dither for RGB.R, RGB.B, RGB.B and YUV.Y. The output format is 2/3/4-bit configurable.
– Supports Color Remapping for RGB.R, RGB.B, RGB.B and YUV.Y. If for RGB, there are two methods can be selected between individual CFA component and pixel array. And, the output order is configurable.
– The EPDCE has a AXI master inteRFace and a AHB slave interface.
% j1 u! {! \6 {
3 s: Q8 }$ R2 a% x7 V/ WCamera interface module
# x* @7 f! T+ D, T; S– Input image size up to 2048x2048 pixels
– Max. VGA for image preview
– Max. VGA for video record
% I* R. W9 A$ p' }1 M: k– Integrated DMA
1 x& l5 _3 q7 D' c* O; [/ R– Supported data format: YCbCr 4:4:4, YCbCr 4:2:2 and other formats

– Output format
 csc mode: YCbCr 4:2:2 or YCbCr 4:2:0
 bypass mode: the input data format
– Output frame format
 Packaged : for all data format
# h. [" U! }/ d% e Separated: for YCbCr 4:4:4, YCbCr 4:2:2 and YCbCr 4:2:0
– Supports ITU656 (YCbCr 4:2:2) input
" Z2 ^0 w  b3 q' t7 n9 V6 C– Configurable CIM_VSYNC and CIM_HSYNC signals: active high/low
! k# {" H7 s9 d& c1 A& t– Configurable CIM_PCLK: active edge rising/falling
) n8 @+ e/ c0 @" @6 A; k8 j) t( l" j– 256x33 image data receive FIFO (RXFIFO)
– PCLK max. 80MHz
– Configurable output order
9 ~. E7 w/ V! u
AC97/I2S/SPDIF controller
1 _9 ]% v$ o% S% j# l; N- d– AC-link (AC97) features
$ s4 [2 Y( `  h7 e! \, o0 j) W Up to 20 bit audio sample data sizes supported
0 t! Q# Q; C5 \8 _& O8 D4 q DMA transfer mode supported
- _& {! ]2 T& s! [" x: o Stop serial clock supported
 Programmable Interrupt function supported
 Support mono PCM data to stereo PCM data expansion on audio play back
& K9 d* ?: c: Z& S0 z Support endian switch on 16-bits normal audio samples play back
 Support variable sample rate in AC-link format
 Multiple channel output and double rated supported for AC-link format
2 V1 e/ D( f0 K6 A5 z Power Down Mode and two Wake-Up modes Supported for AC-link format
– I2S features
; E$ h" P& r3 @5 D7 X3 V 8, 16, 18, 20 and 24 bit audio sample data sizes supported, 16 bits packed sample data is supported
8 O: y5 l9 P# M9 ~ DMA transfer mode supported
 Stop serial clock supported
- z7 P0 Q4 X# _  v7 ~7 Y' I Programmable Interrupt function supported
$ d, |5 _( G8 A( W Support mono PCM data to stereo PCM data expansion on audio play back
 Support endian switch on 16-bits normal audio samples play back
  Y7 F6 G( D2 o, g5 a0 t6 s5 e1 D Internal programmable or external serial clock and optional system clock supported for I2S or MSB-Justified format
 Internal I2S CODEC supported
 Two FIFOs for transmit and receive respectively
6 }" Y$ {0 Z3 Q0 }6 g) Z$ o8 H SPDIF features
2 r8 l& W' Y# U1 {) U2 b! @ 8, 16, 18, 20 and 24 bit audio sample data sizes supported
- \# @7 G, M% H: \- L9 v0 x DMA transfer mode supported
# t$ Y  Q7 p0 i  \: v Stop serial clock supported
7 ?& V0 G* M7 A) _$ v, Z Programmable Interrupt function supported
 Support IEC60958 two-channel PCM audio
" p' g- g! E# b Support IEC61937 multi-channel compressed audio
 Support consumer mode and only support transmitter mode
( S$ h# \9 j0 _; x) Z' t. n/ n5 i
4 F0 Q7 [6 W9 n9 A5 L" i  ~# C  xPCM interface
7 N; m) U5 x7 E% c– Data starts with the frame PCMSYN or one PCMCLK later
& M) I3 _2 P; U* O6 H– Support three modes of operation for PCM
 Short frame sync mode
) G% i, ?' Q7 J. N3 M8 t' p Long frame sync mode
 Multi-slot mode
" W5 l5 `+ w( n' b& `2 T& }– Data is transferred and received with the MSB first
  r- U: M+ j" |) _% Q4 S– Support master mode and slave mode
5 E" f' J3 p7 ^2 Q- p. D9 g– The PCM serial output data, PCMDOUT, is clocked out using the rising edge of the
PCMSCLK
– The PCM serial input data, PCMDIN, is clocked in on the falling edge of the PCMSCLK
( @/ G) w( Q, g– 8/16 bit sample data sizes supported
) K; D4 ~$ m  O+ V, L8 `– DMA transfer mode supported
% {' U9 n$ n* v0 I, n* z, e2 Z' D- q– Two FIFOs for transmit and receive respectively with 16 samples capacity in every direction
! ]' s0 l" G- T2 P0 `
, N8 U6 B6 ^$ {5 d1 Z. \  ?! k+ `Internal CODEC Interface
– 24 bits ADC and DAC
4 y/ u8 u7 z4 E. _( b5 B3 A– Headphone load up to 16 Ohm
– Sample frequency supported: 8k, 11.025k, 12k, 16k, 22.05k, 24k, 32k, 44.1k, 48k, and96k
– Stereo line input
$ G: a. ^1 ~9 Q% L– DAC to HP path: Power consumption: 17.6mW, SNR: 95dB, THD: -65dB @17.6mW /16Ohm
* l; E% d7 _$ S5 e  H– DAC to stereo line output path @10kOhm: SNR: 95dB A-Weighted, THD: -80dB @FS-1dB
- Z4 i! q3 k$ _4 ^1 X– Line input to ADC path: SNR: 95dB A-Weighted, THD: -80dB @FS-1dB
  p9 E3 d5 g3 O& o# Y6 p, d– Separate power-down modes for ADC and DAC path with several shutdown modes
& d) S. a1 X! Y  N5 u' P5 m– Reduction of audible glitches systems: Pop Reduction system, Soft Mute mode
– Output short circuit protection
$ Z# t4 e! _/ r+ ]9 O– Digital MIC supported.
– Support Capacitor-coupled and Capacitor-less mode headphone connection
5 o) z) H" S8 x) r8 i– Advance SNR of recode.
6 [+ L5 _* g( Q3 l* j' N- X; D! ^– Updata AGC system.
  [: D  |: {! @/ n' n4 A# w– Add digital amplitude limiter use for remove the short when sound is very largely.
– Add DAC digital amplifier the gain up to 32dB
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: o* r1 ~3 B1 I7 fMemory Interface
 DDR Controller
– Support DDR2, DDR3, DDR3L, mobile DDR (LPDDR), memory，up to 800Mbps

# K6 Q. }8 L* o8 Y! B% L* J2 m/ f8 r– Support x16 and x32 external DDR data width
– Asynchornize to system bus and each port.
– Support clock-stop mode
– Support auto-refresh and self-refresh
% l4 Q* h, O" j– Support power-down mode and deep-power-down mode
! v- v7 X: ~: `( q: |' f– Programmable DDR timing parameters
; z& A" g  f; U3 R1 S3 t( z6 B6 X– Programmable DDR row and column address width and order

0 U2 P( U" x4 W& s8 oStatic memory interface
– Support 3 external chip selection CS3~1#. Each bank can be configured separately
– The size and base address of static memory banks are programmable
, d% Q" `( c& m+ T# Q– Direct interface to 8/16-bit bus width external memory interface devices or external static memory to each bank. Read/Write strobe setup time and hold time periods can be programmed and inserted in an access cycle to enable connection to low-speed memory
– Wait insertion by WAIT pin
– Automatic wait cycle insertion to prevent data bus collisions in case of consecutive memory accesses to different banks, or a read access followed by a write access to the same bank

NAND flash interface
* [3 P% a! r3 f" x– Support on CS3~CS1#, sharing with static memory bank3~bank1
– Support both of conventional NAND flash memory and Toggle NAND flash memory
– Support most types of NAND flashes, 8/16-bit data access, 512B/2KB/4KB/8KB/16KB page size. For 512B page size, 3 and 4 address cycles are supported. For 2KB/4KB/8KB/16KB page size, 4 and 5 address cycles are supported
4 w1 p$ ]) V0 r5 Y– Support read/erase/program NAND flash memory
8 p, V: t4 ?" o/ L– Support boot from NAND flash
( ]- Z) w3 C! O; [' Q% k
BCH Controller
– Support up to 64-bit ECC encoding and decoding for NAND

" w2 O5 q1 ^/ n  pThe XBurst®processor system supports little endian only

System Functions
/ I- t- p  X6 a9 o0 r Clock generation and power management
+ I+ w( c/ Y7 c5 }– On-chip 24/26MHZ oscillator circuit
– On-chip 32.768KHZ oscillator circuit
– One two-chip phase-locked loops (PLL) with programmable multiplier
– CCLK, HHCLK, H2CLK, PCLK, H0CLK, DDR_CLK, VPU_CLK frequency can be changed separately for software by setting registers
5 O9 \  R. [$ p) H; R7 Y– SSI clock supports 50M clock
– MSC clock supports 100M clock
9 a( [4 Y; ]1 X0 P9 V– Functional-unit clock gating
4 |, Q) P" p/ p( R" j" `9 O2 u– Shut down power supply for J1, VPU, L2CC, X2D

$ k* t8 f- e! M! [4 \8 `5 |- dTimer and counter unit with PWM output and/or input edge counter
9 g6 Y! H4 A  n7 ^/ S" n8 d– Provide eight channels, four channels 0~3 can generate PWM, two of them have input signal transition edge counter
& F4 C( A, S8 k" }7 o$ z4 l$ D– 16-bit A counter and 16-bit B counter with auto-reload function every channel
– Support interrupt generation when the A counter underflows
$ \' b6 K9 y* W: }$ b% W– Three clock sources: RTCLK (real time clock), EXCLK (external clock input), PCLK (APB Bus clock) selected with 1, 4, 16, 64, 256 and 1024 clock dividing selected
' ^2 j# y! b$ M& v6 K% G/ n– Every channel has PWM output
& \% E* s2 c* C- d
- _& K6 Y4 }; f1 kOS timer
– One channel
+ e: u) O+ _6 B, `" V– 32-bit counter and 32-bit compare register
* |+ w0 X: [6 P5 @+ \# M5 H" h– Support interrupt generation when the counter matches the compare register
1 _# M+ R& F" }5 O2 v. ]– Three clock sources: RTCLK (real time clock), EXCLK (external clock input), PCLK (APB Bus clock) selected with 1, 4, 16, 64, 256 and 1024 clock dividing selected

. u6 G0 D. ^6 e- ?: p9 }% B6 ^+ V5 yInterrupt controller
/ g6 [  o- ?7 ^8 A8 `– Total 64 interrupt sources
& W; l6 Q, [& _– Each interrupt source can be independently enabled
9 Y, C( C4 Z# P: w& L– Priority mechanism to indicate highest priority interrupt
– All the registers are accessed by CPU
2 v/ e% V) U* S& T2 Y; @– Unmasked interrupts can wake up the chip in sleep mode
– Another set of source, mask and pending registers to serve for PDMA
" V4 x7 d# C, L; U# d
: [+ W! X: ~; w1 h4 BWatchdog timer
+ W9 D/ o! U& C& n8 J– Generates WDT reset
5 ]4 _' g5 `" r8 x8 w– A 16-bit Data register and a 16-bit counter
% [! s: l! c3 i  Q+ ?  ^: m4 u– Counter clock uses the input clock selected by software
! c, j& K# e$ N# K/ j( X% L" O PCLK, EXTAL and RTCCLK can be used as the clock for counter
 The division ratio of the clock can be set to 1, 4, 16, 64, 256 and 1024 by software

9 n) \7 B5 t6 M8 `- f& uPDMA Controller
' U2 W2 m' z! V+ C* i( e! c% G– Support up to 32 independent DMA channels
) `. H! ~" ?% @0 Z  l$ A– Descriptor or No-Descriptor Transfer mode compatible with previous JZ SOC
! M5 V2 n. h3 e$ e) b4 h– A simple Xburst®
8 M% W# J3 ^6 h( F-1 CPU supports smart transfer mode controlled by programmable
firmware
– Transfer data units: 1-byte, 2-byte, 4-byte, 16-byte, 32-byte, 64-byte, 128-byte
– Transfer number of data unit: 1 ~ 224 - 1
2 c% g) ~: O- C, N) [– Independent source and destination port width: 8-bit, 16-bit, 32-bit
& r/ i! e& `+ V& t: z* n– Fixed three priorities of channel groups: 0~3, highest; 4~11: mid; 12~31: lowest
– A dedicated bus interface - BIF interconnects with on-chip BCH
– A dedicated bus interface - NIF interconnects with on-chip NEMC or off-chip NEMC.
– An extra INTC IRQ can be bound to one programmable DMA channel

SAR A/D Controller
( p- I6 c7 M9 t/ t– 7 Channels
  K/ W( `; l" Z" {( ^9 }– Resolution: 12-bit
– Integral nonlinearity: ±1 LSB
( @' z* |* c) H& p8 Z$ R6 u– Differential nonlinearity: ±0.5 LSB
– Resolution/speed: up to 2Msps

$ {) A" N$ ~5 z' x更多信息可参考“JZ4775 Datasheet”
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