|
|
EDA365欢迎您登录！
您需要 登录 才可以下载或查看，没有帐号？注册
x
R11代表了Allwinner在智能硬件处理器上的最新成就，它集成了一个以1.2GHz的速度工作的单ARM CortexTM-A7 CPU，并支持多个外围设备。
( Q' W! }- k% t" t/ k7 X6 L" f1 P7 d( L0 H3 k$ |4 ^; ?0 U; P
: r' X& e& R1 Q7 D
CPU g$ I3 F( O2 N
( Q I0 ^* S- r8 x( U) j
5 _& \2 `: g! Y p6 s h
ARM CortexTM-A7 MP1 Processor 6 I+ b9 [3 {7 ~0 v& W1 ^
Thumb-2 Technology
g. b% Y6 h p# K0 YSupports NEON Advanced SIMD(Single Instruction Multiple Data) instruction for acceleration of media and signal processing functions
: @8 k3 X" R( o6 v/ c5 Z H0 f- ?Supports Large Physical Address Extensions(LPAE)
) ]9 C! ?. @+ L7 I; JVFPv4 Floating Point Unit 8 x8 F$ u. @8 N l3 X5 z( b% |
32KB L1 Instruction cache and 32KB L1 Data cache
2 Q& }! s( P6 j0 E: A128KB L2 cache
' ?# p) L. r2 J/ H! l
; f7 G; }' d, }5 q! r
# d% G( [5 }- F9 lMemory Subsystem & [. \) B! j7 G2 k9 m2 w
Boot ROM
7 ~; W! q! t A) ~* H1 L; ?* \9 Z9 S& ^1 l) f
: d5 x* y6 r5 B4 O
Internal on-chip memory ) O! n5 P- H' M! X4 C4 R2 x7 E1 \
Supports system boot from the following devices:
5 ]- _) O" ], a3 L9 ^% u9 R; a- SPI Nor flash 9 l- |6 x) f$ p z N/ \) u; \
- SPI Nand flash 4 }1 B# _9 c/ t* x
- SD/TF card
; `' ?, P- x5 O* K- eMMC
) n( J4 _$ G$ nSupports system code download through USB OTG
/ o8 F2 ?7 {) ~% ~* h
4 U% r; J% g6 @% T6 g# H; y. V% L4 \. A4 l' F: L) X* J
SDRAM0 ], r. q+ \* E0 a9 ?- Z: H
5 U/ m9 _* Q( Q8 L/ j: z2 l& c" A1 ]5 O
Internal on-chip memory
$ U& ^1 @& z) ~2 u! b$ cBuilt-in DDR2 in the R11 ; M' j" v! z6 X" u" `$ e4 F$ B# W9 ]
Clock frequency up to 400MHz ! G" S+ c( K" e' h' O6 H: t2 g
Supports Memory Dynamic Frequency Scale(MDFS)
" v3 Y0 U* n! x0 G1 G1 y- |- Y+ Q" J* `
0 P$ u- ^# n2 v( X, W3 MSD/MMC! t" u/ S* I2 Y7 _4 H8 E x
5 f- a' [; b) T# x( X1 y F2 Y: I- M( b j. j
External off-chip memory and storage device
' j9 W8 }- a- P9 R* x. RTwo SD/MMC controllers 7 A) w: z- e9 _
1/4-bit data bus 7 ~3 s3 o9 m* M" F1 h' E
Complies with eMMC standard specification V4.41, SD physical layer specification V2.0, SDIO card specification, f6 o- r* s# r: |9 I5 I5 r
% U, {7 h( J( t- {+ R% l2 r; U% R/ K! m( N* @' }7 x( X
Supports hardware CRC generation and error detection
5 N) `$ W7 q j+ q' K8 l) tBlock size from 1 to 65535 bytes
M( f x" C h3 u9 O# t* Q! ~: k% H* R
2 G, Z* _8 u% c* j: K" nSystem Peripheral W7 {) m7 ^" {: N6 b( h
Timer- U( o1 y2 J& G/ w
+ s& A/ p' t8 L
* I& G1 N( u# q1 R! sThree on-chip timers with interrupt-based operation 0 M5 f- C% n' t5 H5 `6 q# n
One watchdog to generate reset signal or interrupt
: q% ~5 S5 Q' j, o" g33 bits Audio/Video Sync(AVS) Counter 8 p/ @1 ?; D2 ]; J) @" e% b
24MHz or internal OSC clock input
7 p& N+ o r# t' y) g
2 Y* r+ T# E. C- `3 X) Y" v1 y K
, W6 K. \+ ^8 ]9 t- k7 C1 Z: D( BHigh Speed Timer
* J; o1 r, c" l! _* |' M; h) M& j: r Q8 k8 ]' p0 X
9 v# q0 W8 v& b u' e- iUp to two high speed timers 2 N) g- P5 n& `
Counters up to 56 bits
$ }& U" i/ i9 r9 F( lClock source is synchronized with AHB1 clock, much more accurate than other timers
5 r" p- U4 p, E5 I2 i( C. y+ Y: A n* w @
, G7 ]( l- }; ^- o
GIC$ w( r4 {/ t" |/ Y) s! @5 n1 v
* ~ D0 [% Q" _
- c' K" B) v4 ~$ R' D: TSupports 16 Software Generated Interrupts(SGIs), 16 Private Peripheral Interrupts(PPIs) and 125 Shared Peripheral & _) I/ y6 ~7 ]; \0 _% a4 i! R
Interrupts(SPIs)$ o1 s" k3 m8 c2 [" C- Z2 |, U) ^
$ s! Q2 G1 h2 ?4 p! N* e" W* f; [0 w2 |: H% }- X* e
DMA
+ W- Z& o+ ~: ?8 E0 d8 _0 B( Q
+ M. `7 F" l# G
# a( ^2 M3 ^$ ]Up to 8-channel DMA
+ V% Q: D+ i" \2 E: }4 oFlexible data width of 8/16/32 bits
6 }* Z9 f) N7 q6 R% hSupports linear and IO address modes * N2 v# ?) u2 ^0 j+ k; H% F4 ~* M
Supports data transfer types with memory-to-memory, memory-to-peripheral, peripheral-to-memory
; \8 Z/ Q, Z- ~( ~
* v8 S. j4 ~: s/ Z9 f8 W+ ?5 F7 v
}7 L. f( c- E0 T& s0 qCCU: i& d) ~! j8 @
: |) u8 o& _$ n& y+ M% N
' w) o1 `1 m2 W& W% z% w4 U9 PLLs
6 M9 v, T' V# t2 J' HOne on-chip RC oscillator % R+ \. \1 C8 Q* N( r
One 24MHz external oscillator x0 q2 \; K- s- c! j
One 32.768kHz external oscillator
5 r3 U( r: ^4 ]( V4 M. L* Q% V6 DClock management: clock gating ,clock enabling to the device modules, clock reset, clock generation, clock division: D# \: O i* o7 q+ Y
+ N4 S( S/ K7 v0 K( B! L5 Q
( g% Z; F) \5 zPWM
0 C: b a9 x/ p3 P- g: h O
0 J) ?: K8 C( F6 R) v$ ~( [2 C3 \! Y) g: O" r0 h$ S+ C$ T
Two PWM channels
& \9 V! @5 ]) t/ k0 m6 ZSupports outputting two kinds of waveform: continuous waveform and pulse waveform
+ r# N3 J3 n5 z# T2 [# M0% to 100% adjustable duty cycle
; K/ R. \7 e0 r) |( J1 HUp to 24MHz output frequency
' V: D$ c% Y& Y* k `0 g& a! ]# T/ f' P! o) g5 [; B" ]
' g r! Q4 F& m6 h& O! @RTC. |0 H# I5 y( k
6 ~( C# X+ w) K& m0 y+ l& o( l
W H+ a7 L9 NTime,calendar
) z( E% M, m+ Y# `: ]Counters second,minutes,hours,day,week,month and year with leap year generator
, A+ }- k& n; P# E! K1 c' |& Y$ jAlarm:general alarm and weekly alarm( Z' p$ z6 Q: L
! Q# B$ S) ]1 h9 `3 l* L
- q& ?& X2 w% o1 S3 qLRADC
% x* D, {6 k4 h) N9 {" E) p* g( D0 s. @# |, ?2 O# @% Q
Q* P% ~) M5 y- c0 x6-bit resolution
$ j; m) M, A1 B7 g! T8 b8 P3 iSupports hold key and continuous key
9 g H- |2 D K' f( KSupports single key, normal key and continuous key: n' J7 ^$ @4 l1 L" d0 A- b
0 j7 R8 i( G7 |7 @# Q3 ]
8 W; e$ z1 L* a- RCrypto Engine' v& d9 f/ k: t
0 \- g/ p0 |- }& K- m3 E
; R1 p2 j3 O8 x ~
Supports AES 128/192/256-bit with ECB,CBC,CTS,CTR mode 8 O8 l$ s& {# e) ?
Supports DES/TDES with ECB,CBC,CTR mode
4 }- s0 H6 [$ Q, _) ?Supports SHA1 and MD5
0 s! u! u# ?. Y, J160-bit hardware PRNG with 175-bit seed- H4 K: S. S- r- N; N( x
; O6 h4 f( P% W0 s% N* W7 F+ Y' J0 w
; R3 G9 S- E& i& l$ `
Display Subsystem ! y' O6 `0 |- W, U, T% R& j
DE2.0
! J3 I% M9 j$ K+ m) y% c0 n3 O) p3 Z, K9 U
4 D2 F) O# N. ?# G# Y2 D
Output size up to 1024x1024
! J% ?% m" W: W& [Supports three alpha blending channel for main display 0 m k8 w" Q2 p; U4 {0 x
Supports four overlay layers in each channel, and has a independent scale
- x& F; r" d# h2 j2 WSupports potter-duff compatible blending operation
: V$ u1 U# w6 h# j2 q) b0 U& O' z# dSupports input format YUV422/YUV420/YUV411/ARGB8888/XRGB8888/RGB888/ARGB4444/ARGB1555/RGB565; p$ ~% d, n$ `! M+ u
* x2 B: {+ a$ D1 V
' f; M5 Q8 P! j$ k8 RDisplay Output
( M" F/ K) W% u1 w' B: s
- k# Y% K$ u# ^3 _! d5 G% p( {- H( [
Supports LVDS inteRFace with single link, up to 1024x768@60fps 3 s1 V' B( @) i3 d; O
Supports RGB interface with DE/SYNC mode, up to 1024x768@60fps
4 ^( P! I7 `0 C9 E5 k2 JSupports serial RGB/dummy RGB/CCIR656 interface, up to 800x480@60fps 6 ?( S6 @7 c" j% t- a
Supports i80 interface with 18/16/9/8 bit, support TE, up to 800x480@60fps 9 \1 E5 J5 ~1 w/ }+ n+ L0 d
Supports pixel format: RGB888, RGB666 and RGB565
6 ?# o3 h7 E& q$ wDither function from RGB666/RGB565 to RGB888 * |1 g3 Y! K7 {1 m
Gamma correction with R/G/B channel independence0 a2 U6 E0 l% i1 S+ }% x
# w3 Q* b: l& c; T! y
7 v# d8 \( r4 WVideo Engine . \4 Q+ \/ c' v1 l- Q( k$ Q
Video Decoding
# M9 F4 R# @) t! d6 y4 p: D3 Y1 P( X, A( Z" O
3 d U/ ^6 U9 X0 m7 H2 t* BSupports video decoder for H.264 and JPEG/MJPEG
, E% l4 r6 R& L4 W9 y7 H* V" p" V$ t& XSupports H.264 BP/MP/HP up to 1080p@30fps
' F& V: }, K$ M9 ESupports H.264 output formats :NV21,NV12,YU12,YV12
0 u x% [: r* jSupports JPEG/MJPEG up to 1080p@30fps
" a e. S9 ?1 `4 L; s- e; y0 c
/ B6 ^8 P3 O( n; x
* c( Q' G) k9 d3 G7 Q+ JVideo Encoding" a3 h) J" B R2 O1 e0 y
$ L1 H9 f9 b. a" D
* m/ I6 E/ ~6 P7 a' t4 C# z8 NSupports H.264 video encoding up to 720p@60fps - h2 `/ M& d7 F3 q" [. |. T
JPEG baseline: picture size up to 8192x8192
2 ?' n, O0 K- z3 _( X9 U' V- _Supports input picture size up to 4800x4800 9 Y9 c+ w. D) v9 W! k
Supports input format: YU12/YV12/NV12/NV21/YUYV/YVYU/UYVY/VYUY $ ?: S7 ]' ?! I. Y) I; w8 l
Supports Alpha blending 0 V" [% K8 G# l+ m$ Q7 n2 l
Supports thumb generation 9 p0 d( P9 F" [1 M; M
Supports 4x2 scaling ratio: from 1/16 to 64 arbitrary non-integer ratio
: t: N2 g7 K8 ^4 k) I3 USupports rotated input2 X+ I. G) V& S' `* }2 `
6 ^+ R5 _% i8 }4 V" |
2 m8 k% M$ Q% M- L7 C l. jImage Subsystem 5 m" E: A% @2 @& L* T
Image Input
0 m! h$ d& `$ ~: X
3 G, R- a% o/ `& v$ Q8 X: M# D. ^! i# R$ b" l/ I% }
Supports 8/10-bit CMOS sensor parallel interface
1 A3 H- I8 G7 g' [4 i( {Supports 8-bit CCIR656 protocol for NTSC and PAL ! R8 D" O1 U9 d
Supports ITU-R BT 1120 protocol for HD-CIF system
* Z8 e2 Q& A" w1 \4 }Supports 16-bit interface with separate syncs ! ^7 q; Q$ Y" }' M
MIPI-CSI2 interface compliant with MIPI-DPHY v1.0 and MIPI-CSI2 v1.0 : U0 u3 G- N' c; |; r
Supports MIPI-CSI2 1/2 data lanes configuration
0 g y# R& j6 H& Y2 P$ I, fSupports Format:# h, T! S' |% N
8 @; ^( ^$ z+ U0 Z7 d. r
2 p0 s6 o, Y. U% Y9 D2 B4 F
- YUV422-8/10 bits
+ ?7 `: ~4 n- S4 j. l- YUV420-8/10 bits(for MIPI-CSI2 only)
/ x$ k( L& ^% L' S- RAW-8/10 bits
7 ~4 Q) o9 i, x n% z: V1 S+ K- RGB888/RGB565(for MIPI-CSI2 only)
% f- X+ g& x* t" d2 m" [; x
9 {' h7 N0 q2 e) B8 V% {- `9 o( S, v P. a# c x
Performance:
) |4 @3 Y- P% t# P7 i }& M4 L; ~, r, n8 [3 f
5 ]8 u, m0 z& E$ Z( _ T. z6 `+ F9 H- Still capture resolution up to 5M with parallel interface
% U; c: V* Q$ c2 T5 g" ?1 {- Video capture resolution up to 1080p@30fps with parallel interface
7 J) o! e8 T) n w% R$ v: J( ?- Still capture resolution up to 5M with MIPI-CSI2 interface 7 D$ ~& v3 ^0 @9 J$ I% d
- Video capture resolution up to 1080p@30fps with MIPI-CSI2 interface * `& J" r/ F$ S, k
- MIPI-DPHY maximum data rate up to 1Gbps per lane
9 t/ x1 `0 D% b% _5 D, a: f2 u) e) G1 |5 T& }- k% G
ISP$ F% M" ?. g/ Y" H
8 N, F0 X' O# f8 C. n
( a6 }2 s% ]& k. D
Supports input formats:8/10-bit RAW RGB,8-bit YCbCr 9 H7 l3 ~, q o B8 U
Supports output formats: YCbCr420 semi-planar,YCrCb420 semi-planar, YCbCr422 semi-planar,YCrCb422 semi-planar,YUV420 planar,YUV422 planar
$ W' A+ m& N5 F9 M; D1 F8 ]Supports image mirror flip and rotation ; Q% ]' P) ?5 y& o) ?$ A1 f
Supports two output channels
" R5 B7 j/ @! r: J& y8 x" w$ VSpeed up to 8MPixels@24fps ( L: R5 b2 S+ P; b. X
Defect pixel correction
0 r' m; \. ?. v$ b$ x4 OSuper lens shading correction
# b+ s/ \( }0 ?Anisotropic non-linear Bayer interpolation with false color suppression
* d. z) [3 A" X' ~+ C( K; KProgrammable color correction
6 q1 y( p- V0 Y: G% o5 |% l1 n; EAdvanced contrast enhance and sharping
4 k4 X: L g4 P3 n1 RAdvanced saturation adjust
2 i4 B Q; K. L DAdvanced spatial(2D) de-noise filter - q+ W$ n; a' \7 p% z
Advanced chrominance noise reduction
& y3 g) H# A. l2 {! cZone-based AE/AF/AWB statistics
' W* Z; `. n3 u- C4 WAnti-flick detection statistics
2 P! e+ j# Q o* gHistogram statistics
3 D( Z0 Q5 C+ W$ i# _+ i3 K8 i% _# ?# F) m6 X2 i* Q4 i+ f" S
" K- s" Y8 X! ^
Audio Subsystem
$ Q5 C; S! C3 n; QAudio Codec
7 R2 ]6 z8 a0 H0 B2 ]! I& u& w2 R: v! w; T8 m
1 V! e, e% S& D* O( f" y
Two audio digital-to-analog(DAC) channels
) ]( z+ @4 N: ISupports analog/digital volume control
$ u' Z" E! Y* ~; I/ ^2 B. }& h- ~One low-noise analog microphone bias output
3 M" J8 M4 j* x% @" {: F" z+ ]Analog low-power loop from microphone to headphone outputs
6 N5 G$ }9 E/ f0 v$ t) ^Supports Dynamic Range Controller adjusting the DAC playback output
& W9 _1 f) O9 s2 |$ i* ~. f6 _One Microphone input ( A5 c0 P9 M7 `6 m- z
One Stereo Lineout output
" p! g: L& L0 x% NTwo audio analog-to-digital(ADC) channels
1 |; ?1 V; ^5 k6 t
. E4 o1 n) z3 a, N* y; ?$ k% z
9 a. H) T2 d* L& r9 V- 92dB SNR@A-weight $ R1 z5 U) x! a9 `
- Supports ADC Sample Rates from 8kHz to 48kHz
4 T( T8 f1 F- }7 W2 gSupports Automatic Gain Control(AGC) and Dynamic Range Control(DRC) adjusting the ADC recording input
* ]9 k3 _( R, Y, J6 k# c5 N$ O8 A, p/ a' N0 y0 E
( g% Z/ G2 V; j$ h% l- sExternal Peripherals $ G- ~# h B! K+ T
% F; g6 s' R0 E+ Z2 ^+ L
6 y. L$ p' S. ^5 d USB
$ U, E# [& X F: B$ K0 _
+ B6 c) K. k3 K5 W5 E; i. R; w9 q/ E9 `, c# V+ ]9 O- c
One USB 2.0 OTG controller with integrated PHY
+ |/ ^, Q: O! m0 [+ V1 q( e% _+ d% TComplies with USB2.0 Specification
% s8 m2 P- F- R8 m9 i' X, KSupports High-Speed(HS,480 Mbit/s),Full-Speed(FS,12 Mbit/s),and Low-Speed(LS,1.5 Mbit/s) in host mode
0 [4 Q/ G. G+ m1 G+ MComplies with Enhanced Host Controller Interface (EHCI) Specification, Version 1.0,and the Open Host Controller
& e# y& E; D: {2 {7 {( A' K/ BInterface(OHCI) Specification,Version 1.0a for host mode / Y9 H; v% N! H
Up to 8 User-Configurable Endpoints in device mode
M6 ^ r; e: B& B* H0 f- mSupports point-to-point and point-to-multipoint transfer in both host and peripheral mode
* b5 q$ [/ J8 l$ T7 w) {; e) i( m7 l4 w" T7 @% g
: D! K4 q. y- ]/ S7 f L5 f3 c/ z/ hI2S/PCM
4 r1 Y+ U, j1 ]- C0 ?& m# D+ b" W& J/ b/ T* T' Q0 Z
( C! o9 T3 \% m9 E7 L. e; x
Compliant with standard Inter-IC sound(I2S) bus specification 3 W( E- B, v- ], \( Z
Compliant with left-justified, right-justified, PCM mode, and TDM(Time Division Multiplexing) format ]* l! s T0 J; v
Full-duplex synchronous work mode
( L. E* Q# S" ^- PMaster and slave mode configured
# J3 B% z& D) iAdjustable audio sample resolution from 8-bit to 32-bit- z- |+ I: u& u2 O4 d% w
Sample rate from 8 kHz to 192 kHz5 p0 S& L- w q
Supports 8-bit u-law and 8-bit A-law companded sample5 D4 e" d4 O( |
- @# V! O. `$ u3 d
! h& `+ g9 t, {# Y
EMAC) \9 E f: a# v; M" ]4 X6 ]
5 ?+ B* l# J% |# |( \
& s) o: l+ ]* aSupports 10/100/1000 Mbit/s data transfer rate ! I( Z' L) Q; ^; T, n0 ~
Supports RGMII/MII/RMII interface
4 f$ |$ v3 L u( lFull-duplex and half-duplex operation
8 x+ H- `' U: r" b ?/ o% {/ }) jLinked-list descriptor list structure ( K3 m5 B7 Z+ Z k8 e5 h$ c3 g z; N2 k
Programmable frame length to support Standard or Jumbo Ethernet frames with sizes up to 16 KB
2 g& \0 ?/ L3 n. `) u' m. R; ESupports a variety of flexible address filtering modes* @' x3 h Q, X) M" t% O0 _; K6 K
1 {; U5 R: z3 v! S; ?. K3 U, W1 z b3 q0 k
- ?' O# t7 e2 k& ~1 sUART
7 u: M1 G! O r+ b8 V- y8 D
2 G5 q9 B% ~5 b" ?; Y
( F6 E& I( U9 hUp to three UART controllers ) n. [: b8 c" _$ `
64-Bytes Transmit and receive data FIFOs for all UART
3 `' i$ ^& K' U9 X1 P, \Compliant with industry-standard 16550 UARTs
( q4 k2 s2 Z# J# g1 i5 \+ q" b$ A) U
2 |) g4 V0 @4 I! |9 q3 n不直接翻译了，且资料内容太多了，想要看完整的，可参考全志R11 datasheet9 A2 q0 ^; g' ~: Z+ `
4 ~1 o9 ~0 u8 M6 ?0 X: ~4 s9 O+ p0 O
$ C! h6 b: ?6 n8 t/ U! I7 ]; C/ M/ {' p# @8 t3 v7 ^# o
|
|
/1 
发表于 2019-11-25 16:38
收藏
淘帖
支持！
反对！