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Readme for SPB Release version 17.2& ]% J! L( H; {+ c& U& E2 G. L
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Copyright (c) 2019 Cadence Design Systems, Inc.
! l- L4 j5 S# a1 QAll rights reserved worldwide.$ r$ N0 s* \0 D
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. f+ r/ P+ O+ w5 k- p* s& u5 @Fixed CCRs: SPB 17.2 HF060& |- R3 H2 ]' w, ^4 f1 U" R: r
10-11-2019
$ Z7 Q3 V; S9 J/ Q D========================================================================================================================================================
. O. r1 _8 N# q& r, y4 kCCRID Product ProductLevel2 Title
" T" D4 Z3 W9 A* S8 V4 _========================================================================================================================================================1 @' k4 o4 w3 k: i& X" m$ b
2137594 ADW DBADMIN EDM is not allowing to modify step model
# c& ^- T8 @; o" z2115805 ADW DBEDITOR 'BOTH' in ALT_SYMBOLS prevents correct generation of part_table.ptf
) V4 i$ B2 r! E2135452 ADW DBEDITOR DBEditor poor performance in high latency networks# `1 C% N6 N2 S
2142315 ADW LIBDISTRIBUTI EDM Library Server stops often and adwserver.out file is extremely large, more than 1GB( Y' T6 e; r5 s; K5 l
2155396 ALLEGRO_EDITOR DATABASE Netlist error when importing from Capture CIS( m( g; V3 {. L0 o# Z) q9 E9 c3 }
2118231 ALLEGRO_EDITOR DRC_CONSTR Crash during DRC: DBDoctor exits with error 'Illegal database pointer encountered'
" ^+ p- S$ z6 J$ a% c; c1 F2150923 ALLEGRO_EDITOR DRC_CONSTR Via at SMD fit DRC not detected with rounded rectangle pads$ h2 R$ A* N; h: y+ D+ P
2140441 ALLEGRO_EDITOR EDIT_ETCH Drill hole to line DRC while sliding but 'Allow DRC' is not selected in the Options tab: C# l2 F+ u6 I, R: P/ U
2141329 ALLEGRO_EDITOR INTERFACE_DES Error message (SPMHSY-49) displayed on running 'Tools' - 'Database Check'& d2 ~1 g$ }4 |! p% S7 C
2126562 ALLEGRO_EDITOR MODULES Create Module File / Place replicate assigns incorrect netname8 o, q9 y5 S! Q, x0 Y+ o* A9 B3 b
2150410 ALLEGRO_EDITOR SCHEM_FTB netrev.lst is created in the wrong folder
$ I9 o2 n) |5 w' B1 k: l2136158 ALLEGRO_EDITOR STEP Update STEP Mapping Data Only should be seperate Menu/Command.6 d9 x5 r0 L5 R
2137801 APD VIA_STRUCTURE High speed via structure instance not adding properly
" b' v7 \5 w; R9 r2 T& `8 h P2145072 CONCEPT_HDL CORE Error on choosing 'Enable Hierarchical Variant'# D v# d' ]' n# J
2124843 PCB_LIBRARIAN CORE Prompt displayed for license choice marked to be used as default- }5 [/ x: d- U
2141656 PCB_LIBRARIAN CORE Part Developer pop-up option 'Edit' for symbols displays an error message
# s$ l3 A( v( |8 d2125794 PCB_LIBRARIAN SYMBOL_EDITOR Part Developer new Symbol Editor: cannot move inverted pins that contain circle and dot
" u+ @* s3 Z& t: e1 j$ M1 v2161864 PULSE R2PLM Second publish with CPM-derived item number and cadName set to $NUMBER causes 'an item is not unique' error5 E) A4 l+ _ l5 z( S; v
1997911 SIP_LAYOUT ORBITIO_IF Support keepout translation between OrbitIO and Allegro layout/physical editors
$ p* n l( [6 }+ z" P5 A9 M. l* ~7 [) A; E8 v) A1 y
8 P* z, a7 N/ |! M/ oFixed CCRs: SPB 17.2 HF0596 Q+ m* H! W4 d }! _* a$ L) C
09-13-2019
+ d) _7 E- A" p9 I5 _9 V5 g========================================================================================================================================================* P& e( @" o3 C9 ^# \6 f
CCRID Product ProductLevel2 Title
8 t8 A0 p1 X$ R% G( u/ w========================================================================================================================================================8 S2 F2 |) ?6 C* C0 Z3 \3 A4 @
2112454 ADW DBEDITOR Icons in DBEditor do not start applications after renaming a model
$ ?# e/ s$ @/ P% P g2120548 ADW LIBIMPORT Missing alternate footprints from vault area after library import.- k7 g% K9 x2 K3 N" _
2143314 ADW PART_BROWSER Component Browser does not start after installing HotFix 057 of release 17.2-2016( m: i# E; ^: M) m2 o% q
2122302 ALLEGRO_EDITOR ARTWORK Coverlay details not being output to Artwork data as per the visibility$ q9 o4 N3 Q( }. W
2135521 ALLEGRO_EDITOR ARTWORK Artwork dimensions do not match Allegro PCB Editor# @2 L' V( M5 n) _: U
2054584 ALLEGRO_EDITOR DATABASE Through hole mechanical pin in zone area without Soldermask Top still shows a pad on Soldermask Top1 U: X; _: C! N M. x, d7 i
2111444 ALLEGRO_EDITOR DATABASE No soldermask for mechanical holes within zone" R: Q# L2 f# \% Z/ O
2115596 ALLEGRO_EDITOR DATABASE Unused Pad Suppression removes pin connected to shape using Net_short property
, r& O* O" z& D2 ?, m b' Y2135436 ALLEGRO_EDITOR EDIT_ETCH Allegro PCB Editor crashes when routing with VOID_SAME_NET property on cline) Q9 C' W$ `: }+ ? b! L: ?- a
1825020 ALLEGRO_EDITOR INTERACTIV GUI ( Quickplace ) not adjusted to current resolution0 {6 F$ @3 f9 P4 z$ v" ?
1949705 ALLEGRO_EDITOR INTERACTIV Quickplace GUI not adjusted to lower resolution3 X" @* Z7 v( u: l- |9 {
2023090 ALLEGRO_EDITOR INTERACTIV Dialog boxes do not fit vertically on the screen5 k! [% Q9 C. F- r+ N
2109940 ALLEGRO_EDITOR INTERACTIV Quickplace pop-up window does not fit vertically on the screen
8 A+ c5 K7 X7 d8 y2 _# D2136823 ALLEGRO_EDITOR INTERACTIV Cannot resize or move dialog box to access buttons0 a" T& |5 D3 q" x/ X5 }; N
2116748 ALLEGRO_EDITOR IN_DESIGN_ANA Impedance vision data not available for cline segments for some nets
6 q* G! Y: H7 J8 i' h2138977 ALLEGRO_EDITOR IN_DESIGN_ANA Impedance check results are incorrect and Crosstalk analysis stops running after updating to HotFix 057, s6 ~7 k0 ~* Y( z; w2 o9 l7 l- X3 G
2132628 ALLEGRO_EDITOR NC Improve the User Preference description for BACKDRILL_OVERSIZE_OPTION
" d; r; c* G8 [+ e7 s2152244 ALLEGRO_EDITOR SCHEM_FTB Netrev.lst is written in the package folder
1 q% a% e5 l2 m$ k( G2152493 ALLEGRO_EDITOR SCHEM_FTB netrev.lst is not created in the correct folder - error displayed for neltist import% D6 L8 Y: S l' K% ?
2104559 ALLEGRO_EDITOR SHAPE PCB Editor crashes while performing shape operation 'andnot'
% p7 T# R3 v0 P$ \2108207 ALLEGRO_EDITOR SHAPE No Void Overlap option is not working in AMB. n. G8 X' z- k, H
2125571 ALLEGRO_EDITOR SHAPE Allegro PCB Editor crashes for a RAVEL rule
: A4 a( y; m7 D5 F) S* V! }% @3 x2140707 ALLEGRO_EDITOR SHAPE Allegro PCB Editor crashes on creating dynamic shape7 s6 H" _$ |7 ]- x* m( H/ r+ P U: {
2078434 ALLEGRO_PROD_TOOLB CORE Shield Router - cline end caps treated differently than cline-segment end caps. w( ^) Q4 p& G1 l' X
2101020 ALLEGRO_PROD_TOOLB CORE Productivity Toolbox Z-DRC with multiple net classes: script selects only the last two classes in a group, g9 b& k' b/ R5 G
2029279 CAPTURE SCHEMATICS Slow response when selecting parts in schematic8 P( K7 Z, v6 n# H$ w8 ?4 B
2039931 CAPTURE SCHEMATICS Slowness in OrCAD Capture when ITC is enabled
4 ] S8 _, h" r% |; E* o, c2106942 CAPTURE SCHEMATICS Inter-tool communication needs to be disabled to resolve the lag issues in Capture
3 U4 |! ^! z5 ^3 [& ?- `2131683 RF_PCB ROUTING PCB Editor stops responding on using RF - Add Connect: f2 U) b/ q# W1 c3 K( q3 B' I
2126505 SCM OTHER Thevenin Termination dialog displays resistors incorrectly
5 n! A0 r; G5 l1 Y) y' x2102383 SIP_LAYOUT WLP Advanced WLP Non-standard fillets not working properly: fillets not added- X% F/ L2 l5 ]
0 Y- P. r7 x0 ^9 o1 D6 [) U6 ?' c0 ]
Fixed CCRs: SPB 17.2 HF058( f. e6 y S9 |, |+ k
08-16-2019
y+ `& ~& W& J7 B========================================================================================================================================================9 m/ a* X. r# Y/ u; V* g
CCRID Product ProductLevel2 Title( y' d& x6 x& Z: |5 h
========================================================================================================================================================5 O N% l a& G+ W$ j( V
2113265 ADW LIBDISTRIBUTI Various DB operations take too long, rebooting server seems to fix the problem1 H/ O. }+ C! u% J" X" q
2122941 ADW LIBDISTRIBUTI Lib_dist execution taking too long to run, Capture CIS DBC File appears to be taking the most of the time# ^7 R1 j Z; V6 d. {) m9 W
2127319 ADW LIBDISTRIBUTI Library distribution fails at cisexport function with error (ORCIS-6250) Q+ S. Z' w- K$ f4 m0 U4 C
2107578 ALLEGRO_EDITOR 3D_CANVAS Allegro 3D Canvas shows split layer' \$ p0 k# j) r" \
2099538 ALLEGRO_EDITOR EDIT_ETCH 'Glossing - Via Eliminate' shifts traces to another layer8 s u) A1 d; g2 l8 R4 m+ y; P
2031883 ALLEGRO_EDITOR INTERACTIV Sub-Drawing: clipboard origin point is not set correctly
+ c2 r9 c- y3 i$ }2 R3 p! D% B2100433 ALLEGRO_EDITOR INTERACTIV Pad Edit displays error for extents (SPMHA1-69) if pads are at 90 or 270 degrees
+ P* L/ [7 w0 ~& i2 }- g- B. @2127239 ALLEGRO_EDITOR INTERACTIV Exporting a query result changes the working directory
' ]# n5 a. A' q# \$ l6 Y" P2117160 ALLEGRO_EDITOR MCAD_COLLAB Error encountered when importing IDX file into MCAD tool in HotFix 056/ g X7 u/ y, A& v2 f8 C5 U
2117427 ALLEGRO_EDITOR MCAD_COLLAB IDX files exported from HotFix 056 cannot be read in MCAD tool (the same files from HotFix 055 can be read)
0 z9 U) Q/ P0 a5 F0 f5 j7 D; A2117839 ALLEGRO_EDITOR MCAD_COLLAB IDX file created from release 17.2-2016 with Hotfix 056 is not readable in MCAD tools
% V( h) {5 S4 t2118019 ALLEGRO_EDITOR MCAD_COLLAB Export IDX is not working in Hotfix 056 but working in HotFix 055
" P) V' R, S) t/ m( `$ T2106425 ALLEGRO_EDITOR NC Disable undersize regular pad and oversize soldermask pad for start layers
& t+ @/ H! `1 c0 j2126766 ALLEGRO_EDITOR REPORTS Cannot generate reports and export ODB on board. b- z M0 ~- I, |( m. x( B
2107849 ALLEGRO_EDITOR SHAPE PCB Editor stops responding on updating shapes2 N6 h% }8 X3 g6 @5 p
1778109 ALLEGRO_EDITOR UI_GENERAL Constraint Manager exits on doing 'Undo' in PCB Editor0 u4 `7 F5 y4 W" {6 V
2064092 ALLEGRO_EDITOR UI_GENERAL Allegro Constraint Manager closes on clicking Undo in the layout editor
; q1 m" o6 C/ c" h \2093341 ALLEGRO_EDITOR UI_GENERAL Show Element incorrectly displays in report window on a single line if an HTML Report is open when show element runs" r* r: f6 m, g6 G9 B
2110909 CONSTRAINT_MGR UI_FORMS Cannot type dot (.) in DFA Table of Package to Package Spacing in DFA of Constraint Manager.+ t% L) C. Y% {* k, N: e
2096846 INSTALLATION ADW Component Browser does not open if adwservice.exe is not added to the Windows firewall exception list
4 {1 x- B1 k& |" ], f% ]2128118 INSTALLATION ADW Unable to connect to Component Browser.
* s0 W# r) }7 B7 O; C2116749 PCB_LIBRARIAN OTHER Cannot open Part Developer with a Venture PCB license (PA3810)0 S9 r) J6 j( B2 M& Y
2115302 SIP_LAYOUT IMPORT_DATA Performance issues with die text in and pin use codes, function utcle pwrgnd
1 E# a V, R# m2 |+ k, W L2103784 SIP_LAYOUT MULTI_USER Symphony Server rejects the move void commands on a specific shape instance- x& i8 o- b5 }; v- T
2096239 SIP_LAYOUT STREAM_IF Database fails to create stream out file4 B7 w, s+ ]4 u
2117572 SYSTEM_CAPTURE EXPORT_PCB System Capture crashes with multiple Export to PCB Layout
( O7 _9 g. {7 k& x, S4 Q& V3 j# F3 m [
1 Q& \3 Z+ o/ A" l
Fixed CCRs: SPB 17.2 HF057. O2 d( Z* D7 ^# A% |& s* o
07-19-2019
4 @/ [" r i. w# }# s; ?9 v========================================================================================================================================================
* F+ d3 i$ F7 ]! r) sCCRID Product ProductLevel2 Title
( N3 V7 U# b5 ~; Q4 k========================================================================================================================================================
3 y$ z* e+ J3 X# X0 j# ~1920958 ADW ADWSERVER Designer server will not start due to corrupt inr file9 H8 v( B( W1 y; j/ i
2039243 ADW LIBIMPORT libimport ignores footprints generated by Library Creator due to changes of attribute names1 G% H+ t. B1 |3 _7 P6 m8 O2 L$ @- I
2113226 ADW PART_MANAGER System Capture stops responding while importing DE-HDL sheets, P# G( K/ @0 i: l1 @* U
2035942 ALLEGRO_EDITOR ARTWORK 'Create Artwork' is slow when all films are selected
& \/ c. Z. N R: y, C* v2096958 ALLEGRO_EDITOR DFA Cannot launch Constraint Manager after assigning CSet and closing
}$ `4 ~' T* g$ [2087181 ALLEGRO_EDITOR DFM DFM reporting false positive hole to hole with stacked microvias! Q$ w7 c/ W) h4 L1 O% S* F, V
2099400 ALLEGRO_EDITOR DFM Placing a mechanical pin on a cutout causes PCB Editor to crash" G) g! J; ~) p$ _" a% A
2067214 ALLEGRO_EDITOR DRC_CONSTR Constraint Manager crashes for design linked board3 v! ^0 N/ [9 B4 P) }8 c
2097464 ALLEGRO_EDITOR MULTI_USER Design data lost if network connection drops in Symphony
; ]9 }( H$ T+ k2108211 ALLEGRO_EDITOR MULTI_USER Error: Update #1 (Perm shape) was rejected by server
- x8 s7 D/ p- y8 T. e, _; }2117154 ALLEGRO_EDITOR MULTI_USER Error message needed for Symphony for client disconnections( _; T4 K$ U. g8 |+ k7 E* W3 t, H
2100149 ALLEGRO_EDITOR REPORTS Error message (SPMHDX-9) for too many field names while generating dangling via report
. X* ]) ~% I$ Z% X: \& k Y* Q2101932 ALLEGRO_EDITOR REPORTS PCB Editor internal error (SPMHDX-9) for too many field names when running BOM report
I" j$ h9 d0 f5 {& q% B% r2111449 ALLEGRO_EDITOR SYMBOL 'Layout - Renumber' results in error: {3 O* i' e* M, s# A0 T6 k
2102177 ALLEGRO_EDITOR UI_GENERAL axlDMBrowsePath returns incomplete information
- L# j* o! M8 t2 Y2105342 ALLEGRO_EDITOR UI_GENERAL PCB Editor stops responding for 'Show Element - Find - Symbol Type' on a particular board. i! W& s4 E4 Y; H6 I- }" ?
2085443 APD ARTWORK Gerber lacks precision required to void some vias for a design in artwork output: need warning
8 V5 B) I4 w7 x: k2080118 CONCEPT_HDL CORE Getting error after adding offpage to bus and assigning a new value to $sig_name/ e! B1 j1 k4 q5 V6 U
2099438 CONCEPT_HDL CORE Genview allows dragging group of signals in split symbol distribution form, w" I1 k1 Y" j9 n6 o" W2 P) K9 ]
2108289 CONCEPT_HDL CORE Variant data is not in sync with the packaged data
# W: m s# Z+ v: B' G2087217 CONCEPT_HDL OTHER Variant back annotation will not work if there is a double quote (") in the description field of a part' U8 o2 Z7 B) _) w) b5 l
2107430 CONCEPT_HDL PAGE_MGMT Insert page is not working
" S7 _" S: Z/ j" K4 D" [9 b2063875 CONSTRAINT_MGR OTHER PCB Editor crashes on deleting match group without closing Constraint Manager- a; q' p9 E& S* _; R# ]( I; s
2103729 F2B DESIGNVARI Cannot enable hierarchical variants for block) F) i- y) p$ A$ {% R
2099076 F2B PACKAGERXL Package fails for 'Save Hierarchy', but succeeds for 'Save'
( s) o6 R: d7 C x) }9 Z6 _2081132 INSTALLATION SPB Part Information Manager cannot connect to EDM server after upgrading to HotFix 053" |; c" k3 }; j: U
1599964 PSPICE ENVIRONMENT Version Info displays 'OrCAD Version Viewer MFC Application has stopped working'
7 Y& U4 B0 ?% l! r( [: e8 V$ E* {2045497 PSPICE SIMULATOR 'Illegal Parameter Value in File' error when loading Monte Carlo parameter file* U$ }: d2 o) ^- i
2025997 SCM TABLE Copy-Paste Broken in Physical View6 l7 V0 X/ Q% {" \
2102652 SCM TABLE Unable to copy the Associated Components Ref Des values to Excel% y" ~2 ]- e/ X6 ^
2054225 SIG_INTEGRITY SIGNOISE Cross Section Editor bug after changing the impedance value in Analyze - Preferences3 N/ x7 [2 ~5 Q, g5 N6 `4 @
2100075 SIP_LAYOUT DIE_ABSTRACT_ Refresh co-design die running slow
# C1 }+ T* v) S. V3 I- j2106312 SIP_LAYOUT DIE_ABSTRACT_ Die abstract I/F to bring into SiP Layout and OrbitIO power/ground and signals not designated as RDL
3 s. g5 J" B( I2106314 SIP_LAYOUT INTERACTIVE Large design causing severe lag in Windows Server machine
% q7 e: z5 V% `/ m' D! O9 R* \2101622 SIP_LAYOUT MULTI_USER Symphony Server rejects the slide commands when tapered trace option is on
: ~9 n& b- n, `: m7 o+ d0 v5 |2107897 SIP_LAYOUT WIREBOND Design stops responding when running Wire Bond Auto Spread in HotFix 055
3 y+ A4 P1 J$ j; d- u4 B% Z6 Y9 B$ Y2104885 SIP_LAYOUT WLP Advanced WLP: Metal Density Scan, scan area in report is incorrect! s9 `" q# E; \" w# @ o& s
" M; H9 a0 H; l$ r) Y( m
+ j! s" n# m* n4 L" [Fixed CCRs: SPB 17.2 HF0560 H# e) l3 S( y6 b
06-21-2019
4 A( I( A O, h6 _5 b4 H0 T0 l+ h2 z========================================================================================================================================================- r- e5 S* G3 Z3 u
CCRID Product ProductLevel2 Title( n; f8 k9 r- Z3 E' j
========================================================================================================================================================
' M5 M* E1 _) B$ @2086463 ADW PART_MANAGER System Capture cannot add components when accessing remote machine via Citrix! `: j, U( a, P7 j2 _ I
2092868 ADW PART_MANAGER Release 17.2-2016, HotFix 054: Empty cache.ptf causing injected properties to not to flow from pstchip! f/ M2 @& }; O _ z
2092872 ADW PART_MANAGER Import DE-HDL Sheets stops responding
* t! o; w4 C) t1 G, \' O2088975 ALLEGRO_EDITOR 3D_CANVAS Bending in 3D Canvas causes PCB Editor to crash
% X8 t5 L) Q3 [, _5 o! i* S( W2088577 ALLEGRO_EDITOR COLOR Export color nets does not write all the nets in param file- g9 A; r6 V! H q1 {7 |
2028867 ALLEGRO_EDITOR DFM False DFF Trace to Thru via pad spacing DRC
2 A' o; H+ S0 S# @$ y2037361 ALLEGRO_EDITOR DFM Soldermask features drawn with a line do not DRC to pin, via, or shape soldermask features
7 [: x0 l9 F5 N: |7 U2077913 ALLEGRO_EDITOR DRC_CONSTR When running a simple SKILL command, the tool will run for a very long time
: d" j- n" t; m8 h* W2079642 ALLEGRO_EDITOR DXF Drill symbols are rotated in exported DXF in release 17.2-2016$ j6 H5 R3 {# S2 L4 F5 N
2083493 ALLEGRO_EDITOR MANUFACT Manufacture - Cross section chart is not readable for rigid-flex designs4 \ p; n" W8 ?: D
2073607 ALLEGRO_EDITOR MCAD_COLLAB IDX_IN batch program to allow a batch update of an .idx file
4 h6 o0 ~$ `; ~2095632 ALLEGRO_EDITOR MULTI_USER Design server on Symphony stops responding and cannot be closed or downloaded6 Y1 D3 U3 c+ M& T- R- W! f
2098221 ALLEGRO_EDITOR MULTI_USER Symphony Server Manager allows connection to databases deleted from the project area4 Z) }: v, A# V
2087315 ALLEGRO_EDITOR NC Backdrill exclusions raised on pins of a component
/ j# m" v) @5 [: L8 m2 _4 B* F1947929 ALLEGRO_EDITOR OTHER The 'show measure' function crashes when measuring pin to pin distance
$ {" c6 T4 C) a8 p: Z2091932 ALLEGRO_EDITOR OTHER Unsupported Prototypes command missing for the OrCAD licenses2 N r% A0 ]9 i% N: X- e. g
2089470 ALLEGRO_EDITOR REPORTS Summary report shows the exclamation character (!) in the middle of numbers and words
" t6 r! z" K: O! N4 y- V2067324 ALLEGRO_EDITOR SHAPE Netin crash during third-party Netlist import
5 i9 ^& F% C3 P6 T* _+ K( `2075191 ALLEGRO_EDITOR SHAPE Delete islands in the design: update out of date shapes and Database Check/ J3 l# q7 q2 e/ t1 Z- X/ m+ |
2090604 ALLEGRO_EDITOR UI_FORMS Undo/Redo UI grayed out when invoking Color192! U1 |- v E3 h4 e
2043825 ALLEGRO_EDITOR UI_GENERAL Custom toolbar settings are not retained upon restart of Allegro PCB Designer
5 B4 q5 E; E7 F) [- _2090185 ALLEGRO_EDITOR UI_GENERAL UI setting in INI file not retained
3 n, D6 ^8 ^* r9 p+ u4 I& \0 q6 O2090517 ALLEGRO_EDITOR UI_GENERAL Shape visibility box is not being enabled with the Enable layer select mode option in the Visibility Pane$ e$ b' y" x r
2092436 ALLEGRO_EDITOR UI_GENERAL RefDes length of input string for Modify Design Padstack is limited to 20 characters* @2 W+ `9 E% I0 H/ `
2099070 ALLEGRO_EDITOR UI_GENERAL UI setting not working properly, Icons missing after restart.
3 k6 _/ G7 \. C% s! c4 C2088484 APD DATABASE Some objects (Vias and Cline) cannot be modified (edit, delete and slide) in the mcm database2 q& }; B5 H$ }0 a! {' r3 h
1951623 APD DEGASSING Shape Degassing fails with specific Void to Shape boundary value' A% K. S' ?# d& h
2081363 APD DEGASSING Cannot degas for specific shape
0 i/ i0 Q9 O! v. H2083498 APD WIREBOND Cannot wire bond from a diepad to another diepad on the same component
6 k9 K C* g6 D2 `. z" d2086589 CAPTURE NETLIST_ALLEG The generate the CM enabled files from the command line using pstswp.exe.8 y* {: k0 u- I
2098248 CAPTURE NEW_SYM_EDITO Ignore pin is not working for individual pins in Edit pin spreadsheet when edited for all pins" ~& u5 m' s8 Z' ?
1773047 CIS PART_MANAGER Pin numbers and names for DNI parts will get disappeared in variant view mode if they are relocated in part editor: i0 Q0 _2 \& e2 Y1 Z7 d: I
2003818 CIS PART_MANAGER Pin name and number of 'do not stuff' parts are not visible in the View variant mode
$ X6 q( c5 K! z2076265 CIS PART_MANAGER Variant view pinnr/pinname disappears
; X+ M3 | ~' M% q. f2076282 CIS PART_MANAGER View variant does not show pinnr and pinname
% c9 [# X/ \+ C: m9 @( y; n! J2083394 CIS PART_MANAGER No pin names and numbers on variant view for specific parts) i9 X7 G8 j( t: M: |" I
2090027 CONCEPT_HDL CORE Cut and move of split hierarchical symbol to another page results in error due to lock or write permission issues
! W% o* j4 h2 {7 m( O2071355 ORBITIO ALLEGRO_SIP_I Dummy nets creation in die after performing Merge Updated SiP
1 O6 m4 b6 C% d/ {) y2067703 PCB_LIBRARIAN OTHER PDV crashes immediately for vector pins if MSB is lower than LSB& G; N9 [* _* Y$ ]) a0 G- j! W
2041348 PCB_LIBRARIAN SYMBOL_EDITOR Grid setting change cannot be saved in new Symbol Editor, ^$ \% K; b5 l6 |! y0 F, b
2041365 PCB_LIBRARIAN SYMBOL_EDITOR Improve copy drawing objects in new Symbol Editor
W- z; d1 t3 Q2067931 PCB_LIBRARIAN SYMBOL_EDITOR New symbol editor grid issue: documentation grid spacing value changes
& O2 c* |6 I4 c0 g5 Z/ w2093849 PCB_LIBRARIAN SYMBOL_EDITOR Symbol font text and appearance different when placed in Schematics
: p# p# e% `+ a0 g8 @- k* M$ C1919298 PSPICE FRONTENDPLUGI Capture crashes on archiving project
# V' B" u; R5 ~0 x1953001 PSPICE FRONTENDPLUGI Archive project causes Capture crash.7 v, r# ?7 h) p% `) J; Z
2035572 PSPICE FRONTENDPLUGI Crash on archiving project4 O8 ^% w) P' U+ K! m
2041286 PSPICE FRONTENDPLUGI Archive project crashes when using lib as global.
" j* B% _1 W; i* } n* s/ `2081796 PSPICE FRONTENDPLUGI 'Archive Project' crashes Capture in release 17.2-2016, HotFix 053
- I9 p4 }+ x% A" z: i" B5 m/ E! H" W2106017 PSPICE FRONTENDPLUGI Capture crashes when archiving PSpice-enabled project
# O {+ E/ M' |- P; e2 Y2051450 PSPICE PWL PWL Sources application: pop-ups and messages when browsing and placing source, ~1 N2 h6 h# R- ~0 k
2090021 PSPICE PWL Modeling Application - Sources - PWL Sources Dialog is not properly displayed4 w, v- `2 ^& L4 C7 S$ y8 T- m: R
2094548 PSPICE SIMULATOR Model undefined error on TL494 x5 Q8 S2 Q! p
2058018 SCM PACKAGER Reference designator mismatch in 'exportsch' schematics and board file
" C v5 A+ b6 a1955868 SIP_LAYOUT STREAM_IF APD/SiP Layout: Export rounded features as circumscribed and not inscribed polygon in GDS0 w" c. y6 `. I2 v1 U. n, f
2081914 SIP_LAYOUT STREAM_IF Release 17.2-2016: GDSII stream out drops shapes
) p! a' q8 l) k+ m5 s1 @7 q* E2013647 SYSTEM_CAPTURE CANVAS_EDIT Replacing a vertically oriented RES with a horizontal CAP breaks the wire connections
- k+ j# _" _) c y; \
7 K0 D* b ~, b9 t/ E( ?0 S
! O9 k7 N0 r$ C) O4 F' L+ kFixed CCRs: SPB 17.2 HF055- K" `. j v6 w o# f
05-24-2019
% O1 ]6 w' |9 o========================================================================================================================================================
! g7 {7 _4 N! `% E, _. bCCRID Product ProductLevel2 Title* A1 s1 ?0 k5 A& \/ @
========================================================================================================================================================
2 T* g+ I8 ~' U5 {) c$ i" B% C8 p2078057 ADW PART_BROWSER Symbol Graphics preview is not available in the Designer Server! Q! ^! ~9 C0 }7 l9 V
2092863 ADW PART_BROWSER Component Browser is not displaying the symbol & footprint preview7 p* |( R* d9 d2 r9 O+ [
2076339 ALLEGRO_EDITOR 3D_CANVAS Floating parts on bending a board in 3D Canvas with HotFix 053
9 Z5 C8 B8 g$ c i' o2051075 ALLEGRO_EDITOR ARTWORK Incorrect Gerber import in Allegro PCB Editor5 V, h" ? G1 D$ G$ o" m! E! g. x
2073407 ALLEGRO_EDITOR DATABASE axlDeleteByLayer deletes fixed shapes
8 i4 z4 L" c; r5 i' f) v2079117 ALLEGRO_EDITOR DATABASE Release 17.2-2016: Board file saved in HotFix 049 cannot be opened in HotFix 014# g% }. m3 @$ V" `$ w
2079204 ALLEGRO_EDITOR DFM Enabling option to update analysis mode and run DesignTrue DFM wizard causes PCB Editor to exit$ @/ ~0 U. u/ \+ z
2082394 ALLEGRO_EDITOR DRAFTING Angular dimension not owned by the same parent symbol in the layout are not deleted on moving object5 j; a% q6 o4 f/ s& u
2067916 ALLEGRO_EDITOR INTERACTIV Place replicate module bounding box does not move with circuit after module is updated
! Y" L7 e: k4 S, s# k% L2068449 ALLEGRO_EDITOR MANUFACT Stackup chart and table shift slightly from original location on re-generation in Allegro PCB Editor release 17.2-2016& j3 v- ` v; `7 ]0 N+ A
2065820 ALLEGRO_EDITOR MCAD_COLLAB Selected objects deleted from the design on clicking Cancel in IDX Flow Manager Import" {9 G: j* x! B
2080164 ALLEGRO_EDITOR MCAD_COLLAB IDX outputs two sets of masks ]. f4 o% {$ `; `; r4 X, O! n
2081955 ALLEGRO_EDITOR NC Artwork file error for via size8 ]8 g$ ~7 |$ p" g# M; E1 g
2045061 ALLEGRO_EDITOR PLACEMENT Setting PSMPATH: axlSetVariableFile() does not update Place Manual but User Preference Editor does/ {, b# U7 D+ k9 ?. w# j
2049949 ALLEGRO_EDITOR PLACEMENT Get import errors and cannot place some parts if user-defined option is turned on for netlist import( Z4 X; c7 d4 N% ^/ K4 ^) x) }& M
2069289 ALLEGRO_EDITOR PLACEMENT Cannot place part because attribute definitions are incompatible for the 'DESCRIPTION' attribute (SPMHDB-154)$ z9 |0 N1 F k( z9 F
2056573 ALLEGRO_EDITOR SCHEM_FTB Import Logic takes a long time when checks are turned on6 M' p# \0 j6 r8 O. q3 X
2076452 ALLEGRO_EDITOR SHAPE Shape Degassing crashes if 'Inside Shape' is selected* C- W+ o* U T6 P
2076873 ALLEGRO_EDITOR SHAPE Symbol Editor stops responding on editing shape with a .dra file
1 ^! N( S: A/ S1788703 ALLEGRO_EDITOR SKILL axlPadSuppressSet does not work when 'none' switch is used) N" ^5 a& K, s/ F5 }
1955127 ALLEGRO_EDITOR SKILL axlPadSuppressSet( 'off 'none ) returns a warning message and does not work per the documentation- P: S0 E6 c- c$ H$ b- ^
2031711 ALLEGRO_EDITOR SKILL Syntax error related to allegro.ini shown if allegro.ilinit loads INI on startup
& M, W4 O- P2 l& l' U$ X% T2062527 ALLEGRO_EDITOR SRM RF elements are shown in Symbol Revision Manager
/ t# o9 a2 i& z# ~ n2074249 ALLEGRO_EDITOR TESTPREP Testprep re-sequence causes PCB Editor to crash if 'Labels with Net Name' is selected$ `2 i3 [. [3 t
2070534 ALLEGRO_PROD_TOOLB CORE Productivity Toolbox bar code generator is creating corrupted shapes in the database" v% ?0 f" ?! t4 G6 y- I5 U
2046278 ALTM_TRANSLATOR CAPTURE Third-party import fails
7 l% t# q) n7 Q' N! Z9 a% T4 D2052399 ALTM_TRANSLATOR CAPTURE Third-party CAD translation stopped with error message: ]4 b- l B! z5 i$ y$ J) q) @, i
2005087 ALTM_TRANSLATOR DE_HDL Cannot translate third-party to Allegro Design Entry HDL
7 z! h1 Y0 N. H2 N" Z1922222 ALTM_TRANSLATOR PCB_EDITOR Third-party translation converts to board with unconnected nets
+ S/ S- p! k# ^. R1987263 ALTM_TRANSLATOR PCB_EDITOR Third-party board file: copper not imported# K& |( d3 s9 k* `2 x+ t+ v
2017988 ALTM_TRANSLATOR PCB_EDITOR Third-party to Allegro PCB Editor import issues with routes, constraints, size, and accuracy
. e S: U) r" E6 H& f1 r8 i2021300 ALTM_TRANSLATOR PCB_EDITOR Third-party translator does not show any results on PCB Editor canvas- @$ i# F7 a$ c U
1890675 APD DIE_EDITOR Mirror Geometry is Mirroring the symbol from TOP to BOTTOM Layer in SIP file7 Z9 g/ S- p9 R9 M0 `
2064219 APD DIE_EDITOR Applying mirror geometry results in mirroring: moved from TOP to BOTTOM layer
) O) l) Y7 V! Z7 P. L0 p: E4 ~2086574 APD OTHER Duplicate layer text shown on the vias5 [' W0 u {/ C. k6 D0 n; U
1948169 CIS CONFIGURATION Auto Symbol Refresh Checking not working for shared folders/ {( M& H+ @' S# U% i+ i& a* I! k
2025385 CONCEPT_HDL CORE Hierarchy Viewer expands/collapses randomly after clicking the '+' or '-' symbols
. N' E" P5 K8 q8 I2050010 CONCEPT_HDL CORE Copyproject does not properly copy the variant files
+ I) I& n1 `! s2063457 CONCEPT_HDL CORE DE-HDL: very slow rendering on some systems# S" V: S+ G5 Q! E
2076312 CONCEPT_HDL CORE Getting 'Variant out of sync' warning when creating BOM for a design with no variants
/ u; s7 H. ?$ q; ?7 H" U9 u, w2083650 CONCEPT_HDL CORE Lower-level signals are appended with _1, _2, and so on
: R. d. f6 r1 H% P* Y/ U- o/ J2083651 CONCEPT_HDL CORE The physical net names still do not sync with the assigned signal name6 W$ {7 Y# B8 p
2056736 CONCEPT_HDL GLOBALCHANGE Global Property Delete does not operate on the entire design unless the top-level page 1 is open
3 V* A/ r/ F. `1955357 SIG_EXPLORER OTHER Signal explorer invocation with OrCAD PCB Expert Suite license
* ~6 o8 O' a8 y4 |! e2079071 SIP_LAYOUT SYMB_EDIT_APP Response very slow after Show IC Details on a very large co-design die9 S6 ]& d) r' w. k
2081884 SYSTEM_CAPTURE CANVAS_EDIT Symbols take a long time to move, and results in DRCs and broken connections4 _3 B6 m# l, \. B. G
1942542 SYSTEM_CAPTURE IMPORT_PCB System Capture - TDO backannotation overwrites net names with stale data in lower-level blocks
3 ]0 E' r! R4 I6 _* [' s" `2071303 SYSTEM_CAPTURE MISCELLANEOUS cds.lib file is picked up from wrong location
) V9 i. W6 v0 S% m' J. u. Q2058979 SYSTEM_CAPTURE OPEN_CLOSE_PR System Capture prevents a project from opening by putting a single quote at the end of a line in CPM file2 ?' h$ t! `# u0 E6 E) x
2088210 SYSTEM_CAPTURE OPEN_CLOSE_PR The 'enable pspice' entry in CPM file is occasionally corrupted
0 \+ e( B [: }/ q
' P; t7 p5 H! G# B( n) |9 v, v
" l' Z ]" O& s4 d$ EFixed CCRs: SPB 17.2 HF054
- c( i! B; @8 O. x- ?, @" A04-26-20194 H: J. ]! {% V6 s+ R, j$ z
========================================================================================================================================================
d7 f" l" t& E) B0 h7 z/ o/ Q, X! JCCRID Product ProductLevel2 Title0 \' U9 Z |5 Q. G, T$ r. N0 G
========================================================================================================================================================' i" {0 t d( A; b$ B8 \7 D
2060269 ADW DBEDITOR Unable to create ECAD type mixed-case schematic model attributes" F/ P' f) s; j# m9 Q9 N
2030086 ADW LRM Cache part_table.ptf made by LRM Update cannot be read if it has null value in key property- x9 @7 p) [- a* ^5 z; ^3 q
1975317 ADW PART_BROWSER Space at the end of line in CDS.LIB results in zero libraries being shown in new component browser
7 F0 }% k. _7 i* f# M2076340 ADW PART_BROWSER .helix folder needs to be deleted for PTF changes to take effect and to convert a design to cache
* z# Q( y- Q: ~2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name) Q( [1 @. r+ M: m
2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design
" _% q- [0 N! `! f" k. d% c/ t% S8 K2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object
5 d- [" X5 F" c7 L6 F8 e! O4 r6 |2054243 ALLEGRO_EDITOR 3D_CANVAS Plating is not shown on stacked vias in 3D canvas* c5 D0 h* c) j/ y% G% c
2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation
7 L- ^4 L. D& R3 V! o2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded
- N# r5 s3 |$ d3 q# ?0 V' q3 W2060489 ALLEGRO_EDITOR COLOR SKILL axlGlobalVisibility() issue in a partition file: VIA/SOLDERMASK_TOP subclass visibility not turned off
& i& |3 ]0 F& ]( b# R2072695 ALLEGRO_EDITOR COLOR Clines of colored nets not colored when 'display_nohighlight_priority' is set
3 O: o( ~+ r" ?* z2 `8 ?, z0 J( Q, n2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone# k" d8 C; w3 h0 d+ J5 e9 D2 X5 j% Y' [
2010812 ALLEGRO_EDITOR DATABASE PCB Editor STEP model offsets should follow origin movements
# |, G ]. D, }! L, f2011993 ALLEGRO_EDITOR DATABASE Change STEP model mapping when Symbol Origin is changed in DRA using Setup > Change Drawing Origin
6 B% K. x0 _, v- w* G) q5 J2051596 ALLEGRO_EDITOR DATABASE Error for unsupported property in element* `: o8 e# p" C" ?6 a
2056497 ALLEGRO_EDITOR DATABASE Place manual is slow
- Y8 }! j/ d0 K; q2 P2059489 ALLEGRO_EDITOR DATABASE DBDOCTOR in batch mode with argument '-check_only' detects text error+ t ~9 n& {- B9 H& u7 G
2064268 ALLEGRO_EDITOR DATABASE PCB Editor crashes when running SKILL code8 l6 G% K/ U6 O0 z) E/ {2 k7 c' l9 I
2068588 ALLEGRO_EDITOR DATABASE Crash on opening release 16.6 design in 17.2-20169 y# K8 p8 V- g# G% d! g; H
2079131 ALLEGRO_EDITOR DATABASE axlChangeNet crashes PCB Editor in fast shape mode with Microsoft Visual C++ Runtime Library Error
: M* n% ?5 J' H; F2034759 ALLEGRO_EDITOR DFM Importing DFT constraints on board does not assign csets to design but shows the csets
+ @% S" {# ?9 f1 Z! a9 S F& g2039992 ALLEGRO_EDITOR DFM Cset is not set in Pastemask element of DFA when importing XML Constraint File., ^ ~; z' c8 M; I; m
2046824 ALLEGRO_EDITOR EXTRACT Extracta ECL_NETWORK View reports incorrect pin layer.
, E, j- Z' Q* E! u$ n- M2048912 ALLEGRO_EDITOR IPC Running PCB Design Compare - Graphic mode reports ERROR (SPMHA1-273) 'Shape intersects with itself'
( N; U7 Z* }* `% `4 N# E9 k2066597 ALLEGRO_EDITOR IPC Graphical compare not completed because of self-intersecting shape locations% w1 h* y% n) X! A4 I9 U
2079719 ALLEGRO_EDITOR IPC IPC2581 import fails with error 'Failed to add (LW)POLYLINE'
' U* i( X: |3 S5 x( M2066229 ALLEGRO_EDITOR NC Tool code missing in backdrill NC file on choosing 'Optimize Drill Head Travel' in NC Drill
+ l) ]& f" s6 I+ |% [3 ?$ X! ^' C2070379 ALLEGRO_EDITOR NC After running backdrill some vias are shorted to other nets" P7 y! H& d4 ~
2041881 ALLEGRO_EDITOR PAD_EDITOR Difference in locations of drill in pad editor and symbol editor
0 V6 ^' N( i4 }8 j. F' S2058852 ALLEGRO_EDITOR PAD_EDITOR Net associations lost on refreshing vias
! k4 g; W0 O0 E8 u, O2061580 ALLEGRO_EDITOR PAD_EDITOR Lock Layer Span settings specified in padstack editor not reflected in PCB Editor
# K7 z6 y+ L0 b' C) B2048116 ALLEGRO_EDITOR REPORTS Extracta command files not visible in Tools-->Reports when there is a space present in the textpath variable
0 V: U! J! d1 Q& D2038949 ALLEGRO_EDITOR SCHEM_FTB Netrev is slow if there is an input board file with many modified components5 C7 o# z# B( k8 o+ a2 Q9 g3 C, Z
2052758 ALLEGRO_EDITOR SCHEM_FTB Connectivity objects are being reported as Added and Deleted in Constraint Differences Report
8 _+ N7 N8 F- x2066099 ALLEGRO_EDITOR SCHEM_FTB Inconsistent net names on export physical after changing net names in DE-HDL
5 w3 W/ H* C* k2043882 ALLEGRO_EDITOR SHAPE Shapes not updated to 'Minimum aperture for gap width' in Global Dynamic Shape Parameters window
, W4 g a* t# H1 Z/ X- ]) y2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update) X; ] [& [! y1 A9 h9 V
2052063 ALLEGRO_EDITOR SHAPE Cannot import IPC2581 due to 'Shape intersects with itself'
3 ^0 i* j ~" v# x+ t1 F7 ^2056478 ALLEGRO_EDITOR SHAPE Editing shape by sliding segment causes PCB Editor to fail due to 0-length segment in shape: ]$ o' l, p4 }7 k3 V
2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present
/ p0 o. z8 ^% P" z2066473 ALLEGRO_EDITOR SHAPE Teardrops create strange copper shapes
( ~0 Q7 E9 @* g4 k" H) p2079698 ALLEGRO_EDITOR SHAPE IPC2581 import fails with error 'Shapes intersects with itself'
/ S. p3 ~" n* d* l) g/ t2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in HotFix 048.. P1 Z: Q1 O. b! z9 Q7 W: J
2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash
0 W' w7 z' V: V/ |+ Z2023755 ALLEGRO_EDITOR STEP Export STEP includes enclosure even when it is not selected.
! R# `: ?- x3 r9 r, D: U1881233 ALLEGRO_EDITOR UI_GENERAL Green/white canvas without grid when creating a board file (File - New)
: T7 J% {2 q9 B; l1900525 ALLEGRO_EDITOR UI_GENERAL Resizing the update symbols UI causes the options to overlap and jumble up (refresh issue)
% y: a% H9 J2 o8 Y5 V# ^2003861 ALLEGRO_EDITOR UI_GENERAL Same y-coordinate returned for different vertical positions when creating board outline in HotFix 048
' T3 O" x6 b- u9 r6 ^$ r2033958 ALLEGRO_EDITOR UI_GENERAL Incorrect canvas display on creating a design from the Start page and then opening an existing design5 u* M5 ?- f7 @8 v6 G$ K; h0 X1 M
2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog is behind canvas4 E& v+ E/ ?/ W
2054429 ALLEGRO_EDITOR UI_GENERAL Editor stops responding until choosing Done after clicking Zoom by Point twice c: U# I1 y4 q( y
2059707 ALLEGRO_EDITOR UI_GENERAL 'HTTPS' links are not shown as hyperlinks when using allegro_html2 ^% a# x" @; U
2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden' y: ^& ]( g. R+ ?- g$ V: B
2038105 APD DRC_CONSTRAIN APD crashes on update DRC in release 16.6
4 v2 U. X+ U) S* ^2050674 APD PARTITION Cannot remove C-Point from a partitioned design& d4 }# U# J2 D) k
2068814 APD WIREBOND Bond wires cross on auto-separate$ G! b- L7 i; s1 F4 d+ }" B# S
1967433 CAPTURE OTHER Cannot open DSN or OPJ files by double-clicking if Capture is already open
& L5 A- k& g0 m# g! R1967332 CONCEPT_HDL COMP_BROWSER Crash in customer environment on clicking on last row border in PIM after filtering
/ A* t* b: _1 M2001759 CONCEPT_HDL COMP_BROWSER Using Modify Component crashes Design Entry HDL
$ u2 i: i) `2 l, ?5 @& F2020788 CONCEPT_HDL COMP_BROWSER Intermittent crash when clicking bottom edge of part selection table in the Modify Component window
4 d0 A' b7 [4 D" E# g: y0 R- Z! R2 X2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved9 j+ D% \3 Z5 R2 q% `4 _
2013002 CONCEPT_HDL CORE Ability to regenerate Netgroup names to remove '_1' suffix
2 U+ l# X# C9 O+ ]2026637 CONCEPT_HDL CORE DE-HDL crashing often when launched from EDM Flow Manager
" @2 P2 L" }3 `& ^ z! D2041145 CONCEPT_HDL CORE Set font size & color of netgroup names and netgroup taps+ ~! F4 y; m7 j, J8 Y+ r6 Y
2056743 CONCEPT_HDL CORE NetGroups appended with _1_1, some are empty, and inconsistent in DE-HDL CM and Allegro PCB Editor CM
g& }+ x+ C$ d2 M- }: J2065889 CONCEPT_HDL CORE DE-HDL Modify command moves location of attached symbol properties
+ n0 N. l" H8 \, |5 ]2074410 CONCEPT_HDL CORE Full net connectivity not shown in Allegro PCB Editor.* N3 _6 ]9 S3 C0 `+ D4 o9 U: M
2045717 CONCEPT_HDL RF_LAYOUT_DRI The RF PCB Options is greyed out when doing Import Physical on Linux with enterprise licenses
2 |# ]! }6 V; ^4 w4 u( [. n2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor
) Z5 B# V4 q. X* y% P$ q2050521 CONSTRAINT_MGR OTHER Unexpected Xnet removal from schematic when Export to PCB Layout is executed.
7 B* d4 `" A7 p. }& `6 k2066270 PCB_LIBRARIAN SYMBOL_EDITOR Unable to edit note text containing comma; u9 X5 S' }2 {) N5 ?
2069181 PCB_LIBRARIAN SYMBOL_EDITOR Pinlist window expand/collapse buttons act weird first time when invoked.: r8 \" \ B- @+ p1 {+ _! L! G
2070007 PCB_LIBRARIAN SYMBOL_EDITOR Project not found error in Symbol Editor when path contains space character
; W1 n; q; ]" X2072793 PCB_LIBRARIAN SYMBOL_EDITOR Right-click menu of formatting text objects is not consistent: second and third options are swapped
& U% s. D) o: Y) n2073138 PCB_LIBRARIAN SYMBOL_EDITOR New Symbol Editor: Do not allow duplicate properties
4 J7 b, ]3 g1 p1957458 PSPICE FRONTENDPLUGI Refresh issue with Bias Display on a new design: bias value not updated1 v) l( ^1 _# L; Y2 v4 Z! K
2022211 PSPICE FRONTENDPLUGI Bias Point results are not updated
% m. J5 y) ^- S7 a6 ~5 J8 |2031058 PSPICE FRONTENDPLUGI PSpice bias values are not getting updated
. b9 a( h V0 v5 x2038021 PSPICE FRONTENDPLUGI Bias display is not updated
- Z, R: ~9 Y8 i9 ^' k% q$ D2055274 PSPICE FRONTENDPLUGI Capture crashes on SIMSETUP OK when two projects are open% }! F1 f& C3 G
2053432 RF_PCB OTHER Property on RF component not transferred to new design not containing the component5 s& G) p1 h1 F9 D
2003341 SCM SCHGEN Unable to generate a schematic for hierarchical blocks% ~2 \2 j6 ^( @- g# s6 _' b& Q
2069924 SIP_LAYOUT DIE_ABSTRACT_ Conversion from co-design die to standard die / BGA / anything else must remove floating function pins.
; U& e J- j% N- ?9 ~; Z2067894 SIP_LAYOUT OTHER sip database size is enormous for a small component definition used in fdesign. S# q) g$ M. r+ a6 [) n
2067987 SIP_LAYOUT OTHER Orphaned die attachment in SiP Layout cannot be removed
Q$ g; t0 A- p2 C2072857 SIP_LAYOUT OTHER SiP Layout crashes when using Find by Query and choosing 'Symbols'
9 [6 |8 x* A" u# M2068973 SIP_LAYOUT REPORTS SiP Layout Missing Fillet report not catching a missing fillet in HotFix 051 and 052
& }( W1 U# ]; K2059533 SIP_LAYOUT SYMB_EDIT_APP SiP Layout: Cannot rotate bumps in Symbol Editor application mode+ V4 X5 ]5 f8 y; S( g+ h1 z) m
1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error( A E! s0 Y- D( s5 W9 q
2054869 SYSTEM_CAPTURE AUTOMATION syscapUtils.tcl command cnsAutoCreateDiffPair is broken due to missing acm_code.il and acm_config.txt files
. C1 M3 E) m) B0 T! G1966488 SYSTEM_CAPTURE CANVAS_EDIT New folder rename box does not show the text typed.2 K/ d! M' s) x; V' H( [ j
1814813 SYSTEM_CAPTURE COMPONENT_BRO System Capture session log should specify the CDSSITE path for the current session. {+ t: X. m! p, X- t
1977673 SYSTEM_CAPTURE COMPONENT_BRO adding reference blocks through add component error when cell name matches design name# M) u, P/ c7 J f% i% c
2027100 SYSTEM_CAPTURE COMPOSITE_FIL pstdedb.cdsz and netlist preview in System capture is not being updated when individual netlist files are written) Q4 I. k2 x7 V3 ^( [2 o
1961274 SYSTEM_CAPTURE CONNECTIVITY_ Xnet removed during pin swapping
# F: F. j) ?9 O$ \1 T2041879 SYSTEM_CAPTURE CONNECTIVITY_ xnets on net with only pull-up resistor, S' u& o: {8 g' ~. i
1889238 SYSTEM_CAPTURE COPY_PASTE Wire fails to connect during copy and paste: ?$ w8 i9 ?) Y" n7 M# l8 P- [
1993146 SYSTEM_CAPTURE DESIGN_EXPLOR Cannot move page up by only one position; G8 e" H5 [ R" G6 {
1910941 SYSTEM_CAPTURE MISCELLANEOUS Parts that are not in any schematic page appear in netlsit and BOM' B/ W0 d' m5 ^# M8 Y, ]
1902347 SYSTEM_CAPTURE PRINT Prints all sheets if one sheet is specified as the print range" d* y7 a: |# C& G! N* d9 `
2041272 SYSTEM_CAPTURE SMART_PDF Smart pdf displays component outline when component is not de-highlighted.
* `6 s8 `, t: F# f2065768 SYSTEM_CAPTURE SMART_PDF Custom Variable in Table Object not getting passed to PDF
3 h! P: k/ e" T' Q# c8 T1969243 SYSTEM_CAPTURE VARIANT_MANAG Export variant does not name file correctly if the filename contains a space
* w, q9 d, K7 N! C6 R" T1990258 SYSTEM_CAPTURE VARIANT_MANAG Cannot paste copied preferred part to multiple parts with the same part number. N0 ^- |( Y, J# M( C5 K% _! Q: g
1992250 SYSTEM_CAPTURE WORKSPACE Double-clicking a .CPM file runs System Capture but does not open project$ y8 k3 A0 q/ s! H( ]# }2 q: p+ [
( p* R O' i# B
: t# h$ }8 d: z5 w+ y- UFixed CCRs: SPB 17.2 HF053
1 o7 U/ K. l$ S1 E+ }. j, c03-30-2019
# E- p% n2 `8 \: i/ f# E" E========================================================================================================================================================
8 L4 K! b7 a9 M0 T: V+ G, eCCRID Product ProductLevel2 Title
& {0 l! v0 `% Q8 X2 G$ W! v5 j========================================================================================================================================================
1 M9 _$ p/ |0 A: c) s2035766 ADW DSN_MIGRATION EDM release 17.2-2016: design migration UI is cut off on right) c4 h O. u* p+ X0 Z
2044872 ADW PART_BROWSER Component Browser: Only one PTF file read for multiple PTF files under Part Table all referenced in master.tag1 F: l% p- o% a4 O1 D
2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name
: N& h% q% M, f& e7 u9 c- Z, v2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design
/ Y3 r8 I# g0 A2 E. i# l, H2052046 ADW TDO-SHAREPOIN Joining projects is downloading 0-byte files due to SSL error
4 j6 P5 l, ?9 H1 Z2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object
' [3 l& x' p" o9 D, z6 @8 D2047512 ALLEGRO_EDITOR 3D_CANVAS Mechanical components do not move when bending in 3D Viewer6 o! y) q8 X0 N
2048086 ALLEGRO_EDITOR 3D_CANVAS Wirebonds are not linked to diepad when component is embedded body down
; K8 U2 A ?- v2 J( ?! ]4 r2051277 ALLEGRO_EDITOR 3D_CANVAS 3D View Vias are Offset from Board in Z direction
3 T) p7 d% F V9 ?1 C5 t2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation
: T/ C" ^! _8 H( f* O$ X2056547 ALLEGRO_EDITOR 3D_CANVAS 3D model not shown for component with STEP file assigned
; H& j% ?! _0 c, x4 O7 D2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded
/ t* V0 y T$ u, S3 l2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone; ?4 O0 W6 H! \8 k, e
1826533 ALLEGRO_EDITOR DATABASE Dyn_Thermal_Con_Type not behaving as defined in Symbol Editor after placing on PCB file. R' ^; W& Y j8 O
1857282 ALLEGRO_EDITOR DATABASE PCB Editor slow when Manhattan and Path length tooltip enabled in datatip customization
2 u- I5 F6 {; ~4 i1 Q3 T2052767 ALLEGRO_EDITOR DATABASE Allegro PCB Editor crashes on editing padstack
) c* x7 t$ t P5 ^% F1825692 ALLEGRO_EDITOR DRAFTING Dimension line text moved by Update Symbols* n0 T) f W( j1 d0 j2 V& B
1874814 ALLEGRO_EDITOR DRAFTING 'Connect Lines' does not merge overlapping lines) ~/ E% ~4 X+ j
1874935 ALLEGRO_EDITOR DRAFTING Angular dimension text has extra spaces added before the degree symbol.$ F' Q# i' e; M0 v% e, g3 M
1882597 ALLEGRO_EDITOR DRAFTING 'Trim Segment' should allow trimming for all intersecting segment types4 x4 [$ }# b$ l: P0 K3 S
2052315 ALLEGRO_EDITOR DRC_CONSTR DRC (pad-shape) incorrect when both pad and drill are offset from pad origin.
* q @; O u% y# K9 z" k2040603 ALLEGRO_EDITOR EDIT_SHAPE Shape is not updating correctly after the 'move' command
6 Y5 H6 z, ~4 P5 z9 f6 K2050177 ALLEGRO_EDITOR INTERACTIV Letters need to remain aligned and uniform after performing Boolean ANDNOT operation
- M& ?1 i# K$ E! p4 g: a2052586 ALLEGRO_EDITOR IPC IPC356 showing shorts and disconnects for chip-on-board design
# A4 o0 ^: I' L" } D; k1 L$ v& q2044350 ALLEGRO_EDITOR MANUFACT Cross Section table showing multiple decimal digits for the Tolerance column& V2 _5 b' f1 |
2051150 ALLEGRO_EDITOR NC Counterbore/Countersink holes not being shown in the NC legend table.+ ]. d1 b8 O; X1 G$ @1 c
2058199 ALLEGRO_EDITOR NC 'Manufacture - NC - Drill Legend' does not populate the CounterBore/CounterSink row values in the Drill Chart table
* h; Q& p5 d, E1 m+ d2061809 ALLEGRO_EDITOR NC Counter bore NC Legend does not show any data
( S' E! @+ C' i, m" B2063477 ALLEGRO_EDITOR NC Counter bore NC Legend does not show its value" b$ X" p! X1 D7 x$ T0 b! N) J% Z
2033849 ALLEGRO_EDITOR PLACEMENT PCB Editor stops responding when removing a plane that the Place Replicate command added
8 a; I- [7 D' L! ?+ e6 ~2037509 ALLEGRO_EDITOR PLACEMENT Move or Rotate or Mirror of a module/group makes PCB Editor to crash with no .SAV file created
5 l- G* T+ n; f* b2047480 ALLEGRO_EDITOR SCHEM_FTB Importing netlist using Capture-CM flow in PCB Editor is crashing netrev R0 z5 ~1 t* J
2046276 ALLEGRO_EDITOR SHAPE Add notch is not snapping to the grid point: n9 `* O% D. f
2047572 ALLEGRO_EDITOR SHAPE Voiding elements on static shape do not void adjacent layer keep-outs and PCB Editor stops responding/ q) l, O3 l6 J
2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update
8 ~$ Y) S( |- v3 T, g7 `2050120 ALLEGRO_EDITOR SHAPE Dynamic fill is flooding over other etch shapes within a symbol.
& V* |( \/ z' g2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present
5 _( Y& @9 U6 P; f" P8 B% Z2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in hotfix 048.: G8 h2 |) I2 Y( L
2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash
1 m/ P5 _8 [% F/ t, ]5 @1961689 ALLEGRO_EDITOR SYMBOL Pin Numbers are moved from center with Pin Rotation when adding pins to Footprint
" k- v1 b$ J+ ]! V* C: T( F* v2034949 ALLEGRO_EDITOR SYMBOL Angular dimension from DRA not created in PCB
$ _( W% x% Q% i1 m* e2046242 ALLEGRO_EDITOR UI_GENERAL Searching User Preference Summary results in crash
: i: F& o7 q5 Z/ O2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog box is behind canvas
/ ?6 P$ t9 J8 V7 B8 A* D1 \2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden# s0 \! l3 q, q; | d& [
1886781 ALLEGRO_VIEWER OTHER Opening Color192 in Allegro Free Viewer causes it to crash, ~* s/ g& V8 k. l& b
1699433 APD EDIT_ETCH Field solver runs when not expected" |7 V7 E) U D* E- K+ v
1937159 APD EDIT_ETCH Routing clines takes long time+ ]1 `' J3 t: ]
2050863 APD SHAPE Taper voiding process is different in Within the region/Out of Region
5 L7 x% F8 C& }' o2047391 CAPTURE PART_EDITOR Pin type cannot be changed in hotfix 051
$ O# v+ [# k9 u2 x3 z L) i- d2049161 CAP_EDIF IMPORT Fatal error 'cannot determine grid' when converting third-party design to Capture
1 N. @) i) B% z; E2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved
& o5 v9 M# i8 h" u! |2047583 CONCEPT_HDL COPY_PROJECT Design Entry HDL crashing when trying to open page 52 of copied project
: i7 ?( O9 F& p5 u1 W, M2036239 CONCEPT_HDL CORE When cutting/pasting, multiple error pop-ups appear for the same notification
% \" ^. X9 t) `2037572 CONCEPT_HDL CORE Warning (SPCOCD-578): Soft VOLTAGE property found is misleading and should be auto resolved when closing CM
/ W! r2 s$ [6 N5 Z: [) @2037578 CONCEPT_HDL CORE VOLTAGE property gets deleted after copying it from a non-synchronized source
! z% h* s5 c) W2046958 CONCEPT_HDL CORE Moving block pins from symbol right to left places pin names outside the symbol5 O9 r2 K \5 r( W S
2032480 CONSTRAINT_MGR CONCEPT_HDL Incorrect matchgroups created when working with multiple level nested hierarchical blocks
( g* v/ P: o6 K1 _2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor& T5 S9 W" T- k1 A
2046765 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout 'dump libraries' crashes when exporting library
9 ~" b: ~9 S8 F0 c1 R6 u2067970 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout cannot dump libraries, viewlog is empty
4 D$ O- v" ~2 N# J! m1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error5 d, O& a$ T k
1968437 SYSTEM_CAPTURE ASSIGN_SIGNAL Net name pasted in lower-case though UPPERCASE INPUT is enabled* {; z% q) v4 k
1983063 SYSTEM_CAPTURE AUTOSHAPES Auto Shapes are being shown as part of components: a2 Q' x8 I+ Q
1968463 SYSTEM_CAPTURE CANVAS_EDIT System Capture should not allow illegal characters to be entered for net names
4 G$ g+ O: v2 x* v: c P# c2006593 SYSTEM_CAPTURE CANVAS_EDIT Asterisk in a search string is not treated as a wildcard character
% } m( N0 W. v9 z1721863 SYSTEM_CAPTURE CONNECTIVITY_ Net Names move to random locations when the components are moved around the canvas E& b/ R+ t& x, N% k6 x
1960130 SYSTEM_CAPTURE CONNECTIVITY_ Disconnected nets when using the mirror option
: L* _$ E) k6 P: O) t2 C1985029 SYSTEM_CAPTURE EDIT_OPERATIO Net aliases do not drag with circuit, they appear to move after the circuit is dropped
1 V# x! x8 u6 U1895142 SYSTEM_CAPTURE EXPORT_PCB System Capture reports incorrect unsaved changes when closed after running export physical
" K# K S3 d8 e# p5 m7 `1628596 SYSTEM_CAPTURE FIND_REPLACE Alias issue in Find: Results do not show the resolved physical net names
" N4 X7 o A% O' V1988297 SYSTEM_CAPTURE FIND_REPLACE Edit > Find and Replace does not replace a net with an existing net on the canvas$ g% G3 v2 f- u4 h* a! C
1843885 SYSTEM_CAPTURE FORMAT_OBJECT Renaming a net causes it to lose custom color assignment' k2 H4 x3 H: i
1969308 SYSTEM_CAPTURE FORMAT_OBJECT System Capture: Clicking arrows to increase/decrease font size does not work correctly when clicked fast
. {9 z, K# m" P+ ^ r" |1990060 SYSTEM_CAPTURE FORMAT_OBJECT Bold, italics, and underline formats not visually shown on all selected objects concurrently
0 s1 H/ G, i2 }1993208 SYSTEM_CAPTURE FORMAT_OBJECT Setting font prior to placing text does not work, pop-up does not work, and bucket results in scrolling page
7 W0 C9 o& O' R+ |- p8 `8 c1981775 SYSTEM_CAPTURE IMPORT_PCB Import Physical takes a long time on some designs to launch the UI
4 A" u2 M9 ]( \/ H1 w: k1982320 SYSTEM_CAPTURE IMPORT_PCB In the B2F flow none of the *view files are created7 x9 N4 Q2 i: s M8 H1 T+ I# q
2010996 SYSTEM_CAPTURE INSERT_PICTUR Image in title block is at a wrong location in design: correctly placed in library
6 D" w' K' U9 h U" D2 V& J* Y/ g1967614 SYSTEM_CAPTURE MISCELLANEOUS Dragging a circuit with net aliases does not move the net aliases with it3 B) l+ E1 {; o* B& ^: ?
1980999 SYSTEM_CAPTURE NEW_PROJECT System Capture stops working with message regarding Part Manager initialization for a design based on DE-HDL) ]. E8 L; `" n& F/ v& `
1973437 SYSTEM_CAPTURE OPEN_CLOSE_PR Opening a design crashes System Capture
" |6 Z0 \9 c% }% m' R1986566 SYSTEM_CAPTURE OPEN_CLOSE_PR System Captures stops responding on opening project, cleaning project displays project already open message3 O6 [5 @% p6 G8 _/ B$ o7 n
1993093 SYSTEM_CAPTURE OPEN_CLOSE_PR Add option to override the lock file similar to Allegro PCB Editor
6 {& a: ~7 H5 n$ c9 ~; u2042360 SYSTEM_CAPTURE OPEN_CLOSE_PR System Capture will not open nor gives error message when previous lock file present inside the logic folder, d, q* [! V1 N* P% V6 D
1992247 SYSTEM_CAPTURE PART_MANAGER Part Manager displays message for undo and redo stack even after specifying not to show message; s. I5 p7 x& Q0 N9 h$ S# j+ U
2048000 SYSTEM_CAPTURE PERFORMANCE Performance issue when instantiating and moving a component
% S/ \( _7 s! O e8 U: n$ b* R1892120 SYSTEM_CAPTURE PROPERTY_EDIT Some parts missing reference designators and some have two properties, RefDes and REFDES
; f: z0 G. }$ N+ |1970009 SYSTEM_CAPTURE PROPERTY_EDIT System Capture: Right-clicking RefDes with conflict in 'Edit Properties' shows the Hyperlink option* V( a {4 X1 q0 `
2042707 SYSTEM_CAPTURE VARIANT_MANAG variant.lst file under 'physical' folder not updated when closing Variant Editor
3 v# `. i" @% A0 T0 `. w+ V6 e8 v& O- D! Z+ e( {2 X0 q; `" L
1 `' [9 f8 x: n, R( iFixed CCRs: SPB 17.2 HF052* c+ O7 d; v" k) d+ s
03-01-2019
! m: L4 U/ V+ n; f7 z========================================================================================================================================================" U5 g5 F7 f* N* Y" ~' d, I# y8 z7 R
CCRID Product ProductLevel2 Title; I" x: I* V y5 v7 q; Z9 a
========================================================================================================================================================1 p8 L3 s. \1 k7 M4 ~: h
2020429 ADW ADWSERVER Incorrect adwservice status on Linux
6 v g* I( w2 {4 R A. @2034815 ADW LIBDISTRIBUTI Cannot mark classification obsolete because it is associated to objects in the database
3 _& U. n- @2 [* f2015461 ADW PART_BROWSER New Component Browser should read the mapping of symbol and associated package as it results in error PKG-1005
, v j) |) E# p; T4 S5 z9 P2049380 ADW PART_BROWSER System Capture Import HDL not importing complete PTF File data* z# W2 Y& c0 s' Y6 ~# H& H$ ~
1948608 ADW TDA CUSTOMVAR directive value in project CPM was not updated by TDA UPDATE command.' n1 B# j# A/ v1 A! F9 v
1992662 ADW TDA Custom directive added to the cpm file not updated after check-in
% n$ h1 w, {. |$ G! F1733129 ALLEGRO_EDITOR COLOR 'Display - Highlight', double-click permanently highlights symbol9 W8 V8 H2 \! {" N: v
1861938 ALLEGRO_EDITOR COLOR Changing layer color changes layer visibility
( @" W' n4 b8 G: v2034753 ALLEGRO_EDITOR CROSS_SECTION Allegro PCB Editor crashes when a cross-section technology file is imported in Overwrite mode
5 m% Z0 T. ?. [) ?2036895 ALLEGRO_EDITOR CROSS_SECTION Replay script error during import of tcfx Xsection file
* Q$ L+ l* }/ `( @ U% d5 q8 N1929360 ALLEGRO_EDITOR DATABASE Via color is inconsistent on Vias with color assigned
! N" i1 ]6 }7 k7 d1984203 ALLEGRO_EDITOR DATABASE Drill holes not displayed correctly in the Zone area
! Z3 A3 g2 R5 r& B" D K2013596 ALLEGRO_EDITOR DATABASE Assigning net name on Vias does not change the Via Color to that on Net Color automatically
9 M' \: H( j: @7 Z0 O2025798 ALLEGRO_EDITOR DATABASE Assign net to via changes color of the via to the default color
: P7 j9 u q3 w6 d+ L2032678 ALLEGRO_EDITOR DATABASE Unable to delete layer on design
+ A |7 E j9 J" R2032725 ALLEGRO_EDITOR DATABASE Dehighlight removes color assignment from color dialog# X, E4 U1 x, }# N, u1 `
2029542 ALLEGRO_EDITOR DFA Interactive Placement with Manufacturing Package to Package spacing2 C3 i2 r0 [! U3 J
2020548 ALLEGRO_EDITOR DFM Cadence DFM Customer site cannot Submit Request6 z, h2 R# S4 E$ d3 S+ m6 M
2020566 ALLEGRO_EDITOR DFM Error when sending Design True DFM Rules Request
+ ]# F: H1 J1 t" G) i: y$ o2030179 ALLEGRO_EDITOR DFM Allegro PCB Editor .brd file will not save after routing using Automatic Router* x- }& K( e! q3 ]" j5 V
2052907 ALLEGRO_EDITOR DFM The Submit Request button for DesignTrue DFM Rules Request does not work! W, h# Q/ ~$ }# D1 X; F
1928915 ALLEGRO_EDITOR EDIT_ETCH PCB Editor constraint status bar does not match Constraint Manager data when z-axis delay is turned on.
! u* R0 C% c5 S! Q1932165 ALLEGRO_EDITOR EDIT_ETCH Arc slide behavior with clines at odd angles: notches on slides& X, q8 y; P% l0 ^
1943901 ALLEGRO_EDITOR EDIT_ETCH arc segment incorrect on slide.% n g5 H3 A ]
2031055 ALLEGRO_EDITOR EDIT_ETCH On drawing cline the width on a Layer is larger than defined constraint
* g* W! c! u% B3 c8 r; o4 {* B1877891 ALLEGRO_EDITOR GRAPHICS Allegro PCB Editor crashes when started from EDM for projects without a board file or empty master.tag file
, |5 s c! T; D1 C" C2 ]1 F2040689 ALLEGRO_EDITOR NC The decimal digits of a rotated oval padstack do not match the Drill Chart.
! \, b) [' \+ w9 }% l* e3 J) C/ |2028105 ALLEGRO_EDITOR PLACEMENT Delay in moving a large count pin symbol2 H: Y, q* O9 D
2019027 ALLEGRO_EDITOR REPORTS Information shown in the Report Viewer is not correct.
" j+ P K- Y7 j% \; g0 Y# M2022461 ALLEGRO_EDITOR SHAPE Abnormal termination of thieving function in Allegro PCB Editor6 N. ^) l. b" ?: B' F) w& Y; G
2032048 ALLEGRO_EDITOR SHAPE shape void difference from hotfix 026 to 048: need square corners for full round; n" K/ X& h' X+ R A
2040138 ALLEGRO_EDITOR SHAPE shape_rki_autoclip affects the overlapping shape boundary/ ~: ^8 O; L4 O/ l* H7 c, Q9 |
2040259 ALLEGRO_EDITOR SHAPE Same net shape and cline adds shape void around cline1 w3 ~0 p" Y1 _3 h& e
2031468 ALLEGRO_EDITOR TECHFILE Cross section import (.tcfx) not working correctly.
( l8 |3 F# M. t2006425 ALLEGRO_EDITOR UI_FORMS Option to disable 'Create a New Design' window in OrCAD PCB Designer P/ F& F- z# V) y# e- c
2007451 ALLEGRO_EDITOR UI_FORMS Option to suppress 'Create a New Design" window for File > Open in OrCAD PCB Editor from hotfix 048
0 [7 `( Y$ O4 L. T, ]4 h4 E2009314 ALLEGRO_EDITOR UI_FORMS Existing scripts that open OrCAD PCB Editor not working in hotfix 048
6 U! S/ t+ e* J7 A, _2021476 ALLEGRO_EDITOR UI_FORMS PCB Editor is slow when using the command 'add connect'
' F9 _& |0 B4 g4 a- N% a1 W, a- {2039462 ALLEGRO_EDITOR UI_FORMS Hovering over Default symbol height in Design Parameter Editor does not display a description
1 I( ?9 _7 i# q. W1808054 ALLEGRO_EDITOR UI_GENERAL Illegal value in axlFormSetField crashes PCB Editor
: p: H. K! t( C, Q0 D, x% I- D, l1822679 ALLEGRO_EDITOR UI_GENERAL 'Symbol pin #' field is truncated on rotating components in the Placement Edit mode
$ l+ |0 ^: a0 D6 K0 D7 f1856438 ALLEGRO_EDITOR UI_GENERAL Script recording messages not displayed in the PCB Editor task bar when using the script window.
B5 `( D9 X; H) X1879078 ALLEGRO_EDITOR UI_GENERAL Running PCB Editor from command prompt with '-product help' should list all products and options
) O5 f1 R! e2 _. j' n+ g" ]3 ?1944225 ALLEGRO_EDITOR UI_GENERAL Cannot close log file window till we close report dialog box& z6 J' K$ Q# P) q6 J( q
1967708 ALLEGRO_EDITOR UI_GENERAL New Command Window Shows Last Command in UI; n- S5 n9 d, J
1968380 ALLEGRO_EDITOR UI_GENERAL Write all open editing sessions in MRU
7 }+ _2 V0 Z0 X; t1982138 ALLEGRO_EDITOR UI_GENERAL axlFormListDeleteItem(fw field -1) not deleting last item of a list
2 T5 L9 ~# l" |5 [4 ?2003054 ALLEGRO_EDITOR UI_GENERAL Grids not shown when 'nolast_file' is set+ p1 L" a0 Z0 x6 ^3 y
2010760 ALLEGRO_EDITOR UI_GENERAL Pressing tabs is selecting only vias and not selecting clines in PCB Editor in hotfix 048
5 F4 e( r4 Q" h; C2019120 ALLEGRO_EDITOR UI_GENERAL Tab key is not working when there are two objects on top of each other
' e& U1 n' X+ Q" F2029248 ALLEGRO_EDITOR UI_GENERAL Colorview load is not working when using absolute path
/ E) t5 L8 C' j2030985 ALLEGRO_EDITOR UI_GENERAL The view of the PCB is offset after closing and opening the board.
5 a2 \" ^7 V2 p6 F) ~% B9 ^2037968 ALLEGRO_EDITOR UI_GENERAL Tab key will not cycle between cline elements. S+ u% Y5 s9 |. ` s5 P% Z& g
2015766 ALLEGRO_PROD_TOOLB CORE Advanced Testpoint Check does not work
# {% K) K! ?2 l- Z' z2023356 ALLEGRO_PROD_TOOLB CORE Edit new session does not work in quick symbol editor tool box% ]2 d8 G7 r/ \; n% n
2017162 CAPTURE CONSTRAINT_MG Cannot apply ECSets in Constraint Manager-enabled Capture# ?- L% m' w" L; H& @- x
2026777 CAPTURE CONSTRAINT_MG Cannot apply electrical CSet (ECSet) in Constraint Manager-enabled Design Entry CIS
6 u' Q. r% Q& l# {2027545 CAPTURE CONSTRAINT_MG Getting error (ORCAP-40320) while creating ECSet. \+ K3 |5 Q" M
2012967 CAPTURE OTHER Capture license is loaded slowly in hotfix 048
3 o! |! @ h2 k7 f5 J( _* N( T2010093 CONCEPT_HDL ARCHIVER Archive .zip file keeps the whole folder hierarchy and not only the project hierarchy
: n/ G [9 {) T' }! ?+ }2040431 CONCEPT_HDL EDIF300 EDIF300, Schematic Writer, crashes in release 17.2-2016: w$ x* T0 {0 P8 K# z8 s$ v
2034077 SIP_LAYOUT DFA DRC is not catching all Shape minimum width violations# h- d2 u( ^: G# o( ^: J! N9 V
2034094 SIP_LAYOUT DIE_ABSTRACT_ [VSDP-RDL Exchange] some traces are lost in SiP Layout
2 W. j( D: w$ c! D2037462 SIP_LAYOUT DIE_ABSTRACT_ Cline Segments are lost on saving and re-opening the design in next session
% `3 R7 }( Y9 B% e# b2025321 SIP_LAYOUT IMPORT_DATA compose symbol from geometry defaults need to change due to performance
/ W) l" L; S% z" M2 u- U7 \9 x2017759 SIP_LAYOUT PLACEMENT Placing a die creates extra place bound and puts pin numbers in the wrong place, causing future netlist import failure
1 M- o' H/ T2 D. z2021057 SIP_LAYOUT SHAPE Polybool assert error when adding dynamic shape prevents shape voiding.$ O3 @& ?8 G' O$ d8 k. ~" N/ A
2012381 SIP_LAYOUT SKILL Ability to check if the Dynamic Unused Pads Suppression box is selected using SKILL
5 ~0 w) E/ O0 h; d9 b7 Y( P3 J+ M$ Y2 W1990299 SIP_LAYOUT UI_GENERAL Pressing 'Esc' cancels DRC checking when there is no focus on the Allegro PCB Editor canvas; O* }1 L# F( G2 q5 ]# `
1997317 SIP_LAYOUT WLP Advanced WLP, Metal Density Scan does not correctly calculate scan region count in Y direction) t0 i0 a7 V9 \1 z& Z1 Q! |* s
2029524 SPECCTRA ROUTE SPECCTRA stops responding when executing the quit command, M0 Y# X9 |3 |' G, ?5 t% f) j# X
1670888 SYSTEM_CAPTURE CANVAS_EDIT Rotation error when connected to a power symbol
7 t5 Z a6 ^4 D- t) i& ?1880809 SYSTEM_CAPTURE CANVAS_EDIT Can modify only one RefDes from canvas for duplicate RefDes; can modify both from the Properties window
- N- G# v, N4 \% a1979063 SYSTEM_CAPTURE CANVAS_EDIT System Capture : File > Close is grayed out/ t) L+ h4 Y+ @ O/ h1 }" E+ S' q
2034498 SYSTEM_CAPTURE CAPTURE_IMPOR Cannot find parts via Find & Replace after importing Capture design
& I& M$ `: U0 v- u7 |# I1984561 SYSTEM_CAPTURE CROSSPROBE System Capture: Cross-probing from layout does not work when zoomed into a specific area on canvas
. V9 g1 N& I, w: H1863460 SYSTEM_CAPTURE DARK_THEME thumbnail preview of pages is in light them but dragging the page the previes is dark
0 ~ x: N1 I* @* _/ _- u2025876 SYSTEM_CAPTURE EDIT_OPERATIO Route failures when dragging a circuit, i, t. y1 L) _3 q& y
2005904 SYSTEM_CAPTURE FORMAT_OBJECT Pin name text is smaller in System Capture than in DE-HDL by about 25%
% B8 e* V; {* d+ j' p6 v. D. ^/ t2036782 SYSTEM_CAPTURE IMPORT_BLOCK Unable to import the block from project.1 f8 x1 `2 N2 s
2025949 SYSTEM_CAPTURE IMPORT_DEHDL_ Title block and thick wires/lines of border in DE-HDL do not translate in System Capture
5 o+ B3 U) Y5 A: b, B1 t+ K+ }' Q2025950 SYSTEM_CAPTURE IMPORT_DEHDL_ Broken connectivity on imported ground symbols
' N0 m, e- p* I% d/ J6 U; b2040923 SYSTEM_CAPTURE MISCELLANEOUS System Capture - Multiple Symbol Replace, disconnects and changes orientation
) x. D7 i) |9 _7 \2017526 SYSTEM_CAPTURE NAVLINKS Page information missing in NAVLINKS
3 n& {7 H- P0 G7 e( O% G5 ]2015346 SYSTEM_CAPTURE PAGE_MANAGEME Rename page fails in some cases
$ @6 b' w& S( [! r+ T% g2 G3 @. U+ @2038811 SYSTEM_CAPTURE PRINT Black & White PDF showing colors) M. N b1 N1 D' g, L1 C" \/ D, V
2048493 SYSTEM_CAPTURE SYMBOL_GEN Symbol Editor, Modify outline adds an 'X' in symbol incorrectly5 S( n+ ]# o0 j7 e1 s/ ~8 y$ E
2031995 SYSTEM_CAPTURE VARIANT_MANAG Variant Editor does not load the design and restarts the machine after sometime.
2 K- X' d/ ~' R6 E ~ ?7 C( T2032005 SYSTEM_CAPTURE VARIANT_MANAG Custom variables not saved for variants
1 h. M) i" f& f8 r2 r8 b5 `1968431 SYSTEM_CAPTURE WORKSPACE Unable to reorder the pages (tabs) when opened in the workspace
5 ]8 \& p* ~- a$ S' R/ }" ^2040995 XTRACTIM GUI Running XIM from APD enables "skip DC R simulation" by mistake
& p" C& l8 a8 r1 k( w" c8 H% d# S" a( k }0 F) [2 j
( p, w) o* l- j8 y( mFixed CCRs: SPB 17.2 HF051, s' L4 p% b' c3 a! A# b9 ^; X8 P/ u
01-30-2019
% i) ]8 J1 ~0 b- ?========================================================================================================================================================
' S" K: ~* j8 s8 ]/ S& mCCRID Product ProductLevel2 Title
' o3 [$ {" W C, i! z' e4 X========================================================================================================================================================. z0 W5 p4 O# B* Q
2015843 ADW LIBDISTRIBUTI Error for library distribution (lib_dist_client) regarding string index out-of-range) \. h# `6 T8 U* }: U' `: r' J
1869914 ADW PART_BROWSER Adding components to System Capture schematic canvas takes long time in Linux clusters: c9 P1 b2 U P& W1 D' c
2010458 ADW PART_BROWSER RefDes values not appearing on parts
: c- j& i; Z% \5 P( O! _5 }2022630 ADW PART_MANAGER Unable to successfully import a DE-HDL Design into System Capture
4 ^" {1 |7 r5 k2005033 ALLEGRO_EDITOR 3D_CANVAS 3D Flex issues: Error message when opening design with bends in 3D viewer0 t8 Q1 f( R0 b
2023496 ALLEGRO_EDITOR 3D_CANVAS Error for designs with bend in 3D Viewer
0 ]$ c5 z, o% u* S8 z2033459 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation
9 w3 i6 J, }5 p( `0 c1996431 ALLEGRO_EDITOR ARTWORK Via holes for connection have incorrect coordinates in Gerber% k, x8 u- C: h0 T& ^
1995656 ALLEGRO_EDITOR DATABASE Attaching and Detaching a text file created with SKILL writeTable() function corrupts the text file+ W `" g' f/ E! i
2027122 ALLEGRO_EDITOR DATABASE PCB Editor crashes when creating Place Replicate module+ q$ r" ^) x! b' [; s/ u, [* b! m
2023916 ALLEGRO_EDITOR DFM DFF Annular Ring: Thru via pad to Mask violates on via in pad instances.) Q& D" B. E' O1 S
2024523 ALLEGRO_EDITOR DFM PCB Editor crashes in Mask To Trace check of DFF.
6 t" r, n I/ ~# \6 \# [2021318 ALLEGRO_EDITOR IN_DESIGN_ANA Integrated Analysis and Checking: Unable to run simulation with Crosstalk flow- V' F+ M! V% `1 v- J
2014162 ALLEGRO_EDITOR NC Backdrill results using an OrCAD Professional license showing wrong values with hotfix 0486 c! ^( l6 K: m- ~
2010791 ALLEGRO_EDITOR PLACEMENT Setting dfa_pause_level to 3 and then moving and rotating part places the part with offset
) [" L0 V6 O7 P; R% t6 T5 K2017112 ALLEGRO_EDITOR PLACEMENT place_boundary shown at wrong location when moved with User pick and footprints rotated: v q5 Q W% n5 r# g" Y) E
2028048 ALLEGRO_EDITOR PLACEMENT Rotate option using pick is rotating the outlines in different axis in view, u2 ]8 _0 _% z- u9 ~; y
2028314 ALLEGRO_EDITOR PLACEMENT Crash on moving components in Allegro PCB Editor6 Z8 W& D T+ P- X
2029235 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes when moving more than one component and hovering on IC7 b9 g$ {, ^+ H$ a: C T* N, B
2022644 ALLEGRO_EDITOR SHAPE dv_fixfullcontact obsolete in release 17.2-2016 ]+ J4 V- n( T% U3 e
2023322 ALLEGRO_EDITOR SHAPE Gloss does not add teardrops on all clines.
) X! U' N6 a/ P# q2024235 ALLEGRO_EDITOR SHAPE Copper Pour disappears when area includes parts
- c. R- W: F' X W. s9 L2024531 ALLEGRO_EDITOR SHAPE rki_autoclip is not working at a special XY location( T* y) U! {- _2 U! ^+ K& k
2024599 ALLEGRO_EDITOR SHAPE Cannot create round corner for shape
8 q! k* A4 c$ S# K8 j9 k2024707 ALLEGRO_EDITOR SHAPE In-line void control does not work when there is no_shape_connect property attached
0 z" {0 d( L2 P# l& q D% l. t2026849 ALLEGRO_EDITOR SHAPE Cannot assign region name using the 'next' operation
8 O7 I, Z1 X: D: [7 I7 C; v- Z2030156 ALLEGRO_EDITOR SHAPE Shape Area report for cross-hatched shape includes hatching and boundary
- {6 u0 J% c, S; x9 x1852981 ALLEGRO_EDITOR SKILL Error message while creating Copper Mask layer without a name using SKILL not clear
$ A: i# x: d6 z7 g# P1968054 ALLEGRO_EDITOR SKILL Document of axlClearObjectCustomColor should indicate that it can clear color for DBID of Net
# X" o5 [2 h9 g0 W" W2026429 ALLEGRO_EDITOR UI_FORMS PCB Footprint wizard: horizontal and vertical lead pitch level reversed in the image
* _0 ]" n; m3 M# l5 A6 b1 {2 V1768032 ALLEGRO_EDITOR UI_GENERAL Numeric keypad does not work for file selection shortcut
5 I9 q) F# K3 A; c; {. _4 V N1797376 ALLEGRO_EDITOR UI_GENERAL Release 17.2-2016: Padstack Designer saves padstack to the working directory when script is used @' j4 u$ `9 D6 |2 `
1798524 ALLEGRO_EDITOR UI_GENERAL Unable to save a padstack using script. r E$ q+ d9 Z; I" V
1823031 ALLEGRO_EDITOR UI_GENERAL Help not working for OrCAD Productivity Toolbox7 c% ^% M) L! x' U
1849921 ALLEGRO_EDITOR UI_GENERAL Analyze menu missing in OrCAD PCB SI: Q8 ~; t: o% i Z
1951740 ALLEGRO_EDITOR UI_GENERAL Trigger for 'open' does not work when opening a .dra file0 j" G1 w& N; d
1952163 ALLEGRO_EDITOR UI_GENERAL Analyze menu missing in OrCAD PCB SI( W, B5 `* X% O% C* D0 l
1982966 ALLEGRO_EDITOR UI_GENERAL SKILL command to access the Option window fields while in Interactive commands.. R0 a B! P' b( I8 \) o
1983567 ALLEGRO_EDITOR UI_GENERAL Alias with Ctrl not working with 'command window history' variable enabled2 E0 z2 L0 w6 M r2 K% h
1989507 ALLEGRO_EDITOR UI_GENERAL Third-party tool causes PCB Editor to stop responding to command7 T" W6 p4 f/ u* _
2003511 ALLEGRO_EDITOR UI_GENERAL Aliases using control (tilde) characters stopped working after upgrading to hotfix 048* y) q9 Z0 S3 }4 r
2010418 ALLEGRO_EDITOR UI_GENERAL New command window breaks funckeys5 Z N+ Q6 W. g# j% O7 E. O, F
2018201 ALLEGRO_EDITOR UI_GENERAL SKILL axlDBControl ('activeLayer /') updates active class/subclass but ministatus form not updated
: \/ ] f7 R9 a3 q% `2023468 ALLEGRO_EDITOR UI_GENERAL axlZoomInOut does not zoom out, always zooms in regardless of zoom factor (positive or negative)( q' t$ T! C9 T6 \
2026428 ALLEGRO_EDITOR UI_GENERAL PCB Editor takes several minutes when saving a design
! I# t. O9 T5 v; ?, i3 K& L/ Y+ b2032697 ALLEGRO_EDITOR UI_GENERAL Funckeys with Ctrl not working with 'command window history' variable enabled
4 u) ^1 M- P9 ^# u' Q4 Y3 E _4 ?2032717 ALLEGRO_EDITOR UI_GENERAL Funckey combinations, such as Ctrl + M, not working
+ u1 t q2 ?1 ?9 q- H, |2014211 ALLEGRO_VIEWER OTHER Arrow keys are not panning in Allegro Physical Viewer
( t3 \' S$ u4 ?: Y* g% v% `2039081 CAPTURE NETLISTS Netlist not created: netlist fails for numeric pin names with backslash '\'; \" @* Z" h5 V2 a2 c
1993057 CONCEPT_HDL CONSTRAINT_MG Constraints disappear in hierarchical design (Electrical->Net->Routing->Relative Propagation Delay)+ N0 X7 X; R. D& Y# \; N: O; }
2004641 CONCEPT_HDL CONSTRAINT_MG 'Save Hierarchy' (hier_write) deletes bus object in Constraint Manager, q. q& ?5 B& z/ i+ {+ u0 b
2020901 CONCEPT_HDL CONSTRAINT_MG Incorrect match Groups created in CM (TDO design)
+ s8 ], Y, n5 G7 F @* s2014979 CONCEPT_HDL CORE The active schematic page randomly changes while editing text- D# y2 _- [! j- U0 Z
2027905 CONSTRAINT_MGR DATABASE Pin Property changes in CM during uprev to release 17.2-20167 k" n' D0 p$ v) u. C
1762263 ORBITIO INTERFACES Add set allegro_orbit_import variable to user preference7 Z/ u9 u4 @0 N5 q$ R7 P
2005860 PSPICE LIBRARIES Error when simulating design with TL494 part in release 17.2-2016! K7 G- H7 J k& _5 B4 M, d# O
1980072 PSPICE SIMULATOR Noise in the waveform when using DELAYT and DELAYT1 with capacitor) ]9 l% h( q9 t& z( a V
1977615 RELEASE INTEGRATION Cannot import third-party schematics into OrCAD Capture in release 16.60 p3 ^1 A$ H' J
2027009 RF_PCB SETUP 'RF-PCB' - 'Setup' changes not saved on Apply
' f# Y$ `8 J3 v2002040 SIP_LAYOUT MANUFACTURING IPC 356 'ignore die layers' does not work: netlists to die; w% B8 W4 L1 U3 ]+ z' b$ w
2024703 SIP_LAYOUT WLP Cannot Add Pin Text: Error on 'Manufacturing' - 'Documentation' - 'Display Pin Text'
; M* i0 R) E8 U8 x2010045 SYSTEM_CAPTURE CANVAS_EDIT Cannot snap back vertical CAP until moved up and down horizontally" T: H. r6 G8 U0 _7 j, f: _$ h- p
2010443 SYSTEM_CAPTURE CANVAS_EDIT Cannot select the CAP part, a7 C% J3 i5 T2 S
2012843 SYSTEM_CAPTURE PACKAGER Cannot short two grounds in the schematic
$ w9 G: v) b1 F1 ?3 j2015574 SYSTEM_CAPTURE PACKAGER System Capture is treating quotes in PTF files differently from DE-HDL% t; e8 t# ~4 e; _
2022653 SYSTEM_CAPTURE VARIANT_MANAG Variant Editor - Allow Alternates where ALT_SYMBOL is a valid match for JEDEC_TYPE
! r/ ~, d% A2 F' W( n" z2024742 TDA SHAREPOINT Accessing projects is taking time
' W4 ?$ g9 D/ U" l2010531 XTRACTIM OTHER Allegro crash on repaint of command window/ N7 W8 z5 d# `. C5 D( B( p
2022351 XTRACTIM OTHER XtractIM is crashing the latest HF S049
0 L, B- M5 F* R5 i( r7 Y6 @
% Y) i1 ]: \0 p( {2 g. ?
$ F: D8 Y' d( ]. W, T/ @# YFixed CCRs: SPB 17.2 HF0508 q6 f3 d3 R1 B& g2 `1 B# p w
12-23-20184 ]5 `) [0 F/ c" {
========================================================================================================================================================4 d" H+ r( H) c9 m/ q5 q
CCRID Product ProductLevel2 Title _9 V* L' k* A7 G( f
========================================================================================================================================================1 J6 Y/ S$ T8 S; j2 m
2012119 ADW ADWSERVER Cannot connect Component Browser to server
@ ^. c2 m$ D D! W1998856 ADW ADW_UPREV adw_uprev fails and a typo in rule name) U* U, v( k3 d3 c
1673333 ADW CONF Configuration Manager stops working and gives Java Timer-1 Error
) y T$ t7 ^& W4 q' H3 m0 }% p1900342 ADW DBEDITOR 'Link To' on a schematic classification attribute does not work with linked attributes containing parenthesis
9 p; a5 n+ i8 Z& j1997516 ADW DBEDITOR DBEditor stops responding on changing attributes. |3 D1 C3 f) U) V3 E" P# O
1986292 ADW LIBDISTRIBUTI Some parts are not updated in the part table in all_noauto and ini_noauto (restricted_sites).% J) C2 [* Z. N# T/ z4 D
2010460 ADW PART_BROWSER PKG-1002 error when opening a DE-HDL design4 }! Y. c1 E% Z1 G( o: y$ n
2013430 ADW PART_BROWSER Add component is inactive if WB_SHARED_RESOURCES is not pointing to the installation directory( z8 }% Y. P! o! h9 b- Q6 |9 U
2022806 ADW PART_BROWSER PKG-10005: Cannot package the following primitive instance in any section of the physical part
3 P5 b# c0 z6 y- p2006528 ADW PART_MANAGER Part Manager does not update parts when Key PTF property value changes
6 ]- F) C% B* |7 ?1980397 ALLEGRO_EDITOR DATABASE Mechanical pins with route keepouts (RKO) not updated
& a# F+ n: u; [& c; f1988171 ALLEGRO_EDITOR DATABASE Backdrill clearance Keepout is not applied consistently: n ?: A6 e9 p8 J0 M4 \
1994280 ALLEGRO_EDITOR DFM PCB Editor crashes during Unplace component8 s' N$ Q0 Z) ]! g' ]
2012742 ALLEGRO_EDITOR DFM DFT for testpoint to outline not showing DRC( e, t( q) Q9 o
2002680 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes on choosing Add Connect for two selected nets
5 ]8 m) T/ q& r% c' \) O8 n2004597 ALLEGRO_EDITOR EDIT_ETCH Illegal BMS Identifier error when copying multiple via structures- c) l" F; J8 C, R8 i$ s
2004929 ALLEGRO_EDITOR EDIT_ETCH Net with physical pin pair constraints is using incorrect line width when routed
; ^/ M1 g- ~ |) I2008314 ALLEGRO_EDITOR EDIT_ETCH Adding nets in tabbed routing crashes PCB Editor$ t/ X4 H% `$ r
2018710 ALLEGRO_EDITOR GRAPHICS Using the mouse to zoom by scrolling stops working randomly' n# i) k# Q* o: j
2018841 ALLEGRO_EDITOR GRAPHICS Canvas does not regain mouse focus after working in the Options pane in hotfix 0497 h1 G9 I" a H
2019482 ALLEGRO_EDITOR GRAPHICS Canvas does not regain mouse focus after working with the Options pane in hotfix 049 on Windows 7
. P3 F+ l& [5 s: F8 m# Y' E2019864 ALLEGRO_EDITOR GRAPHICS Using the mouse scroll button to scroll the canvas: focus is in the Options pane: ]; ?( Q8 u; u2 Z' }- K
2020750 ALLEGRO_EDITOR GRAPHICS Zoom in/Zoom out scroll does not work w8 g% s q4 I% r8 w
2020847 ALLEGRO_EDITOR GRAPHICS Scroll up/down key focus remains in command screen even when canvas is selected
( }. ~% F% ]2 D4 W! M+ s# Y7 s9 v1908812 ALLEGRO_EDITOR INTERACTIV Tools > Design Compare command does not work on Windows: L* P! D2 A- a' J
1995846 ALLEGRO_EDITOR INTERACTIV When there is an embedded component, the result of Metal Usage report is incorrect.
& O2 C0 M2 H( L: a: y! h& V- I3 C2011449 ALLEGRO_EDITOR INTERACTIV Command not found error (_impvision) for Impedance and Return Path DRC visions2 k- _2 x; O; F( q
1982867 ALLEGRO_EDITOR INTERFACES DBDoctor displays error for objects outside extent that cannot be fixed because the extents cannot be increased
. [ T- @# t; `1983177 ALLEGRO_EDITOR INTERFACES PCB Editor crashes when reading IDX file. O8 r& k% l" r, i$ n- }% G) v% q
1985623 ALLEGRO_EDITOR INTERFACES STEP model not exported from PCB Editor; Z' K$ ^/ \- m/ P
1994855 ALLEGRO_EDITOR MANUFACT Drill legend with counter-bore: legend size not uniform when database set to inches9 o' Q7 ~8 O, J
2001355 ALLEGRO_EDITOR NC PCB Editor crashes with NC route parameter! k9 { k. Q' @7 w- I/ c
1753414 ALLEGRO_EDITOR OTHER Ability to add Rigid Flex class in a format symbol0 w# S w+ C! A: k7 q9 o
2004786 ALLEGRO_EDITOR OTHER Legacy menu option missing in OrCAD Professional; s0 I0 _2 [9 b/ C+ t
1949695 ALLEGRO_EDITOR PADS_IN Third-party to PCB Editor translation does not make a clean conversion5 a; I( |; V$ \1 X5 ]
1949658 ALLEGRO_EDITOR PLACEMENT SKILL module creation issue: subsequent runs rotate module incorrectly
( H3 _) }0 ~0 r' Y$ h2001496 ALLEGRO_EDITOR PLACEMENT Constraint Region not replicated as part of the Place replicate apply command1 V4 U. H1 a: R& [0 Q2 x
2002989 ALLEGRO_EDITOR PLACEMENT Default rotation point is set to 'User Pick'; }8 N5 H% ]# g1 B
2007301 ALLEGRO_EDITOR PLACEMENT DFA boundary is shifted when moving components with User Pick8 ]/ }0 z* J9 a, ~7 S4 d/ C5 e
2007312 ALLEGRO_EDITOR PLACEMENT DFA boundary is shifted when moving components with User Pick) ~( X' Z0 F& [: J% V* }
2008098 ALLEGRO_EDITOR PLACEMENT DFA boundary shows a shift if anchor point is set to 'User pick'
% P4 _' c* N9 a3 K& Q9 l/ [0 ?2009085 ALLEGRO_EDITOR PLACEMENT DFA boundary is shifted when moving components with User Pick
- K L0 x7 Q4 Q/ W2009090 ALLEGRO_EDITOR PLACEMENT DFA boundary is being offset when moving components with User Pick* T; T( r0 Q& E7 g- u7 z
2009580 ALLEGRO_EDITOR PLACEMENT Component outline offsets during move process
9 {" o8 Z( a- `2010726 ALLEGRO_EDITOR PLACEMENT Two images appear when moving component in release 17.2-2016, hotfix 048
9 y8 ]- b0 ]- Z+ \% o. r5 R: p: \2010819 ALLEGRO_EDITOR PLACEMENT A separate outline appears when moving components using User Pick
& V; `+ z) q, P, ^2011454 ALLEGRO_EDITOR PLACEMENT DFA boundary is not centered correctly on moving components# \2 ~9 v7 ]' z9 @. p z( L* k
2011497 ALLEGRO_EDITOR PLACEMENT DFA boundary shifted from the part when moved# f3 Z* B3 k$ d) R
2014250 ALLEGRO_EDITOR PLACEMENT Moving a symbol using the 'User Pick' causing an offset image of the symbol outline getting attached to cursor
- i* V4 I1 h! g5 Q3 W2015676 ALLEGRO_EDITOR PLACEMENT Strange end-to-end DFA checking: offset of DFA from component when in user pick2 h( \1 R( C$ k/ c: w
2016421 ALLEGRO_EDITOR PLACEMENT Fail to place symbols because definition is incompatible for attribute 'PW_GENERATED'- f3 ?2 p$ t8 V0 H7 v
2016452 ALLEGRO_EDITOR PLACEMENT Some symbols cannot be placed due to property definition differences ?+ ~! _8 S; U) ?6 S( @
2016527 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes on moving all components on board
3 s- P& H \* ]. v* \2017364 ALLEGRO_EDITOR PLACEMENT Strange behavior when moving component: DFA or place bound area is centered around the User Pick position
+ j* d* \4 B: C, s2018859 ALLEGRO_EDITOR PLACEMENT Moving parts by 'User Pick' or 'Sym Pin #' shows two component placement boundary outlines
6 G4 o& T* f; H/ K V1 E6 u* V6 W2019364 ALLEGRO_EDITOR PLACEMENT PCB Editor stops responding when moving components
$ i2 q, U$ m) h# |0 e: l2019478 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes when moving more than one component across the design
- g4 N0 F- f1 E2 M# F8 m2019624 ALLEGRO_EDITOR PLACEMENT DFA Boundary is offset from definition when moving symbols with user pick
% z# R2 ?/ j# Z$ K E, d2021625 ALLEGRO_EDITOR PLACEMENT Graphical Issue with Edit - Move and User Pick: additional outline image shown6 J2 i( O) A; K' h
2022203 ALLEGRO_EDITOR PLACEMENT Place bound outline is shown at the center of the pick when moving a part by User Pick
/ D9 m8 ?) X2 Y9 y2024655 ALLEGRO_EDITOR PLACEMENT Moving multiple components causes PCB Editor to crash, A6 {$ a9 L" E) ]7 V
2025895 ALLEGRO_EDITOR PLACEMENT PCB Editor stops responding when multiple symbols are moved and on getting too close to another symbol; Y' e1 o8 |1 t( W1 q! p- R" k
2004497 ALLEGRO_EDITOR SHAPE Automatically deleting antenna shape is not deleting thermal reliefs associated with those shapes
3 J$ N! W! m$ P2 E2007832 ALLEGRO_EDITOR SHAPE Cannot void shape properly after rotating symbol6 @1 u3 }; ]% N
2009601 ALLEGRO_EDITOR SHAPE Error for shape created using third-party SKILL utility1 A# I* g! e4 E2 d3 W N$ K
2010924 ALLEGRO_EDITOR SHAPE Dynamic shape does not void in route keepout areas
- A& D- e3 P8 M8 \( T0 H4 d6 [7 P( S( Q2011176 ALLEGRO_EDITOR SHAPE Nothing happens on choosing 'Shape- - Change Shape Type' in Allegro Sigrity SI% y6 r8 s a# K0 j9 p9 o& B* h
2015446 ALLEGRO_EDITOR SHAPE Thermal relief connection created for static shape covering pin when inside a void in a dynamic shape.8 ~1 f' l+ h4 k0 ?) [
2017273 ALLEGRO_EDITOR SHAPE Same net spacing does not void properly for shape to hole." \; R8 J0 Z. n. Y
2012878 ALLEGRO_EDITOR UI_FORMS Custom toolbars cannot be loaded as size differs for customState and customExteded in registry, E) o/ {' T2 `
2018177 ALLEGRO_EDITOR UI_FORMS Custom toolbars cannot be loaded as size differs for customState and customExteded in registry1 s5 x8 u% Z' C$ X
2019437 ALLEGRO_EDITOR UI_FORMS Custom toolbars cannot be loaded as size differs for customState and customExteded in registry, P5 z0 L6 p$ T4 c2 L
2020491 ALLEGRO_EDITOR UI_FORMS Cannot load custom toolbars because the customState and customExtended Windows Registry entries are incorrect6 {' e% b5 d' f( G
1897843 ALLEGRO_EDITOR UI_GENERAL Function Keys, such as F3, F6, and F7, are not working if tool is idle for some time
: l1 \4 t) T3 p4 ?2000445 ALLEGRO_EDITOR UI_GENERAL Funckeys not working in hotfix 048 with the new Command Pane as default& D/ _8 G, i! N0 F- G
2001847 ALLEGRO_EDITOR UI_GENERAL Ctrl related funckeys not working in hotfix 0480 T M3 Z! o* v8 J' ?! l1 G
2008112 ALLEGRO_EDITOR UI_GENERAL Funckeys using Ctrl and Shift do not work in hotfix 048 (QIR 7)/ B @7 j( N; e1 u* X: `- X
2010370 ALLEGRO_EDITOR UI_GENERAL Shift + arrow key does not move component in release 17.2-2016, hotfix 048% l- ]0 Y) I6 n4 N+ q- ]5 C
2015418 ALLEGRO_EDITOR UI_GENERAL Funckey not working
( U y2 q% _5 |" t' X) P2 W2015443 ALLEGRO_EDITOR UI_GENERAL Text does not regain focus even on clicking after using a drop-down menu
z; n$ N1 ^# l: [: Q2016899 ALLEGRO_EDITOR UI_GENERAL Dynamic zoom and funckeys are disabled after clicking a combo box in the Options pane
" N. x, X' c6 ?9 {% F2019753 ALLEGRO_EDITOR UI_GENERAL Infinite Cursor disappears regularly in hotfix 049 when infinite_cursor_bug_nt is set' b8 G( q' Z( c$ Y6 c! p1 S, ~
2019990 ALLEGRO_EDITOR UI_GENERAL Mouse over does not highlight pin, need to click1 a! L' Y# [% o
2020162 ALLEGRO_EDITOR UI_GENERAL Funckeys not working in hotfix 049: pressing F4 not running Show Element
. d K+ j) c, O: l5 S1 M2020168 ALLEGRO_EDITOR UI_GENERAL Data tips not shown on mouse hover( \+ W- R+ I* U7 H" j
2020840 ALLEGRO_EDITOR UI_GENERAL Page-up/Page-down (remapped to zoom-in/zoom-out) stop working until mouse scroll button is pressed
7 K7 P& c* y! [7 O$ x2021416 ALLEGRO_EDITOR UI_GENERAL New user interface does not shift input focus and zoom in/out does no longer work in layout window) K1 L3 _7 o5 E& y- i+ ~) |7 s
2022185 ALLEGRO_EDITOR UI_GENERAL Ctrl related funckeys are not working
6 L. h" T- Y% N% B" N# q2023402 ALLEGRO_EDITOR UI_GENERAL During Add text, focus does not move from the subclass dropdown to the canvas.
# Y: v T/ `" B8 H2 F8 g2025806 ALLEGRO_EDITOR UI_GENERAL Function keys and shortcuts not detected8 u' B8 P9 P+ R( e Q' c Z
2027581 ALLEGRO_EDITOR UI_GENERAL Funckey problem: focus lost from canvas on using another window. b( g# [' |# |) q- ]) }
2009382 ALLEGRO_EDITOR ZONES When deleting zone by Zones - Manage, the shape in zone is out-of-date
?, B) v" b% q" V3 e- P1977211 APD DXF_IF APD: die pads shift after export DXF
& F' i: ^* ~" c' z. H2018483 CAPTURE NETLISTS Error when extracting netlist from schematic (ORNET-1193)+ N8 l$ C2 P( ~& l
2022764 CAPTURE NETLISTS Schematic will not generate pstchip.dat file+ K! L, y, O0 k. C7 z
1921557 CAPTURE NEW_SYM_EDITO Zoom to region option grayed out; R- u0 P @( }% ?8 q7 i. _
1945203 CAPTURE NEW_SYM_EDITO Symbol Editor: No Zoom to Region and cannot edit Pin Type and User Pin Properties for multiple pins* C' l" \& L, O. D( z
1950178 CAPTURE NEW_SYM_EDITO Ability to remove convert view of a component
& \" g6 a" a' J$ E3 P1966792 CAPTURE NEW_SYM_EDITO JavaScript error on trying to edit pin name for GP08 c* K8 r/ U5 A3 e6 T% ^8 ~
1969099 CAPTURE NEW_SYM_EDITO Cannot add convert view after creating a part
; q% g* K. v$ h4 Z" C1969834 CAPTURE NEW_SYM_EDITO Shapes not mirrored around center if more than one shape selected in Symbol Editor- d& p( z. y3 x) J$ }
1970984 CAPTURE NEW_SYM_EDITO New part is getting Numeric Numbering automatically }& D0 c5 b: E2 \% [( k* a
1972607 CAPTURE NEW_SYM_EDITO New Symbol Editor: name cannot be edited unless value is entered for a new property2 @+ w8 q9 s5 N( i
1972635 CAPTURE NEW_SYM_EDITO New Symbol Editor: wrong listing of Symbol Properties in right pane- n. C0 q( x3 Y8 G f9 Y
1974296 CAPTURE NEW_SYM_EDITO Design Template font settings are not being honored for new library/part creation
5 W+ [% j4 X7 S$ G5 p7 s1 a. E& R- q1982783 CAPTURE NEW_SYM_EDITO Part Editor is blurry when zoomed out.0 K6 s; Z+ U! R- \" i
1993361 CAPTURE NEW_SYM_EDITO Cannot change part numbering, set to Numeric by default7 z1 n8 b+ Q8 V
2003749 CAPTURE NEW_SYM_EDITO Cannot save edits to hierarchical blocks in new Symbol Editor in hotfix 048
4 ]* q a; S6 P2 m! E0 h8 W' k2004395 CAPTURE NEW_SYM_EDITO 'Pin ignore' modifications not saved in new Symbol Editor 'Edit Pins' after hotfix 048+ x7 G" C9 C8 W. H( K
2007747 CAPTURE NEW_SYM_EDITO Cannot add Convert View after creating a part
0 n) h& d8 J% M9 A$ Q. p" g! |2011321 CAPTURE NEW_SYM_EDITO 'Place - Picture' is not working for blocks in hotfix 048" Q' d/ E2 Q: o" `
2013146 CAPTURE NEW_SYM_EDITO 'Part Edit' not updating changes in hierarchical block: D- V; Z/ V6 C" ^. j: I$ b
2002904 CAPTURE OTHER Unable to check out Capture license in release 17.2-2016, HotFix 048' f$ R0 C! L* [% f7 ` K* [. C
2002922 CAPTURE OTHER Unable to check out Capture license in release 17.2-2016, HotFix 0482 P& O" c. n9 ~1 {
1988812 CAPTURE PART_EDITOR Parts created or edited with hotfix 038 Part editor do not use default font size1 K4 o& n3 E- ?. ?+ R
2008912 CAPTURE SCHEMATIC_EDI Design Compare shows 'NaN' in the graphical output& E; u. G! }* b
1985701 CONCEPT_HDL CHECKPLUS Library symbols are missing from the examples folder
& c' G" F$ ?+ H* u3 J$ I$ p1 S1933789 CONCEPT_HDL CORE honor_sch_custom_texts' m; J5 @& g/ S/ I* M$ j' e
1933892 CONCEPT_HDL CORE HONOR_SCH_CUSTOM_TEXTS& ~% Q! P! p9 T6 g9 h3 F
2001737 CONCEPT_HDL PDF DE-HDL crashes on choosing File - Publish PDF
3 [! {4 V: W$ _1 M7 @% G2010508 CONSTRAINT_MGR CONCEPT_HDL Schematic data corrupted on reading the data from CM database using the CM SKILL APIs/ Q. V0 N1 k& T9 d! L
1997461 PSPICE AA_FLOW 'Edit PSpice Model' from 'Assign Tolerance' window does not work1 v& X7 F O1 O% E8 ~) C2 U: p8 f+ d
2005948 SIP_LAYOUT DIE_EDITOR CTE expansion tool shifts pins off the die0 ?8 Z( ?/ _. |. D
1893045 SIP_LAYOUT INTERACTIVE Refreshing bond finger labels causes all the labels to shift location
7 I! }& W' R/ M! _: @; b' n2006926 SIP_LAYOUT ORBITIO_IF Bundle translation from OrbitIO is incorrect
9 ?4 _, T' Q& _. o' `" B% w6 ?! t2006659 SIP_LAYOUT SHAPE Cannot form fillets inside a shape in hotfix 048, U0 F/ W% ]; b9 L6 r5 E
1969192 SYSTEM_CAPTURE CANVAS_EDIT Pin Numbers of Discrete Symbols visible% L) R+ r' J1 z2 d' R# Z' c# v% Y
1982368 SYSTEM_CAPTURE CANVAS_EDIT System Capture switches to Auto Pan, even if the option is disabled, in the Notes mode
& n1 q( Y6 d4 }2 v0 j+ q: S1995012 SYSTEM_CAPTURE CANVAS_EDIT Connect lines do not move with components6 e* {- T8 E% ` B8 r8 X
1907992 SYSTEM_CAPTURE CONNECTIVITY_ Draw stubs is not respecting stub length setting.
2 W+ z+ Y9 v7 Q1960100 SYSTEM_CAPTURE CONNECTIVITY_ Moving components after routing failure: connect lines do not move resulting in disconnected route# q: b3 i2 Z2 N; A8 `5 F: Z
1988284 SYSTEM_CAPTURE CONSTRAINT_MA Log files and topology files are being stored at the top-level design (CPM) folder level; _9 j: t8 Y1 d! @: q. x' Z
1996039 SYSTEM_CAPTURE COPY_PASTE Cut and Paste change the pin numbers for connector after saving design.6 f$ r B: g! [- |, Y4 `7 H
1951700 SYSTEM_CAPTURE EXPORT_PCB System Capture: Export Physical - Change Directory UI entry block not displaying properly3 r) [0 w' e" z! r/ f {
1970761 SYSTEM_CAPTURE EXPORT_PCB Cannot import System Capture netlist if PCB Editor is launched with -proj argument
: ^/ }. v; K9 Z% ]; A. f* h1997533 SYSTEM_CAPTURE IMPORT_PCB Pins do not swap in System Capture on backannotation% |8 ?: \& M' x: |& `, H" t) w% |
1910962 SYSTEM_CAPTURE MISCELLANEOUS Dragging GND symbol placed on a pin sometimes disconnects the GND symbol1 n* P3 B N% v. p- E
1962037 SYSTEM_CAPTURE TABLE_OF_CONT Table of content link number not same as page number in the title block
4 x: E, [/ L3 ^+ E9 x, Z8 O1986317 TDA SHAREPOINT Cannot enable Design Management and SSO session expires, k1 }' T. L$ P) m E5 f
/ T* N+ L$ f, D# J
* b, m9 F+ m- @4 b5 G# f& x
Fixed CCRs: SPB 17.2 HF049
+ O9 j* R7 v1 ~4 x, _! f9 f2 \11-16-2018
, \4 `, d4 p( |5 x* K========================================================================================================================================================
( d# E5 h6 @# b4 c3 BCCRID Product ProductLevel2 Title
; N! R: q' q% L! \4 H========================================================================================================================================================' W9 [2 z9 q$ R; U
2002642 ADW ADWSERVER Exception in adwserver.out with LDAP enabled8 S) r; o) m1 a9 B; d* |* G/ {, u
2007046 ADW ADWSERVER Component Browser is not connecting to server in hotfix 048
0 |# T2 e5 O2 q1997678 ADW DBEDITOR Model not deleted due to missing cell model relation, |8 b0 |" ^" {' \& |- X+ R
1985059 ADW FLOW_MGR Flow Manager issues warning about project path that contains a period, removes from catalog file
1 c' Z" I# s3 @! O, u, B' ^5 H- K1991515 ADW FLOW_MGR Flow Specific Tools: Launch error after upgrading to Hotfix 044 and extending code7 e& Z7 [/ W, N
1972762 ADW PART_BROWSER The Schematic Models icon does not match the definition in EDM Component Browser0 G) G! o9 v" I* Y0 z
1830062 ALLEGRO_EDITOR DATABASE Uprevving release 14.0 design with stand-alone DBDoctor in release 17.2-2016 crashes; works in release 16.6/ j0 _0 E( T& _
1980161 ALLEGRO_EDITOR DATABASE NODRC_ETCH_OUTSIDE_KEEPIN assigned to text in library part is not passed to PCB Editor7 B. g, m; K) H) X- |
2003757 ALLEGRO_EDITOR DATABASE Open circuit not detected by PCB Editor: reports unconnected pin as connected
* ~3 w' p+ z- D7 k2009748 ALLEGRO_EDITOR DFM PCB Editor crashes on Update DRC. J, t i/ b2 o5 f
1796895 ALLEGRO_EDITOR DRC_CONSTR Increase precision of Inter Layer Spacing check. ] ]2 z/ O+ G. N7 t' U
1997487 ALLEGRO_EDITOR DRC_CONSTR Cannot add teardrops to some pins0 Q: M6 y$ s! t: A
1857024 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes on using funckey 'y FORM mini padstack_list -+'3 B Q6 r+ c6 F
1979750 ALLEGRO_EDITOR INTERFACES axlStepSet not working for component definitions. ?8 t0 ~) D# a: v
1988168 ALLEGRO_EDITOR MANUFACT Graphical Compare in productivity toolbox terminates with errors
[- M- k6 C2 U5 B2 W; @1982233 ALLEGRO_EDITOR SCHEM_FTB Netlist files cannot be imported into board as the process is not finishing7 ~9 b& g( O( r# A# V
2000367 ALLEGRO_EDITOR SCHEM_FTB Cross-probing between OrCAD Capture and PCB Editor does not work in HotFix 048
/ k% f7 h- v2 K4 o9 N. q( [2000397 ALLEGRO_EDITOR SCHEM_FTB Cross-probing not working with hotfix 048
( s; ^, f0 L6 x$ l* l2000552 ALLEGRO_EDITOR SCHEM_FTB Cross-probing is not working if we are importing Netlist from PCB Editor
# \0 b' T, T" ~2001165 ALLEGRO_EDITOR SCHEM_FTB Cross-probing between Capture - Allegro PCB Editor fails after hotfix 0487 m% z% C& L! |- ^/ S9 X7 _8 R# a$ p
2002635 ALLEGRO_EDITOR SCHEM_FTB Cross-probing issue because of Unique MPS Session in HotFix 048 (QIR7)4 j& K# }( q/ K7 A# [
2004252 ALLEGRO_EDITOR SCHEM_FTB Cannot do cross-probing between Capture and PCB Editor# l3 a: p* B( p
2004305 ALLEGRO_EDITOR SCHEM_FTB Inter-tool communication is not working properly in PCB Editor release 17.2-2016, hotfix 048" W7 T5 F3 g. @/ _) B
1978660 ALLEGRO_EDITOR SHAPE Static shape on dynamic shape issue: thermals not removed when component is moved8 U+ G2 r% p8 {& H2 O& V" L1 B9 w
1985035 ALLEGRO_EDITOR SHAPE Thermal reliefs not removed on moving parts
7 h9 x) f9 N* e* y( {1960966 ALLEGRO_EDITOR SKILL Stackup import is not working in release 17.2-2016 via automation( ~" P" _2 h0 ?" V4 x
2003651 ALLEGRO_EDITOR UI_FORMS Error on starting and loading footprints in hotfix 048: message about customExtended and customState) q" ~4 V& h( N# ~8 q7 ^
2003810 ALLEGRO_EDITOR UI_FORMS OrCAD layout editor font size is too small for almost all UI
+ a7 D* v: {6 k& i2003832 ALLEGRO_EDITOR UI_FORMS Error on loading footprint in hotfix 048: custom toolbar cannot be loaded due to registry problem; _6 y" B" Z [, F" V( u+ B$ i
2004769 ALLEGRO_EDITOR UI_FORMS Custom toolbars cannot be loaded as the size of customState and customExtended differs in registry
; K3 c2 E4 F8 _0 i9 D% {/ ?2007669 ALLEGRO_EDITOR UI_FORMS Broken scalability between OrCAD PCB Editor and Allegro PCB Editor
0 A0 |* d4 r% w, G1987164 ALLEGRO_EDITOR UI_GENERAL PCB Editor stops responding when multiple sessions are accessing third-party tool
* y6 b: E0 [9 }" J/ W$ Y1983512 ALLEGRO_PROD_TOOLB CORE Allegro Productivity toolbox: Advanced Testpoint Check is not working9 l, W n4 }+ s: a
1996008 APD 3D_CANVAS New 3D Canvas does not work in APD& l; |; R$ h2 K% W
1993698 APD SHAPE APD stops responding and database is corrupted on moving, deleting, or updating a symbol
1 ]( P S* {2 m% F1999446 CAPTURE OTHER Update symbol database in Trial# b* E# Q* Z( I" M7 I
1962222 CONCEPT_HDL CORE Nested hierarchy block RefDes transfer issue: suffix added to RefDes/ }2 r0 B. y$ k! \# V+ a
1964260 CONCEPT_HDL CORE RefDes not updated in a hierarchy block on repackaging release 16.6 design8 l( F7 g I4 S2 `4 [
1972243 CONCEPT_HDL CORE Version filter does not work correctly
6 Y$ b9 _4 Z/ z( N( q Y# y" E, v/ l1993448 CONSTRAINT_MGR DATABASE CSet is duplicated with same name when modified in SigXplorer
, K, X- b+ Q. V; Q9 E, G1976148 CONSTRAINT_MGR INTERACTIV DRC worksheet in Allegro PCB Editor: 'Go to Source' flickers worksheet and does not switch5 z. @3 K- ^; f+ X1 v% C2 M: b
1948372 CONSTRAINT_MGR UI_FORMS cmDiffUtility fails to compare and gives the message 'Failed to read the configuration file'8 P% G. K3 N' k; B. I# n0 Y
1961750 EAGLE_TRANSLATOR PCB_EDITOR Voids and some shapes of third-party board not translated correctly- F9 f5 [, X$ S
1984569 FSP DECAP When a pin function is in an interface or custom connector is changed, decaps defined for the part is deleted
8 b( r0 r/ a' h. ~2 Y1984588 FSP DECAP FSP crashes when changing pin functions or bank settings for a connector
6 `$ R( y5 q# i9 W" j, {9 I1984590 FSP DECAP FSP design fails to load if pins are defined with a pin function that is later changed in custom_connector.crf& w4 c* K ~0 \4 Z
1985555 PCB_LIBRARIAN IMPORT_EXPORT JavaScript exceptions on opening libraries converted using con2cap
9 ^7 y0 H% W. z- k7 j5 n1961944 PCB_LIBRARIAN SYMBOL_EDITOR Hide symbol outline in new Symbol Editor B# H& I1 ]! d) {& Y" |! X! ~
1967532 PCB_LIBRARIAN VERIFICATION libimport fails with ERROR(SPDWPAR-102): Metadata has the ErrorStatus value set.) M# S0 B& M! u( _2 P% t
1976965 PSPICE SIMULATOR PSpice 'Tools - Generate Report' not working in release 17.2-2016* | j% u- q8 g0 ~
1982260 RF_PCB FE_IFF_IMPORT Unable to successfully pull in .IFF file created in ADS.
6 q0 d3 Y* W0 O/ O1981585 RF_PCB LIBRARY Cannot load RF symbol via2 into PCB Editor u" U& p, w5 Q1 m5 T
1976845 SIG_EXPLORER OTHER CPW trace models do not solve in SigXplorer after changing some trace parameters$ O; M& _% ^, h: |. d/ R
1986466 SIG_INTEGRITY OTHER Delay in Relative Propagation Delay worksheet is displayed as a negative value3 ]+ }) L: e6 D3 _' q
1980264 SIP_LAYOUT INTERACTIVE SiP Layout crashes on running 'Manufacture - Documentation - Display Pin Text': y0 {8 t% G8 \+ @' v# j, F h
1983381 SIP_LAYOUT REPORTS Incomplete Design Summary Report! j. o" f/ t0 ~( N" K
2005709 SIP_LAYOUT SHAPE Dynamic shape voiding around same net cline segment: no property attached5 M3 H" G( }! j9 T
2008064 SIP_LAYOUT SHAPE Hotfix 048 (QIR 7): Shape creates void for same net cline, it should be shorted9 ]$ G7 H+ ]( R
1980967 SYSTEM_CAPTURE CANVAS_EDIT System Capture does not reflect part symbol changes
$ V6 t" a: z) g+ K5 C. |% e8 o+ f" N1988928 SYSTEM_CAPTURE CANVAS_EDIT Changing version 2 of the resistor part makes the PART_NUMBER property visible
; c7 W( v4 y- _ R+ q1990215 SYSTEM_CAPTURE CANVAS_EDIT Draw Multiple Bits: Bits do not follow mouse smoothly6 ~) q8 H {; {1 t R
1972658 SYSTEM_CAPTURE EXPORT_PCB Modified injected properties do not get updated in the pstchip.dat file after running Part Manager and Export Physical
. f! ]% R& t: m. ^& V+ ^' C1989421 SYSTEM_CAPTURE EXPORT_PCB Part Manager does not update the PTF values
, s5 E" N F$ i8 z1992407 SYSTEM_CAPTURE PART_MANAGER Part Manager removes part properties and main window and details window updates are inconsistent
* ?+ ^9 J' i7 t/ i5 G
. Q* M& Z) l1 ?, N
1 Z2 s4 |- X' D( \ B4 r( b3 _Fixed CCRs: SPB 17.2 HF048- P: Z4 b/ n* E$ a
10-13-2018' t/ Z/ V( `( r( a# U
========================================================================================================================================================% U% K0 n! A! U5 w' M3 k
CCRID Product ProductLevel2 Title
5 Z( a# I. b, x========================================================================================================================================================; q. b" Y- \. \% a; T. q9 J* H
1913039 ADW ADWSERVER EDM Library Server exits with error message on starting library server service
: Y: J9 K. {* S, }) Y9 z2 S' g1709155 ADW COMPONENT_BRO Search query does not search for all the parts in the library
4 N1 g) H1 }) X1827231 ADW COMPONENT_BRO Clicking the 'a' key in Part Manager launched from DE-HDL crashes DE-HDL; j- Q3 Z) Q! C! M
1903818 ADW COMPONENT_BRO Parts that have comment_body do not display version
# d" W3 d! i2 {+ t( q5 t# \1917961 ADW COMPONENT_BRO Component Browser PPL column values are truncated when selecting the top '*' filter
D" p, M8 F( t! s% N1938172 ADW COMPONENT_BRO Symbol version with COMMENT_BODY set to TRUE cannot be instantiated
* D5 J3 {; q0 A/ N6 k; v1914103 ADW CONF conf creates incorrect path in fetch_dump.ini when MLR is enabled.
! {" _) ^6 I- u1911422 ADW DBADMIN RuleP101 - PACK_TYPE check against schematic model not working2 i4 H1 O) w5 r; `' w
1926691 ADW DBEDITOR Adding a new classification and immediately trying to delete it results in errors
* G; p1 y/ P" z7 U I1926694 ADW DBEDITOR Renaming a classification and then renaming it back to the original results in error
# ]9 ], g7 S, ~4 {1934870 ADW DBEDITOR Adding a new classification and immediately trying to delete it results in errors$ Q% ~% @& a# j2 f1 g5 d# w
1872387 ADW DSN_MIGRATION Design Migration does not cache all used parts into flatlib/part_table.ptf
0 ~5 W, l) k1 w2 b H+ ?7 j1254292 ADW FLOW_MGR Flow Manager Open Last Project should open last project closed' _" [4 t) S' N, ~7 M) C
1281817 ADW FLOW_MGR '-proj' switch in 'pcbdw_fm' does not work; launches Flow Manager without loading any project
) j9 H+ I0 u7 H! m. ]2 u1727286 ADW FLOW_MGR Product options for PCB SI and Power Integrity are incorrect in the flow and tool launchers
2 B3 ~8 m# ~! p8 L: b! }1875498 ADW FLOW_MGR EDM fails to open or becomes unresponsive.# {& p8 n1 i+ s! m
1879386 ADW FLOW_MGR Unable to access COS with the default Firefox version in the 17.2 installation
/ E( z3 ?% F, E3 o9 n1922541 ADW FLOW_MGR Warning message for unavailability of Java version appears on opening a project on Linux8 n4 v; Z4 P2 }, D _! k& h
1945451 ADW FLOW_MGR Checklist does not work with two-byte characters
( r, |5 q3 i! ?3 w; b; Y1956213 ADW FLOW_MGR Not able to invoke Flow Manager on the remote system
Z) @( J8 o$ Q7 A$ I1 `1892285 ADW LIBDISTRIBUTI Symbol not consistently available in 16.6 ADW Library
9 p) \+ s- Z! s+ z- B0 r0 f1961731 ADW LIBIMPORT libimport fails to create tar for two Capture models1 y( e& K5 D- r. u
1836620 ADW LRM Library Revision Manager crashes on clicking Help/ ]2 f- P/ C+ t8 _3 z
1961845 ADW PART_BROWSER Error regarding environment variable5 z4 j: U4 `5 _* X6 Q. R2 ]# l
1890782 ADW TDA Launching TDO dashboard connected to PLM returns a license error$ H3 i' A9 G( j/ S
1980914 ADW TDA Cannot start Design Entry HDL and Component Browser in a TDO design/ l) \9 c% p- n0 X( S( B2 E
1833750 ALLEGRO_EDITOR 3D_CANVAS Soldermask Text is not shown in 3D Canvas
* y/ E/ o+ z, o; d+ q8 o/ P' `, Y3 W1891230 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas Viewer not bending PCB with proper radius
* c, a+ e) f5 H1 w1913338 ALLEGRO_EDITOR 3D_CANVAS STEP models missing from exported .stp file
1 Y9 O$ l% ^# y& @2 S5 X9 c, f1927507 ALLEGRO_EDITOR 3D_CANVAS Get Error: All bend operations are disabled due to licensing and/or DLL installation issues on invoking 3D Canvas+ M$ u+ u$ U* n2 w( h( \0 M
1931508 ALLEGRO_EDITOR 3D_CANVAS Place Bound Bottom is displayed on Top, when dra is opened in 3D Canvas
) k( x9 \, O! L1943060 ALLEGRO_EDITOR 3D_CANVAS Placebound bottom is not showing correctly.
7 j! Z) ~* A6 ~+ E0 l9 u1950099 ALLEGRO_EDITOR 3D_CANVAS Place Bound Bottom is displayed on Top, when dra is opened in 3D Canvas: u. ^* K1 n* A i. L+ {
1988307 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation4 v. X/ j, P- w1 h( `
1923585 ALLEGRO_EDITOR ARTWORK Additional unwanted subclasses appear in film control when a new film definition is added
4 ^. u- _* F7 O5 Q; t3 p1944079 ALLEGRO_EDITOR COLOR Export of Board Parameters (Net Colors) does not contain entries for nets with spaces$ {& m D8 ]6 V1 H1 \( C
1856320 ALLEGRO_EDITOR DATABASE Donut pad fails to connect with cross-hatched shape in full contact thermal mode, despite hatch overlap of donut.$ b' q0 Q" H" s; a9 r2 {
1912313 ALLEGRO_EDITOR DATABASE Database corrupted during background process% ]5 j1 ]" Q& v ]3 F
1913344 ALLEGRO_EDITOR DATABASE When changing accuracy of design, the thermal relief for donut pad's outer pad connects to inner pad
% `5 L, W/ l5 H$ j8 Z$ c1914470 ALLEGRO_EDITOR DATABASE Release 17.2-2016: export libraries command does not inherit posi/nega information
( s, B+ ~- V9 W" d/ H4 F1932086 ALLEGRO_EDITOR DATABASE Unable to resolve DBDoctor error
% \6 L# T9 G4 \9 v0 B; h: S9 o1963932 ALLEGRO_EDITOR DATABASE DB Doctor is not recognizing placed parts and showing them as unplaced.
+ r# ?2 p% c5 K2 R" b/ z1987735 ALLEGRO_EDITOR DATABASE Interior sub-lamination backdrill holes are displayed with Top Soldermask pads where backdrill does not exist
% ]' k0 D9 [! k1977622 ALLEGRO_EDITOR DFM Not able to add value '5' or multiples of 5 in in DFF constraints for maximum stacked via count
2 \: N, R' X& ~! N1892809 ALLEGRO_EDITOR DRC_CONSTR NODRC_ETCH_OUTSIDE_KEEPIN property is not working on TEXT
4 J7 Q! J9 ~3 s: @1894765 ALLEGRO_EDITOR DRC_CONSTR DRC for no_drc_component_board_overlap is not created if the place bound is outside Place Keepin
2 s( j ?( q$ o1896627 ALLEGRO_EDITOR DRC_CONSTR Moving components takes long time while doing placement
& g8 s0 E4 O" T c; U1914591 ALLEGRO_EDITOR DRC_CONSTR Spacing constraints for Mechanical to Hole shows resolved constraints different from the actual air-gap/space
9 V# s/ J2 Z: \: g. T4 Q* s% N1956468 ALLEGRO_EDITOR DRC_CONSTR DRC getting generated while moving the uvia and getting removed after updating DRC.
9 h$ C& z% M# ^3 ~1884149 ALLEGRO_EDITOR EDIT_ETCH Arced Routing of differential pair creates unexpected arc radii
+ U8 R9 ~# V- h p! l0 e- F/ d1891985 ALLEGRO_EDITOR EDIT_ETCH Etch edit does not follow the constraints/ P3 `6 m: A& W: t) |5 A5 D
1860056 ALLEGRO_EDITOR GRAPHICS PCB Editor crashes on right-click after choosing the Move command
6 x2 u6 p, }, {1 x# Z% o/ Y1860723 ALLEGRO_EDITOR GRAPHICS APD crashes on right-click when using the Move command
4 z/ w0 H# {- u9 S) ]! |1870058 ALLEGRO_EDITOR GRAPHICS PCB Editor crashes when using Place Manual -H command4 r$ X* |: l7 R) K5 C! B( J- ~ U- ?& X
1930282 ALLEGRO_EDITOR GRAPHICS PCB Editor crashes on executing axlVisibleDesign(nil) from allegro.ilinit
3 p; |! U4 ~' b. `: ]3 Q# H% K# J* L1882813 ALLEGRO_EDITOR INTERACTIV Unable to set the end point with 'snap pick to' when adding an arc
/ r; b2 t( D9 R1 c( S. a1884725 ALLEGRO_EDITOR INTERACTIV Edit and Move vertex operation not working as desired
) w9 x: _+ G; w* K, i! S2 p" l# {1902359 ALLEGRO_EDITOR INTERACTIV Connector boundary remains ON for a layer if visibility toggles in Shape Edit application mode
) b! X0 i( b7 V2 ~1909004 ALLEGRO_EDITOR INTERACTIV Parameter description showing wrong for Padless Holes under Design Parameter Editor, `' C3 { l7 i" q3 l
1912055 ALLEGRO_EDITOR INTERACTIV PCB Editor crashes on Delete By Query - AutoSilkscreen - Find By Query/ A% R' o: q: W' P7 k0 ?! g, g( |
1924503 ALLEGRO_EDITOR INTERACTIV Editing shape causes PCB Editor to crash; m c9 O6 U i) r# x9 r, B# h
1929614 ALLEGRO_EDITOR INTERACTIV Unable to Place Via Array when Staggered ring is selected in Global Ring Parameters.! R2 m# m9 F i; z; @; j6 a/ @. Y
1938523 ALLEGRO_EDITOR INTERACTIV Change Shape Type message is same for dynamic and static shapes
: R3 T$ h% s0 u+ n2 j% M/ j, x1940827 ALLEGRO_EDITOR INTERACTIV Irrelevant/incorrect warning message when doing Edit- Change on Clines5 D5 n3 G& h4 y. L% }, a' x+ Z! n
1872653 ALLEGRO_EDITOR INTERFACES DXF export shows embedded layers in the layer configuration file$ V% U4 F: T8 S& C
1873971 ALLEGRO_EDITOR INTERFACES IDX proposal comments are not shown when importing the IDX file into Allegro
1 U. k$ F( B2 J, ]* w% _' |: y) b1892172 ALLEGRO_EDITOR INTERFACES STEP Package Mapping form needs to be larger( ^; Q7 Y0 ~* A2 v7 i
1893311 ALLEGRO_EDITOR INTERFACES A line became two lines after import dxf
$ ]2 n- p# s6 }5 {" a1937816 ALLEGRO_EDITOR INTERFACES Unit as % in Property Definition not supported by SubDrawing
5 D# Q8 W( Z) x9 _$ g4 e1973084 ALLEGRO_EDITOR INTERFACES Physical library not placed if design and IDF database not matched while running
3 q5 ?3 o" Z- f9 f1 g0 o& z' O1987526 ALLEGRO_EDITOR INTERFACES IDX import Fails to recognize SURFACE FINISHES Class
" I3 Z# D; |& U# i3 q8 i) Y1872856 ALLEGRO_EDITOR IN_DESIGN_ANA Message displayed when creating directed groups needs to be improved
' J" Y# b6 @$ o1900832 ALLEGRO_EDITOR IN_DESIGN_ANA RTP: Return Path DRC does not check circle void correctly
4 ]6 @2 v3 e; _0 h* [: m9 l" z1935641 ALLEGRO_EDITOR IN_DESIGN_ANA Return path DRC crashes PCB Editor* S: M; x) u) B( X9 ?7 \3 h' @* k w
1649465 ALLEGRO_EDITOR MANUFACT Manufacturing options are not visible in OrCAD PCB Designer legacy menu
& T* \1 z) N0 ?1 A1873417 ALLEGRO_EDITOR MANUFACT Autosilk fails to add line information. Only part of the line is getting copied to the autosilk layer.
1 `) r4 h2 h, y4 S V) Y4 H% y- m& J1911596 ALLEGRO_EDITOR MANUFACT Documentation Editor drill chart shows two different rows for the same slot.
& W, E1 U; T" q/ ]* u Z% k3 E" J1937721 ALLEGRO_EDITOR MANUFACT Drill figure character scaled up in GERBER
3 `. ~& t& P4 V3 H, B1957768 ALLEGRO_EDITOR MANUFACT Import IPC2581 on cross-section does not import line width and impedance% w: S# R! A! j0 Y2 ]; c( S8 M0 k
1969363 ALLEGRO_EDITOR MANUFACT Pressfit connector backdrill depth is considering MNC Layer3 s! \+ D( {5 W$ ^ r3 E$ y; Z
1891102 ALLEGRO_EDITOR MULTI_USER Rejected by server error messages when using Symphony Team Design
) ?) E* V6 r+ p' J1928082 ALLEGRO_EDITOR MULTI_USER Unknown SubClass BOUNDARY/MULTI_USER_LOCK automatically added when defining Artwork Output.8 X6 g4 T( p9 p) R- @
1976705 ALLEGRO_EDITOR MULTI_USER Symphony client disconnects from server without any notification - despite ping mechanism
+ |+ A# P! X, K! o1972554 ALLEGRO_EDITOR NC Mill symbol moved from Nclegend-slots-1-2 to Nclegend-1-2 subclass if nc_param.txt not present a% [5 H- A$ a
1914412 ALLEGRO_EDITOR OTHER Autosilk lines do not clear padstacks that are not rectangular: s Y( o# n! U, E5 {1 h
1921933 ALLEGRO_EDITOR PAD_EDITOR column clearance cannot reset to 0 in padstack editor
6 W% p! t" I8 C M7 q1922234 ALLEGRO_EDITOR PAD_EDITOR DBDoctor reports 'illegal value for pad' and does not fix when zero corner radius for Rounded Rectangle is defined4 I( Q8 t7 A) j7 m
1932183 ALLEGRO_EDITOR PAD_EDITOR Drill Symbol information not exported in Padstack XML if Drill Figure in none
" }% `$ Z' @) Y( A$ J1934880 ALLEGRO_EDITOR PAD_EDITOR Shapes with offsets not displaying properly in Padstack Editor views
9 d; `) x( M4 r4 b0 S7 z# c1813270 ALLEGRO_EDITOR PLACEMENT When a place replicate module is updated, the vias used in thermal pad are removed
" ]+ k' G7 P& T' i9 u1840275 ALLEGRO_EDITOR PLACEMENT Placing component with the Mirror option causing display problems
0 m, r X4 T2 o4 r1854099 ALLEGRO_EDITOR PLACEMENT Align components to zero spacing causing mirrored components to overlap2 T+ T& j' b. v1 w$ ]1 U
1854696 ALLEGRO_EDITOR PLACEMENT Pins shown incorrectly when the Alt Symbol and Mirror commands used consecutively
' ?6 q' A' p, L3 C1 R5 e1862863 ALLEGRO_EDITOR PLACEMENT Too many messages in the command window when symbol does not support mirroring
6 S2 A1 n5 U5 f) o$ _1909857 ALLEGRO_EDITOR PLACEMENT Using Mirror with Alt Symbol placement displays incorrect graphics
8 U: J6 |0 E. T6 K8 z4 }: O5 C1917128 ALLEGRO_EDITOR PLACEMENT Place - Autoplace - Room when all the components of the room are placed on board causing crash0 C$ ^& b2 E4 z" h% c$ Z( `
1925144 ALLEGRO_EDITOR PLACEMENT PCB Editor stops responding on using the Autoplace - Room command: I+ W3 v; y: D) X! a) G; ?+ k0 V+ b& Y
1961509 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes on choosing Place - Autoplace -Room
/ Y& t9 L" b! B: f) t5 e5 ^9 ^1930669 ALLEGRO_EDITOR REPORTS Net 'VSS' not included in the Etch Length By Pin Pair Report
: Q0 I! A" l. t' ~% \ B1982934 ALLEGRO_EDITOR SCRIPTS PCB Editor stops responding if Generate button is used to create script from journal file4 e1 K; K& g6 g+ d i
1337346 ALLEGRO_EDITOR SHAPE Shape Check is generating problem point errors that seem unnecessary
7 ]- R* B0 | s0 [& e: M& c1396692 ALLEGRO_EDITOR SHAPE Zcopy with expansion not following board outline, T3 \2 e H7 \% Y: A- w. T
1902001 ALLEGRO_EDITOR SHAPE Shape behaving differently across hotfixes+ K2 o5 w9 K, p0 F; I+ ]! f
1921287 ALLEGRO_EDITOR SHAPE 3D canvas is showing some stray objects+ { q! B2 b* {; D% ?3 g
1936482 ALLEGRO_EDITOR SHAPE Option for Fillet to not obey NO_SHAPE_CONNECT Property* Z2 E! B" p% z3 W
1943899 ALLEGRO_EDITOR SHAPE Only one Shape to Route Keep In DRC in release 17.2-2016 compared to two in release 16.6
# B$ F, `1 P2 S" ?1944041 ALLEGRO_EDITOR SHAPE shape_rki_autoclip makes shape voiding incorrect
& r5 j i! A& I' X& ~8 s5 [* |6 y1947675 ALLEGRO_EDITOR SHAPE Shape void error when dv_squarecorners is enabled
5 y, L, l- {. v; G1949250 ALLEGRO_EDITOR SHAPE Shapes are filled even after raising and lowering priority
% C1 h3 S4 ?5 B. }1984526 ALLEGRO_EDITOR SHAPE Same net shape voided is inconsistent with respect to vias4 T1 x% \/ i! b! q
1984955 ALLEGRO_EDITOR SHAPE Dynamic shape creating same net spacing drcs.: M! O8 X5 R$ I5 @: l" ~! ?
1839147 ALLEGRO_EDITOR SKILL axlDBGetLength() reports that the segments of a filled rectangle shape are invalid database ID arguments
1 P+ W+ Y& c$ V' m& L6 n9 e1882776 ALLEGRO_EDITOR SKILL SKILL documentation for axlIsBetween() is wrong
/ Q1 n& `8 P& r9 _1882882 ALLEGRO_EDITOR SKILL Example for axlMathConstants needs correction in Allegro SKILL Reference. \% y2 S' L$ h4 s9 G9 W
1902712 ALLEGRO_EDITOR SKILL axlAltSymbolReplace moves symbol to the top of design while replacing
4 D( G5 ]" c e) l% }8 r1906329 ALLEGRO_EDITOR SYMBOL Mechanical Pin to Conductor property set on a pin in a symbol does not pass to the board) U) e$ @( F% h, `6 {- k7 a/ ?% V
1911343 ALLEGRO_EDITOR UI_FORMS Global Visibility not turning all layers off$ f+ l: D- q, x9 p- q
1985584 ALLEGRO_EDITOR UI_FORMS Import logic changes the Current Working Directory1 m5 y7 V/ [: G3 F9 q% B' K
1987829 ALLEGRO_EDITOR UI_FORMS Import logic changes the current working directory8 V- ~6 S$ q6 k. O8 J4 t
1992722 ALLEGRO_EDITOR UI_FORMS After netlist import process, the board file is changing its current path
0 W+ d+ m# N& f1697506 ALLEGRO_EDITOR UI_GENERAL Stroke Editor working in OrCAD PCB Editor of release 16.6 does not work in release 17.2-2016
: R0 h' q7 a2 c& S+ Q! d1702631 ALLEGRO_EDITOR UI_GENERAL Etch Length by Net report does not list correct net name for nets in a bus
2 r8 ]/ v! A( E! a/ X r1703105 ALLEGRO_EDITOR UI_GENERAL Bus net names are incorrect in reports when using the allegro_html_qt variable
P& Z) f; |+ r( K1770786 ALLEGRO_EDITOR UI_GENERAL Stroke Editor working in OrCAD PCB Editor of release 16.6 does not work in release 17.2-2016
4 x; @) f0 R, I1784938 ALLEGRO_EDITOR UI_GENERAL Etch Length by Net report does not show net names with angle brackets in release 17.2-20160 k" d$ W, Z! ]) m/ F
1822557 ALLEGRO_EDITOR UI_GENERAL axlUIWCloseAll is not closing text window in release 17.2-2016
3 V; m, R4 O) ^! h8 t9 u6 W1836400 ALLEGRO_EDITOR UI_GENERAL Net names are truncated in HTML reports
6 B5 l B7 q$ |# u1869879 ALLEGRO_EDITOR UI_GENERAL Links not working in the Net loop report: q+ S$ H% s5 S: M$ j. b3 n
1895878 ALLEGRO_EDITOR UI_GENERAL axlUIWClose()/axlUIWCloseAll() functions do not work when allegro_html_qt setting is enabled.
$ R0 A! ]- n# Q( T+ J ]! {; H1 K1912282 ALLEGRO_EDITOR UI_GENERAL PCB Editor exits with error message on editing objects% p/ b4 R+ E O) v
1913962 ALLEGRO_EDITOR UI_GENERAL PCB Editor toolbars change on choosing View - UI Settings - Save Settings and then restarting+ S& X$ j" R6 y
1933172 APD UI_GENERAL Cannot paste text into the command prompt without clicking when 'enable_command_window_history' is set
1 j3 A0 F2 U" B4 |0 Y8 ?1843712 CAPTURE NETGROUPS Signals shown only for first segment of NetGroup
- e, O5 W; J9 [1917768 CAPTURE NEW_SYM_EDITO Missing package pin overview in Symbol editor
6 s+ g" T0 p# o* D' D1920088 CAPTURE NEW_SYM_EDITO Package view missing in the new Symbol Editor6 }1 ?) ?9 f& H K* ~9 ^
1922196 CAPTURE NEW_SYM_EDITO Snap to grid issue in Symbol editor
/ v, u; }. Z5 E' B. M; v1927268 CAPTURE NEW_SYM_EDITO View Package is grayed out in release 17.2-2016, hotfix 038 and later versions; C" n4 M( @, E% L7 I7 a: V% ~
1928012 CAPTURE NEW_SYM_EDITO In new Symbol Editor, View - Package is grayed out5 B; Y. M5 h. W# S a8 X& W
1930865 CAPTURE NEW_SYM_EDITO View Package missing in hotfix 038
* M& Z C, {! _( Y; S4 z! Y* K1938507 CAPTURE NEW_SYM_EDITO Issues with new Symbol Editor: Justification and spreadsheet usability
; {! W8 v$ Y0 K1 {5 F8 f; l5 o7 o0 \1940869 CAPTURE NEW_SYM_EDITO Missing pins in 'Edit Pins of All Section' table view for 4k resolution but not in 2k resolution3 b! f; |: S$ Z* g9 O/ _
1940888 CAPTURE NEW_SYM_EDITO Copying pins from a part and pasting on different parts not working properly.) i& w( F7 s# g8 ?
1942994 CAPTURE NEW_SYM_EDITO Cut / Paste of object in New Part / Symbol editor always pastes on grid
* i A/ E( l# O2 g" E1944396 CAPTURE NEW_SYM_EDITO JavaScript error while copying from 'Edit Pins of All Sections'6 e7 ?( _: _4 z
1950224 CAPTURE NEW_SYM_EDITO Cyrillic alphabets are not displayed properly on Schematic.% M! A. W6 b6 s7 [# p
1951369 CAPTURE NEW_SYM_EDITO Cancel closes Symbol Editor" ]$ Y7 i1 N% q! R9 q
1966785 CAPTURE NEW_SYM_EDITO Edit Part is grayed out
. O2 a1 W& O* h5 x2 {$ N6 r7 B! F1973135 CAPTURE NEW_SYM_EDITO Issue with new Symbol Editor: cannot copy-paste pins$ M% ]) v7 l: X8 @
1973344 CAPTURE NEW_SYM_EDITO JavaScript error on opening part from design6 Z5 v6 b9 |: X
1974122 CAPTURE NEW_SYM_EDITO Cannot copy-paste all pin list on the new Symbol Editor6 E4 @7 `: s& x7 ^- G* t( A
1983593 CAPTURE NEW_SYM_EDITO Script error on copying and pasting to property sheet. `( l- v: H; m, J. [1 F% b7 p
1929692 CAPTURE OPTIONS PACK_SHORT issues with Pin Numbers that contain letters/alphabets1 o" i5 ]% f4 R! G' p
1876939 CAPTURE OTHER Incorrect Capture renaming error (ORCAP-1310)- K; |' X5 T' U/ ~, ~# [1 K5 R* y- W
1916090 CAPTURE OTHER Incorrect error message when 'save as' fails due to long directory path/ E, ^$ i# d( t/ R* G
1921927 CAPTURE OTHER Two functions are mapped to Shift + R in OrCAD Capture in hotfix 0382 q( W* ^4 \, n6 { v2 j
1946453 CAPTURE OTHER Shift+R shortcut is assigned to two functions.
1 }8 r; J* M* t) A6 s1 ^1965456 CAPTURE OTHER Shortcut Shift + R is not opening the Independent Sources dialog box: ?' U! R0 s8 Z" g( x1 ^* `
1968757 CAPTURE OTHER Close CIP is grayed when right-clicking on the tab in Capture.8 f/ d5 }$ i$ E5 ~7 z1 u$ V
1938437 CAPTURE PART_EDITOR OrCAD Capture new Symbol Editor Pin Type missing in table
/ N W. I1 ^. @. E1906757 CAPTURE SCHEMATICS Intersheet reference is overlapping with the offpage connector name
8 y+ t8 g" ?+ a$ w7 n: L: e1867016 CAPTURE SCHEMATIC_EDI Part placeholders not being positioned when moved/ U3 j- p4 { H6 I2 `+ H
1932837 CAPTURE SCHEMATIC_EDI Parameters graphics are not correctly positioned, b& X0 ~. T, v& V
1949518 CAPTURE SCHEMATIC_EDI Getting error when comparing designs2 P, T8 i5 [4 M- X0 t, i3 ~
1967545 CAPTURE SCHEMATIC_EDI Only section A of heterogeneous part being placed and not sections B, C, or D P2 J; E% K* o4 e. ]7 ` }6 N
1933919 CIS DBC_CFG_WIZAR New CIS Configuration .dbc file created in release 17.2-2016 shows release 16.3# v3 _# V$ j1 K/ b( N) m3 {# q
1932550 CIS RELATIONAL_DB VIEW NAME in Relational Database configuration is not working as expected.
2 ]& Y. k( }2 Y& R1832524 CONCEPT_HDL CHECKPLUS Default checkplus rules show body height of 0 (sym_2 of the attached cell). This causes the cell to fail verification.
8 A S, |( P( Y' E1912023 CONCEPT_HDL CHECKPLUS signalWidth predicate does not recognize SIG[1..0] as bus.5 t7 V4 Y- \7 g
1966120 CONCEPT_HDL COPY_PROJECT Copying release 17.2-2016 project results in message stating the project is of an older version
6 `1 H2 \, v4 f1 c2 w& i1879425 CONCEPT_HDL CORE Adding signals with the right-click menu is not following the defined color scheme
# s& u u8 B! F2 ~ [1890542 CONCEPT_HDL CORE Getting ERROR(SPCOCN-1911) when running export physical with backannotation" p$ ~/ L' h! v1 i
1907684 CONCEPT_HDL CORE Moving symbol makes canvas unresponsive for a long time8 Z9 c5 [, l. F/ D
1920711 CONCEPT_HDL CORE Pin names changes when mirroring the swapped section.: U2 x- e5 ]4 m% Q, d: \
1931421 CONCEPT_HDL CORE On Linux, 'cpmaccess -read' returns incorrect value
7 {, D: i; U% I) G# K( G* ]! o" w1931782 CONCEPT_HDL CORE Setting DONT_FORCE_ORIGIN_ONGRID to ON does not work for sig_name" P3 |* d! w4 b6 V/ j
1932433 CONCEPT_HDL CORE _movetogrid causes signal disconnection4 j" b: O. U; A6 P0 f+ i
1946993 CONCEPT_HDL CORE DE-HDL Part Manager fails to update parts on schematic if new KEY properties exist in PTF but not in schematic
8 e3 Q) { i4 J3 _+ c0 W1947029 CONCEPT_HDL CORE Design Entry HDL Font Support not working for signal rename; v; u( B6 T6 Q( {% Q
1962865 CONCEPT_HDL CORE Schematic symbol creation with '-' as pin name not packaging
' ?' ?. h+ |" |. ~4 a5 D0 X9 {1966805 CONCEPT_HDL CORE Issues with packaging design containing cells named with a leading underscore i- j" ^1 p z! O0 |
1967760 CONCEPT_HDL CORE DE-HDL crashes on moving Net Group/Port in release 17.2-2016, hotfix 044/ d; e8 \# C) C* [
1968282 CONCEPT_HDL CORE DE-HDL Part Manager fails to update parts on schematic when new KEY properties exist in PTF and not in schematic0 Y5 j f; w8 M( K& x
1972815 CONCEPT_HDL CORE Part Manager not updating missing key attributes from the ptf file by using 'Update instances' option
$ X8 f" \+ s+ _1 P. c* h) q1 [1887790 CONCEPT_HDL CREFER CRefer links not working in selected cpm file
+ h% j3 N' n$ d5 `% E/ @' y1898535 CONCEPT_HDL INTERFACE_DES Global Navigation window does not reflect removal of a net on page2 that is part of a netgroup on page1
) r" z7 M. _# B W: F& S+ x, ?1888048 CONCEPT_HDL PDF Japanese characters are not output correctly to PDF on Linux.
; B# p4 H$ Z: y$ o+ g) d# a# _1937505 CONCEPT_HDL PDF Missing intersection dot in schematic PDF. K! j* h8 X1 W& T f
1942486 CONSTRAINT_MGR CONCEPT_HDL CM crashes when you save after importing a TCF file; [& q- G( G% m6 n4 B
1983743 CONSTRAINT_MGR CONCEPT_HDL Region Class-Class members are being duplicated in CM in the current session
1 [$ \. c! P0 |% K, o4 P: q+ V1906573 CONSTRAINT_MGR ECS_APPLY Database corrupt and DBDoctor reports illegal database pointer error2 c" S) j l5 `# ?
1913805 CONSTRAINT_MGR OTHER Setting environmental variable CM_PARTIAL_DCF in release 17.2-2016 causing crash- L' b- X8 g" D) s: x+ q8 h
1914813 CONSTRAINT_MGR OTHER C++ Runtime error and non-recoverable crash in class-class worksheet
& \0 ~4 j: n+ f1920142 CONSTRAINT_MGR OTHER Xnet names are not consistent in the design/ _5 z- v( n, V7 b2 \
1898549 CONSTRAINT_MGR SCHEM_FTB Importing netlist causing crash in release 17.2-2016, hotfix 036
8 a0 Q5 R7 N/ ~4 Q. ]5 u1814851 CONSTRAINT_MGR UI_FORMS Field solver /DRC check running forever6 l% T/ b3 n* v
1889862 CONSTRAINT_MGR UI_FORMS PCB Editor hangs while assigning net voltages in CM' t% }9 c' b3 t/ L: P; R
1965470 CONSTRAINT_MGR UI_FORMS Constraint Manager GUI Issue in release 17.2-2016, hotfix 039: Font size small and rows/columns in shrink mode
/ ^1 ]5 }* r3 n M7 G( S1945406 ECW ADMINISTRATIO Tree view was not refreshed soon after changing the site permission.
4 J# ~. d( Q+ o5 |, q1826848 ECW METRICS SPDWECW-551 and SPDWECW-553 should be warnings, not errors' r2 Z% G. b4 y7 s4 N+ ]# q
1933373 ECW PROJECT_MANAG ecwbatch does not accept password and does not ignore invalid users" M# B; @" I( D& w+ E' m
1921502 F2B PACKAGERXL Errors on running Export Physical:SPCOPK-1138 and SPCOPK-1149' M! U( g+ a0 i& a/ g: j* r: T8 t
1929846 F2B PACKAGERXL PackagerXL is still creating the pstcmbc.dat file on a release 16.6 design uprevved to release 17.2-20169 n" P6 a1 H" z% f$ B
1953780 F2B PACKAGERXL Updated subdesign package information not updated on the top-level design in the reuse flow
* ~- Z$ N! Y( v' w0 m% [1971738 F2B PACKAGERXL Deleting blank space from pstxnet.dat file crashing DE-HDL
7 v4 S) G) R2 S6 Z# P8 g1891002 INSTALLATION DOWNLOAD_MGR Issue with Download Manager (Change Preferences Option does not Work)
2 m7 a) Z9 F9 }- c' J1972890 ORBITIO OTHER OrbitIO-APR failed to run if PCB design included
/ J. R/ P$ C( }7 |1 V! t& |% |1954262 PCB_LIBRARIAN CORE Footprint model check in fails with verification checks failed error
8 i" m1 J( P" L7 ^2 `* j. J1943656 PCB_LIBRARIAN GRAPHICAL_EDI Symbol Editor is blank if .ascii file is newer than .css file
1 y( w5 d' Z2 P }( @* s4 K* m" Z1897887 PCB_LIBRARIAN SYMBOL_EDITOR New Symbol Editor: Inconsistent symbol results when adding vector pins in Part Developer' m+ I- s* M+ K
1898003 PCB_LIBRARIAN SYMBOL_EDITOR Issue with Page Border Symbol9 {0 u& Z9 E" ~1 J0 c3 G S
1842007 PSPICE LIBRARIES Change required in swit_reg.lib) m9 V8 |$ H3 |, x4 X0 v
1906922 PSPICE LIBRARIES Mismatch in mapping of IC pins in model and PSpice template for analog device AD8138
2 ?* j# K7 A: g; i* C+ V6 _5 T& q1947586 PSPICE LIBRARIES Update the model AD8138/AD in ANLG_DEV.OLB
+ D; A! h. q' V( h1748470 PSPICE MATLAB PSpice displays an error when sending current in co-simulation$ E4 K U7 ~ ^/ C; I& h2 h+ P
1802455 PSPICE MATLAB Incorrect current direction for pins in SLPS flow$ o9 a, p, v5 }! [ e9 E. G6 J( U% l' Z
1852811 PSPICE MATLAB ORPSIM-2604 being reported in SLPS simulation8 N" e! } Z# n
1858716 PSPICE MATLAB Co-Simulation fails if 'RC' is used as reference of resistor Y: d) r2 U) K& @
1921641 PSPICE MODELEDITOR Model Editor in Client Server installation slow to invoke; p+ ]( M# L/ S9 t
1922160 PSPICE MODELING_APPS New Capture Associate Symbol GUI not reading libraries) R8 C8 e" F$ n2 j
1843698 PSPICE PROBE PSpice icons appear very small on a specific computer
# m& o/ @1 @# X0 U* T1773841 PSPICE SIMULATOR orSimSetup64 crashes when running the simulation for attached design1 o% v/ O; ^$ p: I+ w3 M
1816316 PSPICE SIMULATOR Simulation stuck; however, the status bar is correctly updated during Pseudo Transient Analysis
/ n7 g0 G$ d* O1 u6 T8 H- _1887119 SCM IMPORTS Cannot selectively update changes in VDD# [) [; ]8 y1 u+ [
1889362 SCM IMPORTS Cannot selectively update changes in Visual Design Differences( F# n' S* ~3 l1 r7 @3 ?) J
1958545 SCM SETUP Auto assign models does not work in SCM same way as in DE-HDL5 o' i0 b+ g% y: [) E
1988841 SIG_EXPLORER INTERACTIV SigXplorer stops responding or crashes in hotfix 047 when a design is saved' c2 _' w5 w0 r% v
1988943 SIG_EXPLORER INTERACTIV SigXplorer crashes on selecting Update Constraint Manager
3 T# H- Q9 D! E% { r1 g1991375 SIG_EXPLORER INTERACTIV SigXplorer crashes when clicking Save
4 a: k* G1 c4 W/ |1993749 SIG_EXPLORER INTERACTIV SigXplorer crashes on saving topology
% p! e8 V* A# g0 t1969975 SIG_INTEGRITY GUI Model Browser edits model above the one that is selected
* G# ^. E) n9 p; H" p+ ] s1953184 SIP_LAYOUT IMPORT_DATA Sub Drawing not saving dashed lines0 D7 z! X" X* R9 [- `
1913864 SIP_LAYOUT ORBITIO_IF SiP Layout design import results in wrong die rotation Z+ k: b# \4 U; q
1880237 SIP_LAYOUT PADSTACK_EDIT Background Window comes to the forefront when closing the Padstack editor
/ U% S1 q' k" I7 H1972560 SIP_LAYOUT STREAM_IF GDS Export fidelity issue: inverted arcs
# {4 D8 g S. K1 m1920317 SIP_LAYOUT THIEVING Thieving pattern does not allow for OOPS operation, _% W" i2 D3 k9 @
1909075 SYSTEMSI DOC SystemSI PBA channel and circuit simulations do not respond if bit pattern is 1s or 0s2 ]$ C9 L; P* k8 O- Q/ Z, o- _
1916101 SYSTEMSI DOC Lack of stimulus in file causes Serial Link Analysis to become unresponsive% x% O( o5 G3 N# X' K9 J6 G) |' |1 ?+ s
1919562 SYSTEMSI ENG_PBA SystemSI generates wrong timing bathtub curves in channel simulations for write and read' B( V" ^5 N9 ^
1964064 SYSTEMSI GUI_PBA Able to sweep AMI parameters in SSI-PBA
6 x( w5 J8 N6 F1 `% K1971266 SYSTEMSI GUI_PBA MCP header shows only 49 ckt nodes instead of 52 for s52p S-parameter file
! o3 t. k0 D& g1885625 SYSTEMSI GUI_SLA Manage AMI + DLL from Setup Analysis Window
% l& l4 [4 J! c4 x) {! }: n+ R1924382 SYSTEMSI GUI_SLA Data Rate field in SystemSI Stimulus property form is confusing for PAM4 operation
8 y8 I4 s- s! l% r1 s+ N# c1982341 SYSTEM_CAPTURE CANVAS_EDIT Signal rename does not maintain new signal name value
1 f" D3 m' A+ w7 G# N4 `1976857 SYSTEM_CAPTURE CONSTRAINT_MA System Capture-CM Match Group Creation is not updating correctly
: `/ r$ \) V$ h1 X$ ~" c: o8 e1929606 SYSTEM_CAPTURE DESIGN_CORRUP Opening design causes System Capture to crash
5 x# k7 |6 x( f( H/ l1914697 SYSTEM_CAPTURE DRC Overlapping component DRC does not work& @; {* z, R* k y) y' F# A
1973467 SYSTEM_CAPTURE IMPORT_PCB System Capture Import Physical shows many component and physical differences on a design that is synced up" x! Z, D5 x- r, d
1962603 SYSTEM_CAPTURE NAVLINKS Ability to not underline hyperlinks for Navigation Link values# B/ K0 _$ q4 w& h. s% D& p0 m
1967639 SYSTEM_CAPTURE PART_MANAGER Part Manager does not open in System Capture for part property value changes even after setting the cpm directive.
' I7 F! m3 A x& o1964388 SYSTEM_CAPTURE SMART_PDF Some shapes are not visible in the smart PDF schematics
4 o3 E. V2 R+ r" L5 s# \1976832 SYSTEM_CAPTURE TDO Rolling Back local lower-block requires check-out of higher-level packaged & variant views" s" r/ u6 l# C6 Y
1976844 SYSTEM_CAPTURE TDO CM - TDO check-out dependencies are broken
7 `' S: h* ?; O% i/ r2 u4 _3 }7 E$ X1976859 SYSTEM_CAPTURE TDO Variant Editor in System Capture -TDO allows to delete a variant without checking out variants view: ~; [1 w" a2 V0 e( ^
1839816 TDA CORE All the design objects are locked in the EDM dashboard after a DSFrame error
* v% b9 K& ]# X4 f, Y1889898 TDA CORE Cannot check in the top level of the project in TDO, z2 r6 m. t' f. y
1892411 TDA CORE Unable to undo the block checkout if something fails7 m/ F7 t4 R* n+ {& r# j# d. Z, R2 }
1877757 TDA DEHDL Refresh Hierarchy does not show latest TDO lock/unlock status in DE-HDL
9 b, ]5 \" N6 ]1 m: m. \' G6 V0 Z& q$ A1 }
5 M2 O3 V! C( ^. h
Fixed CCRs: SPB 17.2 HF047) {0 c1 ^! M) {" A" |0 e; Z7 C8 M
09-9-2018" N9 K+ M1 ~! W+ f5 r: `% {
========================================================================================================================================================
" l" ~( c R0 bCCRID Product ProductLevel2 Title6 H1 U+ x0 C' ^/ X3 ?, @$ [
========================================================================================================================================================7 }( `* V' B% T" v
1969527 ADW LIBIMPORT Getting java.lang.NullPointerException error on bulk import in hotfix 0449 p0 b( ^" e9 H6 x6 Q
1976219 ALLEGRO_EDITOR DATABASE .SAV file not created although message states it is created0 F; B1 F, @( U& B7 n+ n; b! Y5 [( P
1968270 ALLEGRO_EDITOR DFM PCB Editor crashes when running DRC
# W) r2 q& b( F; d1978421 ALLEGRO_EDITOR DRC_CONSTR False DRCs between via and its fillet shown after editing shape boundary
1 \+ j. u2 }' A) ~* z1966772 ALLEGRO_EDITOR PAD_EDITOR PCB Editor and DBDoctor crash on editing DRA file: Found bad pointer, run dbdoctor
, g$ k$ d% H) M1973866 ALLEGRO_EDITOR SHAPE PCB Editor crashes when deleting a group
2 m# o/ R- G7 O: d* ^6 I1 j( i: [/ C1818779 ALLEGRO_EDITOR UI_FORMS Dialog box goes behind main window on clicking PCB Editor canvas
; N& d. Y7 q* W: z1880175 ALLEGRO_EDITOR UI_GENERAL Multiple sessions of PCB Editor gets mixed up in Linux in release 17.2-2016! Q' R+ \; o6 k; M
1946027 ALLEGRO_EDITOR UI_GENERAL Arrow Keys in Canvas stop responding after changing the view.
3 L1 T# r' P, }9 s: K1967701 ALLEGRO_EDITOR UI_GENERAL Arrow Key panning does not work when third-party SKILL call is active
$ j; I( `, L0 W: y1967706 ALLEGRO_EDITOR UI_GENERAL Observe Special Characters when command is run+ K- o( P e _. x% _
1971183 ALLEGRO_EDITOR UI_GENERAL Focus is lost from command line when Save icon is used
6 j* m0 H6 E5 \4 r# v H1971186 ALLEGRO_EDITOR UI_GENERAL Focus from Command line is lost when using CTRL + N
+ y; t: L; Y. A( p0 F% u! U, \1971190 ALLEGRO_EDITOR UI_GENERAL Focus from Command line is lost when using CTRL + Alt1 ~+ \4 N' r2 k; x, h
1971200 ALLEGRO_EDITOR UI_GENERAL Focus is lost in comand line when you save using command save8 X: ?# D% |$ S6 n/ ]
1961833 APD SHAPE Crash when changing dimension of existing via padstack in the design
# `" G- q* }" |. F$ c. x1968256 ASDA EXPORT_PCB SDA crashes directly after Export to PCB
8 w! ^5 P7 `: V! _% `- e# i* b1970284 ASDA EXPORT_PCB Placing part crashes SDA- |: Z% P" w$ h
7 \ Z i- l1 S7 i5 z5 a3 @
$ M8 S; Z: h G7 r
Fixed CCRs: SPB 17.2 HF046% O8 \+ M7 D0 s
08-24-2018
& A$ k- \ q, o4 x5 O( z' k========================================================================================================================================================# S7 y& G7 n3 y2 e4 R+ m# P
CCRID Product ProductLevel2 Title
& O7 Z* b9 |6 q* E+ m6 a========================================================================================================================================================- P, B4 R& W0 Y3 J. R
1880800 ADW PART_BROWSER Server connection failure on a running SDA session.
" Q0 b1 p) Q" C/ ]9 s; C2 {' C5 B1880895 ADW PART_BROWSER NCB - components missing from the component browser$ d8 k' _6 l" M4 `& t/ x
1962336 ALLEGRO_EDITOR INTERFACES Smart PDF shows both top and bottom probe layers for a film layer with only a single probe layer (top or bottom)7 ?0 X& i! W' m0 E
1955128 ALLEGRO_EDITOR MANUFACT Need to close PCB Editor to delete xsectionChart.log generated on placing a cross-section chart3 u6 h& q; }$ Z. B P
1969088 ALLEGRO_EDITOR SHAPE PCB Editor crashes on updating shapes to smooth' u. B+ X' N& y" L4 _" ?
1963828 ASDA DESIGN_EXPLOR Unwired schematic block movement with text is not correct
5 y5 O& k! r! m% I( G l1954426 ASDA OPEN_CLOSE_PR Double-clicking to paste a note crashes SDA
$ T' @9 I) s8 T6 }1965423 ASDA OPEN_CLOSE_PR Crash when working with notes in SDA2 t9 j, m) c! H' D2 w7 W' T
1960060 ASDA PART_MANAGER Original property differences not displayed in Part Manager on selecting a new part from CB and doing reset
2 y3 {) A$ F4 ]: I1960112 ASDA PART_MANAGER Part Manager incorrectly updating part property values
- d$ I1 w7 ~6 u8 K. |( \8 Z1955723 ASDA ROUTING Draw Multiple Bits misses bit 0 when in reverse order.
/ W" U4 f& h% t+ F* o* h1952963 CONCEPT_HDL CORE Variant Editor takes a long time to load
! c5 {, i( n( x- x! e' [1 Y1962568 CONCEPT_HDL CORE Directive DEHDL_BROWSER_FILEPATH does not work
: s3 F* k' @9 {2 x/ Q1939192 PCB_LIBRARIAN SYMBOL_EDITOR pin_text size and location very different between DE-HDL and Symbol Editor resulting in text overlap. Y7 X0 ?' d% c
1952967 SCM OTHER Error while copying a release 17.2-2016 design: message says design created in release 16.3 or an earlier version
]' j) X& e) h5 g. r/ L1948999 SPIF OTHER Some place_keepout shapes and antipads not exported
* y0 d; u* P( C I4 d4 I" I: S
- Z' ?2 w0 u3 d# ^& m
7 T% ?$ ^5 J5 Q3 xFixed CCRs: SPB 17.2 HF045
; F" n) A% A" D08-10-20188 {- o& r7 T6 |5 P3 ^
========================================================================================================================================================" A' n4 ?* ^$ ?( Z: `* T* A$ {
CCRID Product ProductLevel2 Title
, t# e0 s: X+ w# Z* [8 Y7 k========================================================================================================================================================( A1 L, @9 P* a- {+ ~& u
1934956 ADW DBEDITOR Footprint missing from part in release 17.2-2016
- u! L6 N3 J5 p4 K1945005 ADW DSN_MIGRATION Right side of Migration dialog box is cut off( i* c& z' P/ \: @( H3 f
1933245 ADW FLOW_MGR 'Open last Project' button should open the last opened project
5 O% p4 Q& |3 g- {+ f3 u. ]1953210 ADW LIBDISTRIBUTI Library Distribution is not distributing all symbols. No errors for the missing schematic models.$ n' K8 M0 g& x: |/ R6 c
1953727 ADW LRM LRM missing two symbols when migrating from release 16.6 to 17.2-2016# I& I3 c _/ c
1952923 ALLEGRO_EDITOR DATABASE PCB Editor crashes on trying to delete layer
0 l* [$ s/ a. S+ A1957171 ALLEGRO_EDITOR DATABASE Pastemask offset not working when creating a symbol that requires two top-paste masks1 h+ F( z' _% Z$ H' w0 y% S7 o3 w# t0 @% W
1960059 ALLEGRO_EDITOR DATABASE Stackup definition causes custom script to crash
( @1 x: D! g) L1 F1932864 ALLEGRO_EDITOR DFM Exporting DFM Constraints losing the association to design level
M( ]' J* C4 B$ u1957467 ALLEGRO_EDITOR EDIT_SHAPE Compose Shape copies lines to wrong subclass5 E$ b& }, b6 j7 `& c" H
1938536 ALLEGRO_EDITOR GRAPHICS Multiple crashes on different boards after installing hotfix 040* u" [& A$ N! x# x+ g
1954075 ALLEGRO_EDITOR SHAPE Dynamic Crosshatch shapes should be clipped inside RKI if RKI Autoclip is enabled9 n% @& O6 ~* l$ s
1957803 ALLEGRO_EDITOR SHAPE Wrong dynamic shape status% Y( J) \( \0 l1 w% B
1949923 ALLEGRO_EDITOR UI_GENERAL Focus lost from command window when any command is active
4 u, ^: M! u. j/ b1963245 ALLEGRO_EDITOR UI_GENERAL Alias behaves as Funckey in release 17.2-2016, hotfix 044( l0 p, H" T! u& M* H: x+ _6 i
1892126 ALLEGRO_PROD_TOOLB CORE Clines disappear and then reappear suddenly on using Route - Shield Generator& ^- b! w3 |" m" N) _
1931127 ALLEGRO_PROD_TOOLB CORE ZDRC not working for Xhatch Shape1 @9 o% j, Q- d) x! p
1932563 ALLEGRO_PROD_TOOLB CORE allegro_legacy_board_outline environment variable not set in PCB Design Compare.4 K' h% T/ Z+ s& O% W
1929855 ALLEGRO_PROD_TOOLB OTHERS Outline not exported correctly for PCB design compare if Design_Outline and Cutout exist
& v) r" S3 a+ R. W8 V) n1956494 APD DATABASE DBDoctor removes pads# V+ ^1 Q0 j( u' K/ m
1956291 APD INTERACTIVE axlSpreadsheetSetStyleProp should accept 0 and 1 as Boolean values for protection style
0 j! i; A& @- k, [1960127 ASDA ARCHIVER Using the Tcl command 'archiveproject' crashes SDA+ a- W t1 }0 c+ n! z* o2 f# ^# l
1953718 ASDA CONSTRAINT_MA SDA Import Pin Delay fails with extra columns, does not explain why
* K" S# P3 s- R4 Q1924498 CAPTURE SCHEMATIC_EDI Cannot place part 'B' for heterogeneous part if 'Preferences - Miscellaneous - Auto References' not set i1 s8 D9 b6 Z4 p! W9 ^# b
1927129 CAPTURE SCHEMATIC_EDI unable to place heterogeneous part section directly from place part window1 E0 f- I6 F5 y6 G6 u- l
1928255 CAPTURE SCHEMATIC_EDI Unable to place a specific section from Place Part1 d9 i7 r7 D. v" A
1945207 CAPTURE SCHEMATIC_EDI Part selection pull-down reverts to part '1|A' when placing heterogeneous part" ]8 w$ A, K5 M p( w
1945661 CAPTURE SCHEMATIC_EDI Section drop-down in Place Part window is not working) o" N& B* k8 ] S; q
1958121 CAPTURE SCHEMATIC_EDI Preview and placement of sections of Heterogeneous parts is not correct in New Symbol Editor5 C- h+ z( G" m
1956535 CONCEPT_HDL CORE DE-HDL crashes on Import Pin Delay for a CSV file1 r8 c" G, _# I! [7 Z
1960922 CONCEPT_HDL CORE DE-HDL crashes on moving netgroup on Windows 10 K2 ?" m- T- b9 m! {9 j
1964016 CONCEPT_HDL CORE In DE-HDL moving around nets connected to Netgroups causes crash on Windows 10
# I' q+ X* u& b( {8 m1907040 F2B PACKAGERXL Export Physical output board file name reverts to old when changing options' \' `( H d( g% \; l: T0 }7 [
1957862 ORBITIO ALLEGRO_SIP_I allegro2orbit failed to translate rounded rectangle padstack
. a! p1 z: _ m6 ?" o$ H6 \* _& J& R8 ^6 [* U
9 h/ a1 `: }4 {. {, Z. R/ [ q
Fixed CCRs: SPB 17.2 HF044
$ T5 B9 y) B1 e6 R! e' X07-27-2018) p- _! P V( ]9 I1 V1 T
========================================================================================================================================================
, U/ n9 m+ T5 _' CCCRID Product ProductLevel2 Title
% p& Z! a( T% f! p3 [/ O, m========================================================================================================================================================) D& o1 w" X/ M% F/ g! b
1943727 ADW DBEDITOR EDM DBEditor: Cannot check in/out schematic model symbols with many linked parts
) }5 i. d7 |' X) Y* {3 X3 }9 V1800630 ADW FLOW_MGR Support spaces in design directory path on Windows9 m* o7 y( L. M5 G
1951052 ADW LRM LRM stops responding on project update and removes parts from design
5 ]. G9 V& j3 B/ W* \1891428 ADW PART_MANAGER Resistor turns into a capacitor when placed
+ o8 K6 D6 J) o {' A1945194 ALLEGRO_EDITOR 3D_CANVAS 3D Viewer crashes when opening from board file.
) s9 ?6 i; b) Q; s. [) g5 M, w) @# s1935558 ALLEGRO_EDITOR INTERFACES Exported STEP file missing components when viewed in free STEP viewer
! k& {/ D7 f6 Z9 X, N$ f1945640 ALLEGRO_EDITOR MULTI_USER Symphony client disconnects from server without any notification
: t' U9 r. i* \4 @1948454 ALLEGRO_EDITOR MULTI_USER Window DRC stops responding when run in Symphony* X1 d* k, k" Z: c
1946619 ALLEGRO_EDITOR SHAPE Pin/via with suppressed pad on shape layer and thermal connection type of none should void to drill hole.
. P7 W* V2 {1 [ h7 l! i1946708 ALLEGRO_EDITOR SHAPE Same net hole to shape voiding is incorrect.- F( `! s8 o: [# e; F7 j
1952213 ALLEGRO_EDITOR SHAPE Shape voiding from Thru Via when the via regular pad is not completely drilled out by Backdrill hole is not consistent
- N- @! G" N) @/ A2 W/ m1889433 ALLEGRO_EDITOR UI_GENERAL Command window shows result at the end of a command rather than showing dynamic updates9 D* c. O! ~3 d
1933503 ALLEGRO_EDITOR UI_GENERAL Extra click required to enable command window
* A4 V6 `" [' X6 K: R) b/ K! e1943692 ALLEGRO_EDITOR UI_GENERAL Funckey commands are not working
* G; J" e- c h1945914 ALLEGRO_EDITOR UI_GENERAL Mouse focus lost in the command console when doing an 'undo' from the toolbar icon
3 Q& g4 f% }$ V1 m2 _; T1945920 ALLEGRO_EDITOR UI_GENERAL Focus lost from command window when the toolbar is used for any operation; y7 U) M( V9 @3 c. w/ }' ]$ P
1949922 ALLEGRO_EDITOR UI_GENERAL Focus lost from command window after save or even autosave% g) x: E6 ]! [1 T- U. t% N! V
1947551 ALLEGRO_EDITOR WIREBOND PCB Editor crashes in wirebond edit mode
$ ^6 {+ W4 {! H1935722 ALLEGRO_PROD_TOOLB OTHERS Panelization: Cannot place parts after migrating design from release 16.6 to 17.2-2016* }& k* D# z3 h
1951511 APD REPORTS The result of Metal Usage Report is incorrect.$ \9 r% z. e+ y7 c6 m- D: O
1952942 ASDA GRAPHICS Need metric (mm) support in grids in SDA
/ s0 H U2 V9 I& ~7 w, G! q1948122 ASDA TDO If user ID has uppercase characters in teamassignmenttemplate.xml, TDO fails to join a project0 A+ M/ u( S* D2 e
1931199 CONCEPT_HDL COPY_PROJECT Stop hard coding Copy Project license inside EDM
1 Y, z" w: x0 D3 A4 Y1938153 CONCEPT_HDL OTHER Component Browser stops responding on replacing and modifying components
; y7 I- [5 N# s0 w' t3 Z1770601 CONCEPT_HDL PDF Wire Pattern set to two-dot chain line not shown in PDF
, T. e: Z5 _9 o( I1791175 PCB_LIBRARIAN CORE Allow baseline of cells with pins at symbol origin: change error to warning6 K# b/ H+ x6 M! v) Q% j2 n* l S
1922238 PCB_LIBRARIAN CORE Unable to check in into EDM Server due to con2con error SPLBPD-323 - Origin on pin connection point# X+ t) D6 \" f$ _+ `
1936812 PCB_LIBRARIAN GRAPHICAL_EDI New Symbol Editor: Wrong text being updated when editing text after copy and paste5 K% I1 z/ R" p/ k
1804159 PCB_LIBRARIAN SYMBOL_EDITOR Copy and paste of pins in new symbol editor: issues with pin name, rotation, and move
7 r* t' Z* G& w3 P1927422 PCB_LIBRARIAN SYMBOL_EDITOR Symbol outline not updated correctly in the new default graphic editor in Part Developer release 17.2-2016# \) Y2 |% K2 k+ K
1939272 PCB_LIBRARIAN SYMBOL_EDITOR Symbol Editor changes origin to bottom left, outline to invisible, shows rectangle with center rectangle at new origin- p0 a: |( B) b) H9 m0 F
1928076 RF_PCB DISCRETE_LIBX dlibx2iff does not work with managed libraries and library-level PTF0 n( ?. O* }1 ` _& `
1929574 RF_PCB DISCRETE_LIBX Discrete Library to third-party Translator does not populate the Available Parts section correctly
3 a6 d; _6 r' l$ `! g- z% W1850360 TDA CORE TDO crashes while changing the root design7 N8 d# S6 v: `7 B' g% w- `
1934388 TDA SDA SDA TDO crashes on attempting to check in a 'New Block in Shared Area'5 ^; k9 {! P. d5 k+ t
7 b+ {$ |& d* G2 d
- i9 D7 [5 s( f2 Q3 ZFixed CCRs: SPB 17.2 HF043
" H# Y$ u) W4 w+ ?: c O4 y* |07-13-2018
8 C+ z; Q U0 d+ f========================================================================================================================================================9 y5 T/ u/ c7 q8 P- Z# n w+ t
CCRID Product ProductLevel2 Title
$ B% B; C; W7 Y+ f========================================================================================================================================================
7 X, ?: ^: r; w$ E1935813 ADW DBEDITOR Auto merging of DE-HDL and Capture Classifications is not working5 M7 q! {6 c W- d* b
1935834 ADW DBEDITOR Some DE-HDL only classifications are removed during the CSV merge process of libimport
+ i2 d& y" ^0 @1941570 ALLEGRO_EDITOR DATABASE PCB Editor crashes or stops responding on performing 'Info' or 'edit properties' on select pins
! G. u6 c" m6 Z* ] w: z1942536 ALLEGRO_EDITOR DATABASE Allegro PCB Editor fails to create backdrill plunges in Zone area
' y8 ?7 f7 t! L( R; V" ^7 c+ {7 U3 r1925899 ALLEGRO_EDITOR DFM PCB Editor crashes when placing components in Hotfix 0393 m5 k1 s5 j1 G5 @: r# @
1943113 ALLEGRO_EDITOR DFM Restore normal move/slide via performance when annular ring checking is enabled.
7 c5 N+ |- B" H0 d) [- }) R' P$ t1940939 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashed on running the Gloss - Line and via cleanup tool
7 z2 M2 N8 I2 m1937754 ALLEGRO_EDITOR GRAPHICS Text string disappears when selected during 'Edit - Text' if using PCB_CURSOR
# e% V7 F, o" y, m1937056 ALLEGRO_EDITOR INTERFACES Cannot import IDX acceptance of third-party change to PCB Editor( _( e; |+ F1 I# B
1940197 ALLEGRO_EDITOR INTERFACES PCB Editor crashes when reading IDX file from third-party$ e) J4 N( c* @: ^; P2 q
1940232 ALLEGRO_EDITOR IN_DESIGN_ANA PCB Editor crashes when running Return path DRC
$ M/ l9 b; N6 N- U; I, Q; Y1916921 ALLEGRO_EDITOR PLACEMENT Property Pin_Global_Fiducial not inherited from symbol into board
! n6 q) u; j. ~ A# d1862241 ALLEGRO_EDITOR REPORTS In 'Summary Drawing Report', the listed quantity for HDI vias is incorrect under Drilling Statistics
% ?3 O- f6 L7 ?% I) p% c1935448 ALLEGRO_EDITOR REPORTS Etch Detailed Length Report lists only one coordinate pair per trace
8 k. u$ H% j0 m C1948322 ALLEGRO_EDITOR SHAPE Allegro hangs when axlPolyOperation api is called# J/ q5 O* B; J; z
1795564 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, focus is lost from command window after right-click
* c$ l6 |" R9 q$ ^6 W% X4 B- F2 G1919247 ALLEGRO_EDITOR UI_GENERAL Infinite cursor graphics issues on move: Cursor disappears and symbol image remains at old location till refresh6 F' d N$ M9 Y9 j- A
1919256 ALLEGRO_EDITOR UI_GENERAL Infinite cursor graphics issue: Symbol disappears during rotate
4 z' `3 V+ H$ C5 G6 A1933526 ALLEGRO_EDITOR UI_GENERAL Panning is slow in PCB Editor in Hotfix 038
1 M1 f4 L5 E. [; {& }, B1933530 ALLEGRO_EDITOR UI_GENERAL Strokes are slower to respond in release 17.2-2016
! K v1 A$ W5 L% @/ H" S1933536 ALLEGRO_EDITOR UI_GENERAL Third-party dialog stops responding on running commands: u' v4 [. L$ p( T- K2 v
1782227 APD DIE_GENERATOR Ability to specify rectangular shapes in die text in; b# r9 `/ j8 E% k9 q; q
1933011 ASDA PART_MANAGER Parts changed in library with new pin names are not reported or updated by Part Manager; V1 r F# i5 j0 m
1924529 CAPTURE NEW_SYM_EDITO Global colors for pin name and number and part body not allowed in release 17.2-2016, Hotfix 038/039
6 Q- Z5 V9 g8 @% c+ s) e, @. p# c. O1925846 CAPTURE NEW_SYM_EDITO Opening library or component with special characters in path throws JavaScript exception% f& m# m& _; Z$ [% m
1928905 CAPTURE NEW_SYM_EDITO Pin name justification, length, and casing incorrect for generated parts in Hotfix 0385 i% B7 H0 f4 D
1928965 CAPTURE NEW_SYM_EDITO Cannot move pins in Capture if Pin Name is missing8 F; _! k# k% C) [
1932149 CAPTURE NEW_SYM_EDITO JavaScript exception if path to part contains special characters in Hotfix 039
E4 @* p, c' Q; \4 r* ^5 b1936301 CAPTURE NEW_SYM_EDITO Cannot edit symbol in new symbol editor: Displays parsing error (SPSMI-1)$ `3 t% W) |9 N
1917172 CAPTURE PART_EDITOR Pin name rotating on schematic even when pin name rotate is off in symbol editor
2 i8 w( L& Z! ?* s& j. }& r1924456 CAPTURE PART_EDITOR Color preferences for pin, pin name, and pin number do not apply in part editor but only in schematic
; m: ^" ~; {: o/ y9 B3 C1928872 CAPTURE PART_EDITOR Pin name locations are wrong and each needs to be placed manually$ s( E4 k& |2 g) S
1929562 CAPTURE PART_EDITOR Changing pin name while adding a pin not intuitive in Symbol Editor( ~& j4 U" L, N3 E: F9 M! x$ @
1932732 CAPTURE PART_EDITOR Part Editor issue: Pin name selection box too long and text not justified in Hotfix 040
! c0 _2 k9 y) N: y# A1933523 CAPTURE PART_EDITOR Connection box does not appear after changing pin of a placed part in Hotfix 040
. E* d6 s, S3 J1936994 CAPTURE PART_EDITOR Error because of illegal characters in pin name and number and net name
% n# D# h7 V1 Z* l1943074 CAPTURE PART_EDITOR Pin names rotated in Part Editor not rotated when placed on page
9 z. @7 @) f" n+ g. K$ V2 k0 D1943078 CAPTURE PART_EDITOR Pin name rotate not working.
* R1 _# w+ a; x1945055 CAPTURE PART_EDITOR Pin names not rotated in schematic
4 A: a* f" b, n& d6 I, k" v9 q& W1925700 CAPTURE VIEWER Pin numbers and text not shown during Variant View mode anymore.: E0 W+ [& p2 g3 E' l! R
1914437 CONSTRAINT_MGR CONCEPT_HDL Constraint Difference Report appears even though there is no difference in constraint.* @; s( g. G/ i; C, e1 O3 t
1935152 CONSTRAINT_MGR CONCEPT_HDL Match Groups are not formed with the correct pin pairs! \* h# D( n1 T: j Y8 w! |) f
1940575 SIP_LAYOUT ORBITIO_IF Need new routing flow3 }5 Z4 T' U8 r
1923722 SIP_LAYOUT STREAM_IF Use one symbol for all instances of a Via Structure% Y% \ ~* L: a* l0 r3 Z
; e! X$ [; ~3 s& u; i
. U' _! H& X8 O
Fixed CCRs: SPB 17.2 HF042
: q& M# w$ w6 \! I8 @$ h! W, I2 M06-22-20188 _: C! Y3 m4 e" Q: N# e, _9 Y
========================================================================================================================================================
+ ~! \/ k" e2 b9 OCCRID Product ProductLevel2 Title# ]9 Q- ]- i* U1 {! A% U
========================================================================================================================================================# J/ G; H; S6 n; ]8 N: q3 n: u
1922654 ALLEGRO_EDITOR ARTWORK Difference in board and Gerber display
3 A; I* F7 E$ R$ H' z1 n1932714 ALLEGRO_EDITOR COLOR Manufacturing subclass NCDRILL_FIGURE missing from Color Dialog when editing .dra file
7 F/ y# m+ `8 \) d! n1 R1932316 ALLEGRO_EDITOR DFM DFM constraint reporting wrong DRC between backdrill via hole to shape clearance under copper spacing
' }- I0 [) t5 D, l6 @* {1914334 ALLEGRO_EDITOR INTERFACES Design Compare does not import some netlists created using Export - Netlist with properties from PCB Editor
; D! M8 g* U: z* K$ G8 O7 B1910213 ALLEGRO_EDITOR MANUFACT OrCAD PCB Designer shows Backdrill Status in Check - Design Status( l4 ]# {2 x0 B+ y1 w2 r( a( j
1933049 ALLEGRO_EDITOR MANUFACT NC Route seems to put all routed drills in the same .rou file regardless of what layer they are on.
4 i) E3 i' ]( l L5 F1880576 ALLEGRO_EDITOR PLOTTING Extra lines appearing in plots that are mirrored
! W$ e3 e- S6 p6 P; [1881031 ALLEGRO_EDITOR PLOTTING Plot Preview with the Mirror option in the Plot setup creates fancy lines on shapes' V, f( d; {# y7 X u ?. r+ O
1908005 ALLEGRO_EDITOR PLOTTING Plotting with mirror options set results in strange lines on the plot
3 O) U" i9 D+ o- }0 Q8 Q) t1909530 ALLEGRO_EDITOR PLOTTING Use mirror function when plotting lines to design
/ s$ F5 ~/ X5 E' [: p1 K1919405 ALLEGRO_EDITOR PLOTTING Printing with the mirror option results in arcs in Print Preview7 q% y9 \" v+ A. G& A+ o9 V ?
1830419 ALLEGRO_EDITOR SCHEM_FTB Import Logic with 'Overwrite current constraints' deletes attributes from drawing* A3 k9 @% y. Z( ~( f4 a
1935253 ALLEGRO_EDITOR SHAPE Compose shape command causes tool to stop responding; y% J+ c1 o" E# r
1571600 ALLEGRO_EDITOR UI_GENERAL File - Capture Canvas Image missing in release 17.2-2016
' l, h1 h! f# n$ K' P, V& F1650403 ALLEGRO_EDITOR UI_GENERAL Include Capture Canvas Image command in Allegro PCB Editor release 17.2-2016
4 z- q7 x% b/ Q$ b, P2 R1710310 ALLEGRO_EDITOR UI_GENERAL 'Capture Canvas Image' command is absent from the file menu in PCB Editor in release 17.2-2016! L- x! S9 _+ b2 t- l G$ v
1718407 ALLEGRO_EDITOR UI_GENERAL Reintroduce the Capture Canvas Image command
$ Z' C; p$ _7 E. W$ B4 F, J1729699 ALLEGRO_EDITOR UI_GENERAL Capture Canvas Image is not present in release 17.2-2016
) w; P# ` @, O) k. Y% ]1753234 ALLEGRO_EDITOR UI_GENERAL Capture Canvas Image missing from the File menu
8 r' p/ n7 z/ J# N, ?1754222 ALLEGRO_EDITOR UI_GENERAL Need command to capture view window as image in release 17.2-2016
! O9 v4 q9 C2 ^# U6 I9 Y$ k+ V% K1794348 ALLEGRO_EDITOR UI_GENERAL Reintroduce Capture Canvas Image in PCB Editor in release 17.2-2016. [7 A5 n. H6 W6 `4 T
1818610 ALLEGRO_EDITOR UI_GENERAL Restore the option to capture canvas image in PCB Editor in release 17.2-20168 n$ l# y3 T: {7 g }
1844591 ALLEGRO_EDITOR UI_GENERAL Reintroduce 'Capture Canvas Image' in release 17.2-2016* W5 L, s3 u1 e- N7 F8 j
1869380 ALLEGRO_EDITOR UI_GENERAL File - Capture Canvas Image missing in release 17.2-2016
$ |, d7 m, d0 S% Z. m5 y( N1889412 ALLEGRO_EDITOR UI_GENERAL Cross-probing between two boards in release 17.2-2016
1 A" O }" G) c. |1 R- E! P( ^1922329 ALLEGRO_EDITOR UI_GENERAL Add the 'Capture Canvas Image' command in release 17.2-2016! Y5 i4 g5 ?* i
1932070 ALLEGRO_EDITOR UI_GENERAL File - Capture Canvas Image is missing in release 17.2-2016: x) o4 Q& K" W0 \ k8 X- Y
1885594 ASDA PACKAGER Export to PCB Layout exits without reporting error when Netrev fails
' _4 g1 j# M0 G. `1 u1931657 ASDA PACKAGER Export to PCB Editor does not work for a project
# o _& u. H& v/ _! Q1937757 ECW METRICS SDA metrics not getting collected* b7 q6 m( X% a7 {
1934482 EMI SETUP EMControl function flow is not working correctly in release 17.2-2016
, T/ f( K: [% m2 K+ |2 y+ Z1931623 SIP_LAYOUT EDIT_ETCH Shapes are not updated and force update does not work
$ P9 z- F7 T% u% P+ W0 [+ C' u3 i7 U+ ?
% R' x7 \7 f0 w) z9 r1 i
Fixed CCRs: SPB 17.2 HF041
6 c2 w" q* c# I9 o1 U% X2 P06-9-2018
; Y; g- m6 r6 L========================================================================================================================================================
. v! t9 s' U) Q$ b2 g/ ]( QCCRID Product ProductLevel2 Title" R; d8 X# q6 g9 t
========================================================================================================================================================0 V5 h- }! x9 }2 M- ] U
1880083 ADW ADWSERVER ALM fails to connect and authenticate LDAP server$ N0 J# B; y ?2 E) f0 k3 W7 y- j* e
1922218 ALLEGRO_EDITOR 3D_CANVAS PCB Editor stops responding when 3D Canvas is opened for a symbol
( v( ?' d+ n1 [0 ~9 c1915838 ALLEGRO_EDITOR DFM Outline to non-signal geometry is not working for non-etch layers in design
% o: }' o% B8 @) {* \6 \& C! U1925263 ALLEGRO_EDITOR DFM False minimum spoke count DRC
: N6 c5 a2 \8 J0 i1895486 ALLEGRO_EDITOR INTERFACES Importing IPF displays error regarding line being outside drawing extents (SPMHMF-409). i: P$ H6 A; M/ ]( e: o% {6 I
1927266 ALLEGRO_EDITOR INTERFACES Miniaturization license required when using enterprise licenses3 C% ?& P; y8 C x# D' S8 R" i
1912186 ALLEGRO_EDITOR IN_DESIGN_ANA Coupling analysis on one net takes a long time
9 ?! b. h& i m8 W1916015 ALLEGRO_EDITOR NC Improve the message for reporting unsupported characters in the directory path while generating NC Drill data- \9 \, K J L. @9 i/ c; m
1926072 ALLEGRO_EDITOR SHAPE Dynamic shape to route keepout not voiding correctly
, [' I+ N0 X. X C8 H1903202 ALLEGRO_EDITOR UI_GENERAL HTML report dialog does not handle relative links to files correctly
0 |( _- w E1 N# a7 U6 z) X1880684 ALTM_TRANSLATOR CAPTURE Importing third-party schematic is not working in Capture/ D/ Q/ V& F0 ^0 _1 r! l
1870218 ALTM_TRANSLATOR DE_HDL Unable to translate a third-party design to DE-HDL, ] a: i" p% d) E' `
1881208 ALTM_TRANSLATOR DE_HDL Third-party to DE-HDL translation: schematic symbols missing all pins
V# r$ [* S3 v. O1889909 ALTM_TRANSLATOR DE_HDL Third-party to DE-HDL and OrCAD Capture translator fails with error message or crash
3 Q8 W2 Z4 c. D9 W! F1924375 ASDA NEW_PROJECT SDA new project path truncated at ellipses
. X. O4 }0 t" W1 D* v1900957 ASI_SI OTHER axlLicDefaultVersion() in SKILL console crashes PCB Editor in release 17.2-2016 and works in release 16.6
% o( f) y9 r) R$ l9 N$ N) g( Z, N1918499 CAPTURE NEW_SYM_EDITO Text in new Part Editor is always left-justified and justification cannot be changed
1 i* _ k/ X' O6 I1921505 CAPTURE NEW_SYM_EDITO Error if property name starts with the less than character '<'
) k1 n- x' \% B% J1924273 CAPTURE NEW_SYM_EDITO Error if property name starts with the less than character '<'
' j; m' ~: ^2 w* @3 w1924332 CAPTURE NEW_SYM_EDITO Capture reports an error when editing pin numbers where names contain the less than character '<'
; m! o5 H! V2 i. o7 N; [' j- d( h- t1934655 CAPTURE NEW_SYM_EDITO Properties populated in older release show up blank in new Symbol Editor
# Z. [- Y6 r/ N9 U1855851 CAPTURE OTHER Crystal Reports not working in release 17.2-2016$ R8 k, m, d+ J) T$ b2 ?7 q W
1918048 CAPTURE PART_EDITOR Unable to modify pin type and shapes for multiple pins simultaneously in new Part Editor ~, h6 k# k$ e
1919459 CAPTURE PART_EDITOR Part Editor background display color is not consistent when zoomed out/in
& D( E6 U& |! y3 _0 F1920078 CAPTURE PART_EDITOR Option needed for updating pin type of multiple pins in the 'Edit all pins' menu! W6 S6 K' I c3 d, Z- |3 p
1922785 CAPTURE PART_EDITOR Cannot place pin array with zero in the suffix in Symbol Editor c1 b: D! ?8 n3 d2 P
1922831 CAPTURE PART_EDITOR Symbol Editor redraws when scrolling with non-default background and when zoomed out. j, o- h7 [$ v& G' x
1923772 CAPTURE PART_EDITOR Placing pin arrays results in error8 D' {8 {/ z2 L
1888897 CAPTURE SCHEMATICS Capture slowly redraws schematic page. ?5 |! j) }( L
1910087 CONCEPT_HDL CORE DE-HDL crashes when adding Current Probe to a design) Q) V- R% y8 _
1930364 CONCEPT_HDL CORE SIGNAL_MODEL properties not deleted on importing release 16.6 DML design into release 17.2-2016 non-DML design y' a, r! j2 L- l7 {5 y& s
1920716 CONSTRAINT_MGR CONCEPT_HDL Issue with the passing of physical and spacing CSets between Design Entry HDL and PCB Editor) y) V: R. X; I5 n, f) r" U
1902591 ECW OTHER Flow Manager reports a digital certificate error when launched with Pulse7 `/ }; O' [, l- u: N/ B
1926029 PCB_LIBRARIAN GRAPHICAL_EDI PDV Symbol Editor opens to a blank page in release 17.2-2016
0 L! D/ W( l7 U+ `1884694 PSPICE ENCRYPTION User-defined library encryption is not working as expected% E2 C" y7 K; J* M5 d7 p
1927537 SIP_LAYOUT ASSY_RULE_CHE SiP Layout crashes when running manufacturing checks on specific designs
! Z: s/ O: p; A8 K1878733 SIP_LAYOUT CROSS_SECTION Layer Function and Manufacture fields in Cross-section Editor are grayed out for soldermask layers in SiP Layout, [, G3 {7 P; Q0 A* f3 P
1900628 SIP_LAYOUT CROSS_SECTION Board thickness in Cross-section Editor does not change even after soldermask layers are added5 D% Q6 j* K2 i# G6 b' ^
7 Y, L. `) {) a8 c6 U
- c5 _* [! w D# Q9 H. uFixed CCRs: SPB 17.2 HF040( r2 G( F& R0 b7 V, I" N
05-27-2018
; v" A# e. W t. G: o========================================================================================================================================================
a1 _* F9 D) P1 |CCRID Product ProductLevel2 Title
1 [7 o% M0 b4 u2 q" `$ @========================================================================================================================================================, ~& X( c. ~* R+ m
1924541 ADW CONF Designer Server configuration cannot be completed. X- U8 N# i7 V1 w
1906973 ADW DBEDITOR Rename attribute fails to preserve values in affected parts
, g/ Y, `, @6 e7 O* m1718524 ADW FLOW_MGR FM: Find Projects does not find any projects when Project Path contains a period
1 G0 M9 x9 W) P+ A' b* ]1803310 ADW FLOW_MGR EDM Find Project no longer supports dot in the project path- P/ C$ Z6 D. v l- u
1916898 ADW FLOW_MGR Flow Manager does not recognize projects with a dot in the path8 C% `) V" X, W' V. D7 @9 n
1887669 ADW LIBDISTRIBUTI ptfgen displaying Java errors, T9 K* d2 n$ V+ h, T1 `7 |0 O# ~* {
1897991 ADW LIBDISTRIBUTI ptfgen fails with error LIBDIST-1062 in library distribution.
8 r/ t0 E( l8 \' [; Z# S0 F1915319 ADW LIBDISTRIBUTI ptfgen should rerun with the -rewrite2db option automatically- W! j: [4 @! A
1920309 ADW LIBDISTRIBUTI Java exceptions in the ptfgen log file
! J. i) ^, d0 l9 g1914706 ALLEGRO_EDITOR DFM False Mask to trace DRCs/ C. D: e1 J3 g: {/ ^# V
1912290 ALLEGRO_EDITOR GRAPHICS Infinite PCB cursor: symbol move results in symbol trail and disappearance of cursor and symbol
, l) ~/ @2 v8 n9 p7 n$ X1927425 ALLEGRO_EDITOR GRAPHICS Infinite PCB Cursor disappear while moving objects on layout
; p2 Q* |7 S4 W8 V1 r1908867 ALLEGRO_EDITOR INTERACTIV PCB Editor crashes in release 17.2-2016, Hotfix 036 and 037
$ B3 S2 C' c' u. S1906116 ALLEGRO_EDITOR IN_DESIGN_ANA Allegro Integrated Analysis and Checking: Coupling vision shows the influence of voltage net
. }# T* L5 U! a7 K6 Q1918161 ALLEGRO_EDITOR MULTI_USER Symphony crashing and clients disconnecting from server cannot leave session, error applying DBupdate7 j# R3 ?. K E! p1 f
1919467 ALLEGRO_EDITOR MULTI_USER Random crashes while routing design in Symphony
: Y( Q7 v$ W! s- b; L0 p( u1918702 ALLEGRO_EDITOR SHAPE Differential Pair vias not voided in a split plane2 {- n/ r0 x1 F u0 a# s1 b- r: D7 `7 v
1905109 ALLEGRO_EDITOR UI_GENERAL PCB Editor randomly stops responding in release 17.2-2016 in Linux
1 @$ t) n' `8 q; c1 R0 X6 j1882365 ASDA CANVAS_EDIT SDA - body changes but not properties when changing version of a symbol
" O* k8 H8 T% H6 M1900370 ASDA CANVAS_EDIT Version command in SDA should use placeholders from selected version
; ?5 I: j1 y; `. U4 L1901120 ASDA CANVAS_EDIT Choosing a different version of a placed component does not use the property placeholders as per the new symbol i/ `3 v" `7 ?- o* R
1907497 ASDA GRAPHICS DNI Cross Mark much larger than Components' n' g% w3 c1 _# Z* {8 G( y
1895135 ASDA MISCELLANEOUS Design created in SDA has the cds.lib containing a pointer to worklib3 ?2 T8 V: z+ U" Y L
1895139 ASDA MISCELLANEOUS Irrelevant warning related to worklib when running checkplus on SDA design
' `1 e; w+ M% o0 k) ^; m# o# a. s+ Y1920753 CAPTURE LIBRARY JavaScript exception reported on opening part with name containing '\' in hotfix 0384 d3 [/ t/ Z: e/ v% x0 ~; V; t1 D
1925848 CAPTURE LIBRARY New (QIR6) Symbol Editor has Script error / SR 600037969
/ B8 x! Y* m( M/ ?# @1916991 CAPTURE NEW_SYM_EDITO New part/symbol editor ignores grid color set in Preferences
n q) ^; O9 ?& i# [% Y& i1917090 CAPTURE NEW_SYM_EDITO New symbol editor goes into permanent pan mode on clicking the middle mouse button2 Q# v& T; P, Y; G; j
1918041 CAPTURE NEW_SYM_EDITO Saves As for symbol in library from new symbol editor saving 0 byte files: r9 }7 H* w+ c! ]+ y
1918497 CAPTURE NEW_SYM_EDITO Moving multiple items using the arrow keys results in error in new part editor
$ t% z2 \! m* D! j8 D2 g1918711 CAPTURE NEW_SYM_EDITO Unable to do a Save As from a Library part to change the name
! V1 g. x8 K0 F# n* t; J* R. M1920889 CAPTURE NEW_SYM_EDITO Unable to edit symbol with name containing '/'' A: t1 K( f1 o+ L
1922123 CAPTURE NEW_SYM_EDITO Save As for symbol in library from new symbol editor saving 0 byte files4 V- C" y1 ]3 q% w
1922276 CAPTURE NEW_SYM_EDITO Space between pin name and pin for names having bar2 e9 Y# M+ z: ?9 H0 Q
1922282 CAPTURE NEW_SYM_EDITO JavaScript exception on closing new part editor window using keyboard shortcuts
; Q4 \+ H2 O( z1923526 CAPTURE NEW_SYM_EDITO Unable to "Save As" in new symbol editor.4 G0 h7 L! S+ Z, G, Y" @
1927262 CAPTURE NEW_SYM_EDITO The File > Save As command in version 17.2-s038 differs from earlier versions
2 V/ s& Q* ^! G q: I1919322 CAPTURE PART_EDITOR JavaScript exception on opening parts and creating new part using right-click8 U3 y$ A* s% ^& l2 o
1914183 CONSTRAINT_MGR XNET_DIFFPAIR ECSet fails to map in PCB Editor but maps fine in DE-HDL' @2 Z" V5 ^, v2 ~1 D& P" `
1908102 ECW DASHBOARD Some lines in Design Dashboard in Pulse are grayed out% J- d, R; k3 j) z. ~
1914812 F2B PACKAGERXL Hierarchical variable not evaluated3 Z* [. j* W: m
1639231 PSPICE ENVIRONMENT Remember last location in simulation settings* B$ {) J$ j( I+ {
1804391 PSPICE ENVIRONMENT Libraries with uppercase extension (.LIB) not retained if added using 'Add to Profile'
) x3 q7 S3 \4 o. D1879915 PSPICE ENVIRONMENT Check points cannot be loaded from a directory with space in its name2 y9 @# Q7 r9 w
1695306 SIP_LAYOUT STREAM_IF SiP Layout - Stream out issue: Embedded or stacked components using pad reference in more than one layer! j2 k+ C: P% G! W
/ p; c0 l, t! N( x! U8 f2 h* Y$ A" S
Fixed CCRs: SPB 17.2 HF039# y7 v6 m& l4 H2 V W
05-11-20183 H' b( R( Z2 g! ~& A
========================================================================================================================================================
6 `$ s% Z5 B' {5 mCCRID Product ProductLevel2 Title
! y- d* W3 B: A7 A2 K* |1 Q) N========================================================================================================================================================
7 K$ D3 |; u( C3 d1915149 ADV_PKG_ROUTER OTHER Auto-connect fails to initialize when rats are selected, but works with bundle( K3 w6 b! f' ~( q8 O; s
1870109 ADW ADW_UPREV Most mandatory properties turned into optional properties following database uprev6 [/ D. W( m9 F) _
1758396 ADW CONF Server Memory setting in setting.ini is lost if server is re-configured using Conf
( n, J/ c) s3 Y0 ^7 Q1911591 ADW FLOW_MGR Flow Manager does not start on high latency (> 25ms) networks: displays Java Content Disabled dialog# r0 u4 {+ H6 u# i. y
1887861 ADW LIBIMPORT Library Consolidation reports front2back issues but does not provide information about the issues.$ h9 P7 t1 b* o( }6 x ]
1778977 ADW REPORT_GENERA reportgen memory setting too high in release 17.2-2016 resulting in launch failure
3 Y. g3 ~$ N" E. g2 n/ g4 m1900422 ADW REPORT_GENERA Save in reportgen does not save Preferred Part List entry into .rep file
m& Q# k5 s6 ]3 U G7 C8 N* E1903888 ADW REPORT_GENERA Report generator not outputting values as expected for PPL field6 r8 Y& t8 c; h* ^% ^7 _
1916903 ADW REPORT_GENERA Reportgen -gui is not producing the expected result
- A9 a8 T3 G5 A7 d4 s1902184 ALLEGRO_EDITOR DATABASE Add connect in package symbol crashes PCB Editor when using the 'clearance_view' variable
9 s0 F$ V% v2 t8 h# _7 h" h. L1914793 ALLEGRO_EDITOR DATABASE Updating shape crashes Allegro PCB Editor
3 ~: H8 ~7 V q, D+ u1905138 ALLEGRO_EDITOR DRC_CONSTR Max Via count DRC disappears on running DRC update/ l, m( c4 y n5 y5 H$ t
1848015 ALLEGRO_EDITOR MANUFACT Export Creo View cannot find the webpage on the PTC site9 K6 P& w, K0 k0 s K
1850553 ALLEGRO_EDITOR MANUFACT 'File - Export - Creo View' is not working
2 M2 s* E+ \+ M( j; e6 I% D$ F1853960 ALLEGRO_EDITOR MANUFACT PTC Creo Interface link is broken% n/ {! @/ E# p* `6 [4 I/ f, A
1862305 ALLEGRO_EDITOR MANUFACT PTC Creo interface link is not working
+ x/ g% H" U$ S+ x4 A1878682 ALLEGRO_EDITOR MULTI_USER Delay in Symphony server session when server is started from Allegro PCB Editor0 g I1 B+ H" I6 q" X$ K
1890108 ALLEGRO_EDITOR MULTI_USER Database rejections in Symphony# T; t# l8 C1 T/ G2 C0 `1 |# c9 V O
1887331 ALLEGRO_EDITOR NC Milling (NC route) in Gerber tools is not the same as what it is in the board.2 P0 ]2 {4 Y' B& |; g6 `
1898179 ALLEGRO_EDITOR RAVEL_CHECKS PCB High-Speed option required for high-speed rules when Venture license is selected6 v) \5 E9 V+ Y2 U& D6 F: H
1461142 ALLEGRO_EDITOR SHAPE Pin with nearly-tangent via fails to generate void in dynamic shape, results in short.
d x. }* P8 [( y6 j1863467 ASDA CROSSPROBE Highlighting all parts in PCB Editor does not highlight all parts in SDA
9 ?5 f8 g% r+ m1910974 ASDA CROSSPROBE Cross-probing between SDA and PCB Editor does not work
6 e7 f$ T4 A: V) Q8 j1904440 CONCEPT_HDL CORE SPCOCD-577 error on migrating from release 16.6 to release 17.2-20166 v. n0 y8 N+ V* s+ ]6 b; w {% F1 P
1909611 CONCEPT_HDL CORE DE-HDL stops responding on running '_movetogrid' and clicking 'No'2 J' V" V# Y6 X$ f( T
1808743 CONCEPT_HDL PDF Inconsistent display of Publish PDF hyperlinks$ F: P8 z( M2 l: Z# r
1894868 CONCEPT_HDL PDF XREFs getting clipped in the Published PDF4 A& O2 ^0 t+ z4 L) e
1911676 CONSTRAINT_MGR CONCEPT_HDL DE-HDL Constraint Manager crashes on selecting ECSet and then creating pin-pair option
$ @: L' l! [! q) u1913968 CONSTRAINT_MGR CONCEPT_HDL Match Group pin-pairs are not created on applying ECSet to differential pair
$ {9 V" V7 L8 H. u l1899638 CONSTRAINT_MGR XNET_DIFFPAIR Differential pair buffer models are extracted differently in release 17.2-2016 and release 16.6
1 Z( s' @0 X9 A# u2 Z3 R' B4 p! W1914116 ORBITIO ALLEGRO_SIP_I Unable to import OrbitIO file to SiP Layout
+ V# {, ]# t7 B; F1 O1896487 PCB_LIBRARIAN GRAPHICAL_EDI Use lower-case characters for notes and pin text in New Symbol Editor. f$ t% `" `, o% J' y
1898008 PCB_LIBRARIAN SYMBOL_EDITOR Styling is not available for custom shape and pins.
1 W7 _$ [$ K) D- p2 [2 b1644787 PSPICE FRONTENDPLUGI PSpice Model Search window does not show complete library path
$ J9 ^: L2 C. `4 U* V1785939 PSPICE FRONTENDPLUGI PSpice Part Search library browser should display path of the library directories% k+ j" r6 V! B+ Y; {0 M
1855867 PSPICE FRONTENDPLUGI PSpice Model Search window does not show complete library path1 k% U$ d* e9 y" m0 P8 X% b* `* c
1887016 PSPICE SIMULATOR Pseudotran should always be invoked first time in case autoconvergence is ON
6 I. r: v# }& t( r1 B6 K/ j8 E1895752 SIG_INTEGRITY OTHER Layout Cross Section: Wrong Differential Impedance calculation (0 ohms) in RHEL Linux 7.1 or later versions
: Y; h1 b7 V5 s9 [1 p1895759 SIG_INTEGRITY OTHER Cross Section does not calculate correct differential pair impedance in Linux CENTOS 7 and gives 0 value, c- S, v& `9 u0 ]" G Z- F
1909257 SIP_LAYOUT INTERACTIVE Error 'E- (SPMHGE-639): Copying component with bond wire is not allowed' when copying SMD symbols# ]0 W1 t1 Z3 W/ s1 c" h
1900970 SIP_LAYOUT SHAPE Shape does not void around SMD Pins and Vias inside pad0 t4 {& l) D1 h- }, s; D- n! q2 r% F
1885496 SIP_LAYOUT SYMB_EDIT_APP Pin Numbering: different results for release 16.6 and 17.2-2016 for the same case.
9 x0 l0 A* t9 y2 y }1907796 SIP_LAYOUT SYMB_EDIT_APP SKILL commands fail to change pin number in SiP Layout$ n0 y1 r0 ^+ x: Q# O# q' x
1887703 SIP_LAYOUT WIREBOND On trying to add wire bond to a die, SiP Layout crashes displaying a restart message
: O% a8 L/ [5 q" @+ ~2 |& f* d1903081 SPECCTRA LICENSING PCB Router is failing in Linux 7.1 in release 17.2-2016& p& y3 g* T3 j% V; q- p
1721606 SPECCTRA ROUTE PCB Router stops responding on exit if opened in the stand-alone mode* ~3 g# R+ ^2 x* G v& ]
1844366 SPECCTRA ROUTE Allegro PCB Router will not exit+ O0 P* B, {; @' j
1873716 SPECCTRA ROUTE PCB Router does not close if opened from Allegro PCB Editor or in the stand-alone mode+ ]9 Y" e3 {2 E9 w3 b* v
1907703 SPIF OTHER PCB Editor crashes on choosing 'File - Export - Router' in release 17.2-2016
1 Z; ^: ]! G5 D0 E& a1889059 VSDP DIEEXPORT Incorrect pin location if bump cell origin is not at lower left for rotation other than R0
p5 ^3 H) E1 U0 ^# O9 u7 |! M9 X. V' q0 s/ g- [+ S2 `
+ o8 D5 l3 M; {
Fixed CCRs: SPB 17.2 HF038
2 z( g+ X& F( D, C04-27-2018# a! k: c# c! W ]% j' g8 F
========================================================================================================================================================
6 b' Q7 j" R2 F' l% mCCRID Product ProductLevel2 Title
' Z$ c8 [7 ~- `, w7 H# |========================================================================================================================================================
& e, q' S) j# N7 X% `0 v1861616 ADW TDO-SHAREPOIN Team Design Option requires Allegro_ECAD_Collab_Workbench license feature
3 j$ Q4 t7 X# \1784170 ALLEGRO_EDITOR 3D_CANVAS Allegro 3D Canvas does not show the flex zone thickness correctly
7 U8 h2 I0 H, j7 u1801053 ALLEGRO_EDITOR 3D_CANVAS Moving component in 3D Canvas does not move the pads0 j7 V% E( \$ } a
1805038 ALLEGRO_EDITOR 3D_CANVAS Soldermask and drill not refreshed when component is moved in 3D Canvas, or on the board with Canvas open0 U) |2 G0 r# G# o5 }$ S
1808579 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas displays annular ring incorrectly) i" h$ X3 u/ K3 u$ `1 P B @
1816732 ALLEGRO_EDITOR 3D_CANVAS Mismatch in shape width between board and 3D Canvas
2 ~6 ^7 n. T) j: e* _& G: P1822778 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas does not display nets when selection is done through click drag8 f D& g& @" A8 }( ?4 ^
1838129 ALLEGRO_EDITOR 3D_CANVAS User is not able to create a pastemask layer that is visible in 3D Canvas. j' v2 l/ j( J0 b- h. F a
1842911 ALLEGRO_EDITOR 3D_CANVAS Etch shapes not visible in the 3D Canvas when invoked from a symbol drawing7 ~1 w$ O8 L6 A2 e
1849380 ALLEGRO_EDITOR 3D_CANVAS Mirrored components placed in flex zones are not displayed in the 3D Canvas0 }; V/ D7 H# s7 ]! [& d
1851898 ALLEGRO_EDITOR 3D_CANVAS STL export from 3D Viewer scales it up by 100+ B$ G x6 q* \* V; U) i$ ^# G
1853378 ALLEGRO_EDITOR 3D_CANVAS The new interactive 3D Canvas has a display issue with the off-centered drills.4 I& u4 u' q' Y6 y" W \6 n5 t
1859713 ALLEGRO_EDITOR 3D_CANVAS PLACE_BOUND shape with package_height_max and package_height_min set displayed incorrectly in 3D Canvas
7 q y8 O) u* T$ K4 a1880073 ALLEGRO_EDITOR 3D_CANVAS Design Outline is not displayed correctly in 3D Canvas; m: ^& [6 B9 |. B" r
1880338 ALLEGRO_EDITOR 3D_CANVAS Step Model missing in interactive 3D canvas., v0 E- r4 R7 R5 s
1881889 ALLEGRO_EDITOR 3D_CANVAS Changing the color of STEP model in STEP Mapping Window does not display this color in 3D Canvas.! A4 _. M# \" @: h! O9 L0 x. Y! v
1889861 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas swaps padstack from Bottom to Top
# p6 e* B1 W2 c3 m& F1830749 ALLEGRO_EDITOR ARTWORK Gerber 4x and 6x output do not fill the shape
$ e7 S) F ^3 W6 U( r1848514 ALLEGRO_EDITOR COLOR axlVisibleDesign does not interact with wirebonds) @( R- L) y2 c4 c+ z
1837388 ALLEGRO_EDITOR CROSS_SECTION Cannot add solder mask to the site layer mask file
" }! f, F( U& k7 [8 c3 J1859797 ALLEGRO_EDITOR CROSS_SECTION The Report only option does not work when choosing Setup - Cross-section - Import - IPC25815 M! m7 j/ B ]. l& i" }/ u
1877858 ALLEGRO_EDITOR CROSS_SECTION Dynamic Pads Suppression option is not working correctly7 m# k% w6 _1 D1 i1 x
1880093 ALLEGRO_EDITOR CROSS_SECTION Unused Pad Suppression options are not working correctly and are reset on opening cross-section
: I) L7 \ E0 Y. B1886283 ALLEGRO_EDITOR CROSS_SECTION Unable to turn on 'Dynamic Unused Pads Suppression'7 k5 u) c2 [! ]( \" {( I" R2 r
1890959 ALLEGRO_EDITOR CROSS_SECTION Dynamic Pads Suppression option is not working correctly- }. V9 ?# T+ i0 V
1900397 ALLEGRO_EDITOR CROSS_SECTION Dynamic Unused Pad Suppression option in Cross-section not working at one go.
; D8 y2 O" L5 L" I& M8 d5 s/ x1905315 ALLEGRO_EDITOR CROSS_SECTION 'Dynamic Unused Pad Suppression' cannot be turned on.7 i4 b2 T% e8 K L# D
1861406 ALLEGRO_EDITOR DATABASE Refresh symbol for flex zone not mapping padstack layers correctly
9 w1 B( q' S* Y, c" I# d7 Y1877132 ALLEGRO_EDITOR DATABASE Fail to open #Taaaaed17598.tmp file and save database, n5 ?$ I! M& j6 q/ ]$ X- N
1883747 ALLEGRO_EDITOR DATABASE PCB Editor crashes on stackup modification3 h# F# w, o( J* e5 ~
1860238 ALLEGRO_EDITOR DFM Applying a DFF constraint set closes PCB Editor instantly
$ D/ ^# {' T: f( _1872780 ALLEGRO_EDITOR DFM DFF false pin to via DRCs: Copper Spacing, SMD pin Pad to Thru Via pad- _# s q1 ^9 z* [* s- X
1823912 ALLEGRO_EDITOR DRC_CONSTR Thru pin to Thru pin DRC between Symbol Pin to Mechanical Hole (with NO regular pad)
' X" m. }$ z# `% s1828168 ALLEGRO_EDITOR DRC_CONSTR Upgrading from release 16.3 to 17.2-2016: Differences in spacing constraints
4 \. ]# F! n+ ?; W; M' y1844780 ALLEGRO_EDITOR DRC_CONSTR Mechanical Pin to Shape Air Gap value is reduced when updating shape5 x' ~% Y1 k) F3 l" L
1845011 ALLEGRO_EDITOR DRC_CONSTR When upgrading from 16.6 to 17.2, Spacing constraints for shape to mechanical pin not being resolved properly, _. v+ k( n, ^' d0 C
1861548 ALLEGRO_EDITOR DRC_CONSTR Inconsistent Micro via to Micro via drill to drill overlap DRCs6 H J: ^: k- ?
1862281 ALLEGRO_EDITOR DRC_CONSTR Mechanical Pin/hole to Shape spacing too small
" o, E3 w& E! q7 T" T1887145 ALLEGRO_EDITOR DRC_CONSTR Mechanical pin to conductor spacing setting is overriding constraint region in release 17.2-2016% i% S1 j3 b/ O. E' m2 ~
1893012 ALLEGRO_EDITOR DRC_CONSTR Shape voiding not taking the shape to hole spacing rules for NPTH
, b r4 h' U/ E7 Q" ~2 Z' W. U1906840 ALLEGRO_EDITOR GRAPHICS Context menu stays when PCB Editor is minimized.
7 R. b( E8 G& B9 [+ {" J+ S1738624 ALLEGRO_EDITOR INTERACTIV 'Invalid Sector' error when saving psm file for symbol that has die pads, which are copied) F! P4 {$ Y3 O* m. F: }
1800741 ALLEGRO_EDITOR INTERACTIV Search in User Preferences Editor is giving incorrect results, J0 _$ j: o5 C" k7 z! d& P4 h3 f, |
1812530 ALLEGRO_EDITOR INTERACTIV PCB Editor crashes when opening a file that is in an unsupported format E$ f# E" `: w' U( b
1812570 ALLEGRO_EDITOR INTERACTIV PCB Editor hangs when an invalid pin number value is specified as the rotation point in the symbol preselect mode X" D% z" A7 l8 ~9 }+ N! {! U. W
1826819 ALLEGRO_EDITOR INTERACTIV 'Route - Resize/Respace - Align Vias' menu is not available
+ q5 ^5 h) L* Z- m7 ?0 ^' R1842645 ALLEGRO_EDITOR INTERACTIV Via align command is missing from the menu path
, y% N# t, E2 V' p1845748 ALLEGRO_EDITOR INTERACTIV With 'Shape - Change Shape Type' enabled, changing visibility reverts the Shape Fill selection to dynamic copper.
# M' ^& j/ z! d+ U' i1849700 ALLEGRO_EDITOR INTERACTIV Add the reason for generating DBFIX_PAD, to the dbdoctor.log.
4 U: [: {7 X% k9 H1860934 ALLEGRO_EDITOR INTERACTIV Auto-Paste environment variable is not working as it should9 j, o! ?& C0 H
1861928 ALLEGRO_EDITOR INTERACTIV Provide a Persistent snap pick option for Display - Measure. O2 \4 _- `# k& _1 l
1864238 ALLEGRO_EDITOR INTERACTIV Shape place rectangle issue: Dimension of placed rectangle changes on cancelling action
6 W. X: l& u4 x+ y/ D+ H1877026 ALLEGRO_EDITOR INTERACTIV Filled rectangles on ETCH/TOP and ETCH/BOTTOM are not getting copied; l! c6 c, u5 b# h6 F+ h3 F1 p* S) g
1881637 ALLEGRO_EDITOR INTERACTIV Radius of Shape changes when trying to place circle using Place Circle mode.
, l e" f6 @4 {+ m; E1883032 ALLEGRO_EDITOR INTERACTIV Find by Query does not find all padstacks in a symbol drawing0 F. f; i+ q. q
1855248 ALLEGRO_EDITOR INTERFACES The Technology Dependent Footprint command returns an error
+ q+ m8 ?# _6 l1885716 ALLEGRO_EDITOR INTERFACES Increase supported STEP model size to enable the use of models larger then 500MB
$ o# y n+ L6 K* r8 j1860835 ALLEGRO_EDITOR MANUFACT Display a message when backdrill_max_pth_stub is defined for vias or pins only
% G% _2 \3 Q2 {% d1869528 ALLEGRO_EDITOR MANUFACT Backdrill out of date when deleting Teardrop and Sliding cline with Teardrop5 `& p7 f! s6 o0 k- t7 @5 X
1885672 ALLEGRO_EDITOR NC NC drill is creating false backdrills when repeat code is turned on in release 17.2-2016
: a1 Y$ G* d( Z( R& z1895084 ALLEGRO_EDITOR NC Padstacks with backdrill data trigger backdrill out-of-date even if the board is not set up for backdrilling
' k& w5 P, R! C7 ~" K6 O" l1837514 ALLEGRO_EDITOR PAD_EDITOR Offset is not consistent for keepout and mask layers in padstack editor.' X1 D+ ]$ c( S6 a/ H3 W; ~
1842902 ALLEGRO_EDITOR PAD_EDITOR Scrolling through the .pad files in the Library Padstack Browser displays Error(SPMHA1-161)
6 f7 o9 o2 k, n" T) V7 f1846504 ALLEGRO_EDITOR PAD_EDITOR COVERLAY_TOP definition lost while opening and saving a 16.6 pad in 17.2 padstack editor
4 q6 P+ J6 h0 F! v a1 ^, N/ r9 Q$ o2 b1879453 ALLEGRO_EDITOR PAD_EDITOR The 'Y' tolerance in the Padstack Editor does not update when changing the units of the padstack.# ]4 q0 I$ }& P. ?, l; X/ L
1805202 ALLEGRO_EDITOR PLACEMENT Place via array adds via on differential pairs incorrectly
* B) D, P ?% V& B1806675 ALLEGRO_EDITOR PLACEMENT Place - Manually - Quickview displays the Assembly Top details only
& G( x6 X% M7 d- Y9 I4 ]1835177 ALLEGRO_EDITOR PLACEMENT Can place symbol even after cancelling copy by choosing 'Oops' from pop-up! ]8 G @3 U8 I1 p7 Y
1846892 ALLEGRO_EDITOR PLOTTING PCB Editor Export PDF does not show lines correct for certain component
, ^' K" v8 s1 c' D) K8 z( A1006328 ALLEGRO_EDITOR SHAPE Static shapes should void around corners as dynamic shapes do
0 A; s- ]: t, Y1033326 ALLEGRO_EDITOR SHAPE Cannot compose lines to shape6 s# z- e( r- q" o1 e3 r
1045089 ALLEGRO_EDITOR SHAPE Dynamic shape voiding is inconsistent for solid and xhatch shape fill type- ^5 d( f- P: ]& B' O
1069959 ALLEGRO_EDITOR SHAPE Compose shape crashes PCB Editor* q9 S; {' ]+ _4 m& ?$ w% x
1085907 ALLEGRO_EDITOR SHAPE Pad does not get thermal connections to shape if outside of the shape outline by more than DRC spacing.
2 r% I* V. _; Q# J1143563 ALLEGRO_EDITOR SHAPE The pin void inline clearance does not seem to dynamically update the shape and requires a 'force update'.! H( i6 S9 \0 [; a! E) A. W
1243688 ALLEGRO_EDITOR SHAPE shape_rki_autoclip fails to clip shape to route keepin
1 p8 l% d& g; t+ B1 t8 \1269069 ALLEGRO_EDITOR SHAPE Shape void not working properly in release 16.5 hotfix 054) c" ?8 y' B0 \5 ~8 v+ U6 y
1327755 ALLEGRO_EDITOR SHAPE Need the ability to nest dynamic shapes on different nets partially or entirely3 R( J: w$ t Z: ?- u, C: B
1417394 ALLEGRO_EDITOR SHAPE Shape not updating correctly) ]! L2 ~6 b/ d! C4 l
1430742 ALLEGRO_EDITOR SHAPE When adding fillet to an irregular pad, the fillet might not be added or be strangely shaped6 ]- l# ?! F$ f8 U# e" B4 O- ? k3 w
1750760 ALLEGRO_EDITOR SHAPE Shape to Route Keepout DRC for a void that meets route keepout
! Y" e( N+ z: V* m* L1793898 ALLEGRO_EDITOR SHAPE Add teardrops fails to add anything with different settings, J, t/ v9 q/ k+ v; y# x
1811662 ALLEGRO_EDITOR SHAPE 'show measure' gives incorrect air gap value between two pins+ W! I) l( s5 S5 r6 ? k
1820901 ALLEGRO_EDITOR SHAPE The pins on adjacent layers are voided as Rounded Rectangle instead of Rectangular as defined in padstacks! N+ h8 Q- @! e% g2 y0 q+ G
1829570 ALLEGRO_EDITOR SHAPE Display measure airgap value is very large8 I H" J+ z" E9 M
1858696 ALLEGRO_EDITOR SHAPE The via to the edge of the board is not connecting to shape even with the PAD_SHAPE_TOUCH_CONNECTION property added
2 \# b/ r1 b: H8 b1873384 ALLEGRO_EDITOR SHAPE Boolean AND operation returning nil
4 L) d, p6 g0 @+ z: ^1873860 ALLEGRO_EDITOR SHAPE Copper shape does not respect route keepout; ^! Y0 A+ G; t4 B- N
1889312 ALLEGRO_EDITOR SHAPE Shape voided for net vias on adding 'PAD_SHAPE_TOUCH_CONNECTIONS' when enabling via suppression
5 \' ]8 ^# G3 T! S5 f& \. q& K1890702 ALLEGRO_EDITOR SHAPE Not able to add teardrop in release 17.2-2016( `# {2 o% c+ f, i+ g
1892692 ALLEGRO_EDITOR SHAPE Thermal relief connections being added to static shapes present in the void inside Dynamic Shapes( f7 U+ C8 G7 I7 [/ v* T
1893492 ALLEGRO_EDITOR SHAPE 'merge shapes' results in moved void; b/ b! G& h' v6 Y
1896543 ALLEGRO_EDITOR SHAPE Same net pin will not add thermal connection to shape if it is a rotated slot in the symdef+ S4 U: ~8 D# g9 S3 K) v4 n+ W
1897645 ALLEGRO_EDITOR SKILL axlCNSGetSpacing() returns nil if active class is non-etch." l9 Q' n, ?; S3 S$ P9 b5 X
1822364 ALLEGRO_EDITOR UI_FORMS Design Parameters dialog disappears if prmed is called while show measure is active
1 n" I" c6 |$ W; C# m3 V1 E1834395 ALLEGRO_EDITOR UI_FORMS Setup menu of OrCAD PCB Editor is missing the Anchor 3D View command# d" @0 w" z! l# I: M$ h# n' c, V
1838941 ALLEGRO_EDITOR UI_FORMS Anchor 3D View command is not available in OrCAD PCB Editor Setup menu
. w. G) L9 O5 W+ a2 B1716433 ALLEGRO_EDITOR UI_GENERAL Alias keys do not work until mouse scroll key is activated
5 i/ Q& ~. m( G9 C; M1721761 ALLEGRO_EDITOR UI_GENERAL During manual placement of symbols, hovering over symbols does not highlight them( v6 Y4 \' g+ x. ?4 l
1732915 ALLEGRO_EDITOR UI_GENERAL Alias does not work in release 17.2-2016 when switching windows
$ D* }6 I, u( Q7 z# l; O6 _* b _$ ^1770723 ALLEGRO_EDITOR UI_GENERAL Funckey does not work if focus is not on canvas in release 17.2-20162 x4 n6 K' W: n e& l
1793839 ALLEGRO_EDITOR UI_GENERAL Function Key does not work if a form is opened by a previous command
" q, F! J3 F0 G+ ~: A D* b' @2 F1813961 ALLEGRO_EDITOR UI_GENERAL Inconsistent file formats available when saving reports1 s1 v# h- g: d% g0 w1 }
1816716 ALLEGRO_EDITOR UI_GENERAL Shortcut not working when using working layer with 'add connect'6 u% Y4 Q; F0 P2 D
1864321 ALLEGRO_EDITOR UI_GENERAL Funckeys not being registered after focus has moved to other window and back again in PCB Editor
9 M. l# c+ }4 N* R5 R1865010 ALLEGRO_EDITOR UI_GENERAL PCB Editor does not get focus when clicking shortcut after switching from any other program or application
3 ^& `- {/ H" C1 p" D. V, [- h' E1868708 ALLEGRO_EDITOR UI_GENERAL Allegro PCB Editor, funckeys stop working intermittently in release 17.2-2016, hotfix 0327 n- ^( e5 {. j3 s
1869745 ALLEGRO_EDITOR UI_GENERAL Allegro 3D Canvas window becomes active on pointing at minimized icon on taskbar2 {* z" i* q+ b1 S
1869860 ALLEGRO_EDITOR UI_GENERAL Hotkeys no longer functional on switching from PCB Editor to another application and then back again4 z8 _) k+ E" D8 x+ _4 l& [! l5 K" {
1870744 ALLEGRO_EDITOR UI_GENERAL Need html extension added to Save pull down menu.
6 z" w: r( W% z3 _5 b1870996 ALLEGRO_EDITOR UI_GENERAL If you switch from one active window to other, hotkeys stop working* x8 b6 Z( ~5 N5 L& `/ _' s
1883507 ALLEGRO_EDITOR UI_GENERAL Hotkeys stop working after Allegro PCB Editor UI window is opened
( o5 d. t8 U) s% f" a) m1886981 ALLEGRO_EDITOR UI_GENERAL Focus lost from layout when switching between PCB Editor and Capture! D4 N6 @3 \- u1 L# x
1887519 ALLEGRO_EDITOR UI_GENERAL Release 17.2-2016, hotfix 034: Shortcuts defined using funckeys not working correctly9 ^' V* t+ r# x ~
1887660 ALLEGRO_EDITOR UI_GENERAL Alias does not work in release 17.2-2016 when switching windows." R% u D" T/ h: ~
1891204 ALLEGRO_EDITOR UI_GENERAL PCB Editor crashes if SKILL form is closed using the Close icon ('X')
: F( J' x- |) j! \. |0 G1898059 ALLEGRO_EDITOR UI_GENERAL Funckey commands are not working consistently in release 17.2-2016% Q3 q, M- |+ ~) G4 T2 a$ e8 d
1902322 ALLEGRO_EDITOR UI_GENERAL Cannot use funckey commands when cross-probing
1 P! c# r# l- L7 |% {9 @0 `1905906 ALLEGRO_EDITOR UI_GENERAL Issue with keys and focus when navigating between windows0 e9 A$ y8 {! }( \7 m7 u
1913768 ALLEGRO_EDITOR UI_GENERAL Uppercase funckey shortcuts do not work
: y/ c# T9 c' V) o4 ^! u* [3 a1751586 APD OTHER axlGetMetalUsageForLayer() for etch returns value including pins and vias
& T7 a) w- ?( y# f1863241 APD SHAPE Fillet is left on the T-Point without Cline(center) connection.# R0 \8 I5 ~7 W) I+ D- Y% j
1894438 APD STREAM_IF APD/SiP Layout: Export rounded features as circumscribed and not inscribed polygon in GDS
: z2 @" I" l6 y1812699 ASDA AUTOMATION Enhance the performance when extracting data from SDA, using TCL functions9 L# o0 K6 J% l s9 \6 B% u) Y
1863436 ASDA CANVAS_EDIT alignment guides are not displayed when placing or copy a part, only when moving. They are most needed during placement, t/ }; b7 q' j7 V2 M1 |0 w2 n
1863445 ASDA CANVAS_EDIT Dark theme blue text in docked CM needs to be of a different color: difficult to read
5 I9 E/ y2 @4 ~# _) O" B1802111 ASDA DARK_THEME Dark theme in SDA should also change the border line color and text color of grid references: they are still black
* y+ i V, n/ Y- L, M( a8 c* w1869951 ASDA EXPORT_PCB File browser button in Export to PCB Layout flashes graphics of the window behind the form
% R4 N2 u( w) ~9 x8 n# n1845831 ASDA FORMAT_OBJECT Width of the twisted pair of wire should automatically be set to 6, otherwise it is not drawn correctly
4 \' y6 m, \/ P( l1879914 ASDA INTERNATIONAL Using French Keyboard cannot use the . (point) delimiter to set VOLTAGE property value: o0 T9 i9 [, ] \- l6 V3 x5 j/ ^
1865753 ASDA MISCELLANEOUS Inconsistent and non-ideal behavior in SDA product choice dialog, small box, hard to check unlike the bottom box
; u) `4 u3 g* y/ q7 u7 L1863457 ASDA PACKAGER Unset all user-assigned references globally
/ E; `% C4 L, m G3 o+ g8 @1889301 ASDA TDO SDA TDO Crashes when switching to/from Offline mode
+ ]) ?) I% V; j6 Z' f( A1823203 ASDA VARIANT_MANAG Variant setting part to not present does not do anything
$ p* E+ A* c: `6 U9 U1823992 ASDA VARIANT_MANAG Variant Editor fails to read netlist if a net is named NC5 m5 c& i5 k9 @
1863451 ASDA VARIANT_MANAG variant mode can select multiple parts to add to variant but can't select multiple parts to hit reset
& \" d+ a& P" u5 r# A6 O1863455 ASDA VARIANT_MANAG Cannot resize any panels in the Variant mode( L D9 U7 L) _& W8 A8 O8 n1 y3 v
1874952 ASDA VARIANT_MANAG Letter I in the alternate part icons in variant spreadsheet should be white for readability) X1 d' s p8 s& C
1878401 ASDA VARIANT_MANAG SDA Variant Display - DNI marker color switches between black and red/ X. \8 X3 G3 C+ V8 m. Y
1877239 ASDA WORKSPACE SDA DRC window is hidden if undocked and minimized
. ~8 f7 u+ F$ U- @6 l1809605 CAPTURE LIBRARY Part has pins in the incorrect order in the Connectors library
7 O6 R u. |8 [, b1638693 CAPTURE OTHER Capture Footprint Viewer not showing footprint.! A1 ~, L( }8 H5 R1 ?
1873612 CONCEPT_HDL COPY_PROJECT Copy project causes nets to be added to net groups and ports - fails to package due to mismatch1 l$ I1 q& W% \2 D& l6 W
1779289 CONCEPT_HDL CORE Adding a component and wire and saving the design results in a 'Connectivity save failed' error
2 {& v, P- v/ O5 T& I1878719 CONCEPT_HDL CORE Cannot enable or apply block variants at the top-level in a hierarchical design.
4 ^" q5 C* L, y% k# T* f1865480 CONCEPT_HDL OTHER 'partmgr -ptfMode shoppingCart' cannot output cell name with project ptf file into shoppingCart.xml* g* p: ?: g7 S) T( b+ y% c8 r
1829966 CONSTRAINT_MGR CONCEPT_HDL DML independent flow: Export Physical audits missing signal models in release 17.2
" A" c. } m' c% J7 ]. y8 T" v5 Q1904458 CONSTRAINT_MGR ECS_APPLY 'Audit - ECSets' crashes DE-HDL in release 17.2-2016, Hotfix 037
, m- E8 @) N) [7 D$ _1798269 CONSTRAINT_MGR OTHER Script changes '-' in layer name to '_'0 ^; e. O# B6 d1 _, D+ ?2 A
1835520 CONSTRAINT_MGR OTHER Cannot add members to netclass name with parenthesis" p- Z! E$ A# }4 i1 w
1896638 CONSTRAINT_MGR OTHER Constraint Manager worksheets jump abruptly: l0 H/ N+ L$ N/ |6 y
1801938 CONSTRAINT_MGR UI_FORMS Add To Netclass window: Focus not on ClassSelection
) V) i" H+ a1 d! M& \, g1854060 CONSTRAINT_MGR UI_FORMS Using the tab key in the Manufacturing workbook jumps a cell% K# |6 E8 O) m9 e9 i2 H; [" u
1881832 ECW ROLES_PERMISS Adding Users in SSO environment using PS is error prone* o5 U1 Q( ]- M8 T7 i2 \5 U4 I% m& a
1864870 F2B BOM Incomplete BOM report generated
9 `5 {2 ~9 X1 r$ v* V8 U1846578 PCB_LIBRARIAN GRAPHICAL_EDI radio buttons and clickable buttons are hidden in the UI for verify rules$ j6 g0 b/ m9 ~7 ?7 j
1854080 PCB_LIBRARIAN METADATA con2con needs to support special characters in Primitive Name
+ i) z7 C7 U+ p9 B, u1796377 PCB_LIBRARIAN SYMBOL_EDITOR Unable to move pins using arrows when symbol is opened in Symbol Editor; ^& U' j k! @. S
1839692 PCB_LIBRARIAN SYMBOL_EDITOR Properties tab grayed out in Symbol preview window& T9 F5 s }7 o% Y
1865657 PCB_LIBRARIAN SYMBOL_EDITOR Cannot change symbol properties using the General tab
0 p$ E6 |3 d/ f& v1906888 PCB_LIBRARIAN SYMBOL_EDITOR Properties button in Symbol Pins tab of the Symbols section is inactive.# @/ E2 A9 w8 X- J8 J
1891248 PCB_LIBRARIAN SYMBOL_EDITOR Copy and mirror arc drawing object in the new Symbol Editor results in wrong arc on opening symbol in DE-HDL
" I- p. _1 ?) \1908381 PDN_ANALYSIS PCB_STATICIRD Allegro PCB PDN Analysis crashes after performing analysis and saving result in release 17.2-2016! B- Y5 n m1 R% \
1825087 PSPICE AA_OPT Graph view menu does not appear when we use 'Curve Fit' in Optimizer.9 u9 N! ~0 z( J6 b( o; J; E9 y. W" N. \
1808091 PSPICE ENVIRONMENT 'orSimSetup' crashes when 'Restart Simulation' is selected
" M$ T: |9 u$ `) D X1811782 PSPICE ENVIRONMENT Setup Simulation Profile no longer enables Advanced Markers when appropriate; C( U" b- A; K* a F! I
1834147 PSPICE ENVIRONMENT PSpice Part Search library icons not displayed if product is installed in the Program Files folder in release 17.2-2016
# f/ X8 f& x U- n1841992 PSPICE FRONTENDPLUGI Getting a blank Error dialog while adding a marker4 @ K+ u* Q" `' z5 ~) _& S$ m
1858574 PSPICE NETLISTER PSpice simulation: Some models cannot be used after upgrading to release 17.2-2016& ~0 K' p7 H9 ?1 M2 H1 C" _
1865022 PSPICE NETLISTER The division operator is not recognized by PSpice in DEV expressions in release 17.2-2016
& ^) F5 z; Q" ]) }# k, S1 S2 d1677119 PSPICE PROBE PSpice crashes when plotting simulation message summary- V& _ i! o+ z% i0 }& E9 P1 k
1837046 PSPICE PROBE On Windows 10, PSpice crashes on clicking Yes to see message
2 j6 v+ \. m# n8 R' A1879387 PSPICE PROBE PSpice crashes when we choose to plot simulation message summary
: ], f4 Q8 Q% p* ~0 ?" }8 _1842231 PSPICE SIMULATOR Wrong results in PSpice Advanced Analysis for DC Sweep Analysis
$ R1 j+ s0 e- H: E u) r1843446 PSPICE SIMULATOR Distribution type is not showing under Assign Tolerance window for transistor/ w8 v" o2 F( P j# k* _
1872630 RF_PCB ROUTING Transition taper length does not work in route- Add RF trace l2 f! y2 ?5 t4 Q' J @
1872636 RF_PCB ROUTING Inherit Width parameter in Route -RF trace only uses width of one side6 w% W, p! @* V& B( w6 |; t
1872644 RF_PCB ROUTING Regression RF trace: change in trace width not retained while routing# L. h8 `! j$ s4 A: {+ `
1901201 SIP_LAYOUT EXTRACT extracta is not retaining custom layer names1 o7 w* ~6 S3 {& V7 {3 c
1813380 SIP_LAYOUT OTHER Layer Compare is not adding the required shapes
, A: G+ A) @4 u, Y, G8 I1852762 SIP_LAYOUT OTHER Error generated in Package Design Integrity Check when adding soldermask to my design) v# p% ^5 k Z
1886847 SIP_LAYOUT REPORTS Incorrect metal area in metal usage report; c( V' V- ~- t5 S3 K' Y: Q( f6 x
1491315 SIP_LAYOUT SHAPE Dynamic shape filling exceeds the shape boundary on running 'create bounding shape' command
& ~, J1 m. L* a1853989 SIP_LAYOUT SHAPE 'Shape - Select' and then' Move' from pop-up with ix 500 iy 0 moves shape diagonally$ J# A! Z" K/ ?& I$ J) I5 F
1868509 SPECCTRA PARSER Autorouter takes long time to invoke& `" |" | }! B/ {* M$ S1 y8 W% }% |
1869317 SYSTEMSI ENG_PBA SystemSI PBA does not align correlation waveforms correctly on Linux platform
) W6 |! s; @) j) u, V0 q s7 Q5 Y7 U/ ?' ^* `6 g
( h) q; E1 E/ E
Fixed CCRs: SPB 17.2 HF0376 L0 m5 C' q2 H3 f7 b) w
03-30-2018
/ y' H) p; S2 Q* n========================================================================================================================================================
: u, A0 d& ^0 w7 tCCRID Product ProductLevel2 Title; U- f: \) E$ L8 c5 z4 X' n: K
========================================================================================================================================================0 H% w2 b: ?. S4 K; t8 ?, Z5 @8 {1 b( U
1886573 ALLEGRO_EDITOR IN_DESIGN_ANA Fail to launch Sigrity executable from release 17.2-2016
1 x$ F. U# _$ s5 H- n! J( k, D1891113 ALLEGRO_EDITOR NC Clubbing total backdrill layerwise data
' u# g' l! a0 Q# u2 _# z: d1886085 ALLEGRO_EDITOR SHAPE Line to Thru Via DRC is not displayed automatically
% G. \: H }- b8 X9 c6 b1850888 ALLEGRO_PROD_TOOLB CORE Design Compare crashes immediately after execution
3 @. K# A0 z8 Q1639079 ALTM_TRANSLATOR CAPTURE Title block issues with third-party design+ f" |- x7 j! C
1722577 ALTM_TRANSLATOR CAPTURE Third-party translator does not work in Capture in release 17.2-2016 if CDSROOT is not defined
% w6 k; E: ]: D- _' R! n) N1744697 ALTM_TRANSLATOR CAPTURE Third-party translator crashes/ y) y! l) \: _8 V7 W2 z2 N
1820160 ALTM_TRANSLATOR CAPTURE Title block does not show ghost image when selecting it for placement
! _' q6 {9 x1 G' S3 k1628560 ALTM_TRANSLATOR PCB_EDITOR Third-party translation to PCB Editor not working properly
9 B% s. @' }2 X; g2 y$ B2 L$ S1836750 ALTM_TRANSLATOR PCB_EDITOR Third-party translator fails to translate a complete design
; \% M# j! j9 s. ?; l a1844423 ALTM_TRANSLATOR PCB_EDITOR Third-party translation takes a long time in release 17.2-2016
5 w: g; d, ^/ |1849338 ALTM_TRANSLATOR PCB_EDITOR Third-party translated board not correct& w! Z% s3 X/ r( b! R
1894607 CONCEPT_HDL CORE Closing CM during 'Save Hierarchy' crashes DE-HDL& u! S$ X- k5 R0 m2 A- Z' m7 \% g
1703351 CONSTRAINT_MGR CONCEPT_HDL SigXplorer shows invalid models instead of default models in extracted topology8 q2 h& `7 T! B1 ^" S6 w
1868687 CONSTRAINT_MGR CONCEPT_HDL DML-independent flow: some pin-pairs missing for Differential Pair XNets when migrating 16.6 design to 17.2# d; n, d/ J: Q4 c% a
1868747 CONSTRAINT_MGR CONCEPT_HDL Additional pin-pairs created on migrating design to release 17.2-2016 DML-Independent flow5 n* w$ Y7 k0 \- \
1887794 CONSTRAINT_MGR OTHER Ability to disable cross-section changes in F2B flow
% o- w# J. D1 F$ j4 x! R1859193 MODEL_EDITOR TRANSLATION DML provided by Model Integrity has a parsing error: curve must start at time zero+ B0 g8 _) G+ i: W
4 a0 H$ [+ e/ s1 Q! f" N5 X+ S* F! @7 q( ]
Fixed CCRs: SPB 17.2 HF036
0 d0 {# d/ o i+ c9 ?03-16-2018# X" t' n( T% N! g6 ]/ P
========================================================================================================================================================! v6 Z/ A7 l+ a& }9 w7 O
CCRID Product ProductLevel2 Title
: h4 D# p m; `6 r- P. U========================================================================================================================================================
% U# G7 {; m4 }6 n0 m1880209 ADW DBEDITOR DBEditor quick search is resetting the check boxes in the Attributes tab; X% S+ u3 |1 q9 g9 Q& S% d
1880376 ADW DBEDITOR Allegro EDM Database Editor wildcard search functionality broken after installing hotfix 034.
+ k9 T2 g/ K9 i/ G1855444 ALLEGRO_EDITOR DATABASE PCB Editor crashes on creating MDD files after deleting subclasses
6 w0 H$ Y, u' t; h+ i6 V! @7 j Z1863478 ALLEGRO_EDITOR DATABASE PCB Editor crashes on a specific machine when loading any .mdd file
6 s* o/ T7 u/ T1875544 ALLEGRO_EDITOR SCHEM_FTB Constraints are getting removed
0 g' \, t% {" s; v. H1719683 ALLEGRO_EDITOR UI_GENERAL Incorrect display when using infinite cursor.
0 ^& q I% ~% |1 }% F; @3 v( g1765989 ALLEGRO_EDITOR UI_GENERAL Selection window does not work correctly with infinite cursor option checked
8 i* V7 [1 X2 ]4 k: ]1885667 ALLEGRO_EDITOR UI_GENERAL Infinite cursor is not working correctly- x2 X0 N" c# Q7 y
1873954 ASDA IMPORT_DEHDL_ SDA: Inconsistent pin number positions on part in an imported DE-HDL project
3 o, T3 K' t6 p i: _& y1 d1873883 ASDA NEW_PROJECT SDA: New project from DE-HDL creates blank Page 1* j% {- C6 {% |: N- N. c" F/ q
1852036 ASDA VARIANT_MANAG Design with variant cannot generate a variant BOM. U/ C3 d' ~+ E
1875549 CONCEPT_HDL CORE Incorrect PART_NUMBER/VALUE properties on schematic
- l2 R) n8 y) r x/ L- e2 u1881848 CONCEPT_HDL OTHER License issue: Cannot open Allegro Design Authoring and unable to choose options and features6 ^- q: t* Y7 Q5 w) D* a g a) Z: b
1872189 CONSTRAINT_MGR CONCEPT_HDL Pin-pairs are created for incorrect members of differential pair after ECSet is applied' T: {$ A8 y9 \# }( F3 M
1880235 CONSTRAINT_MGR UI_FORMS Ability to lock auto-generated Constraint Set in UI
; p4 h a1 b/ f% R# f$ r+ `1868711 CONSTRAINT_MGR XNET_DIFFPAIR Nets are dropped from XNets on the BRD file in the front-to-back flow
- H: v! H* {9 c' H! U1879296 ECW PROJECT_MANAG Mode to remove Uprev Lock from locked webs in admin keys
' e8 X6 L2 C, A( N1 z! m& w; O1881632 PSPICE SLPS PSpice creates 'psp_input.log' during co-simulation flow' a1 T$ _2 Z. L5 Z& Z) C# A3 U# O
1879302 SCM OTHER SCM crashes when global nets are changed in the Block Packaging Options dialog box
9 d# y. e' p6 t' w1879580 TDA SHAREPOINT GetData error when opening a project in Design Data Management
4 f# w; O4 K! u* w; l! @2 F& L% e3 a( B5 _# n ]& V' H
9 i5 i9 Z0 D( _% SFixed CCRs: SPB 17.2 HF035# d; q" b$ i1 V( L! C
03-02-20185 a; |* {- h' K. q
========================================================================================================================================================( ]& K" ^4 r; u3 [. I& p
CCRID Product ProductLevel2 Title( @6 O k T( F! `3 ~4 _
========================================================================================================================================================! [4 @8 q" b8 v& j% q6 V- s1 w/ ]; \5 n( A
1873547 ADW ADW_UPREV adw_uprev resulted in incomplete footprint XML( ]4 o k) x: Y. ?
1643895 ADW DBEDITOR Create Footprint model name is not working properly if footprint exists in local flatlib' X+ q% J: a2 x0 c# z4 A* h# \7 k
1846400 ADW DBEDITOR 'Copy As' and 'Rename' STEP model options do not work
& H. A+ k; e" z+ L1868299 ADW FLOW_MGR Copy Project fails and makes Flow Manager unresponsive, h/ U! o) j5 E2 G
1872796 ADW PART_BROWSER Part/Model Details Attributes are all empty when connected to the EDM DB
, v8 l `$ B$ W/ @8 h1877199 ALLEGRO_EDITOR DATABASE Purging backdrill adds bottom filmmask to vias when it is not defined in the padstack
" v, ^. S. k% g. R7 n* `1877219 ALLEGRO_EDITOR DRC_CONSTR PCB Editor crashes on updating DRC
$ ~. s8 O1 z8 R0 N7 n4 e1875528 ALLEGRO_EDITOR GRAPHICS Subclasses disappear in partition! b4 I7 u/ A3 O
1868364 ALLEGRO_EDITOR OTHER Translator for Layout to PCB Editor fails in release 17.2-2016 but works in 16.66 q; O3 H( C. {6 e( [1 F
1822989 ALLEGRO_EDITOR UI_GENERAL PCB Editor very slow when using infinite cursor4 Q u$ ]" G. t) z- G1 ~% r0 w
1855275 ALLEGRO_EDITOR UI_GENERAL PCB Editor becomes slow if OpenGL is disabled
- }1 k' z$ T% B& U- E1868803 ALLEGRO_EDITOR UI_GENERAL Infinite cursor not working as expected4 f7 P; |8 l% p. F, u: U/ E+ L
1869523 ALLEGRO_EDITOR UI_GENERAL PCB Editor hangs inconsistently on axlOpenDesign
( ?6 ~ k% G) C: J1 z( f F" B1871409 ALLEGRO_EDITOR UI_GENERAL ESC key does not function with Enable_command_window_history set
. K' M3 P/ P: U3 V1812306 ALLEGRO_PROD_TOOLB CORE Incorrect DIFF result of PCB Design Compare5 J G9 y0 X- t( s
1872772 ASDA MISCELLANEOUS SDA pulls a license for 'Allegro_performance'6 m* V+ S/ b& g) g2 }* D1 f6 J4 u
1877070 CAPTURE OTHER Capture redraws icons) F( y @ u& T* r$ D
1863624 CONCEPT_HDL CONSTRAINT_MG XNet names are changed in the designs migrated to release 17.2-2016" {% T3 c6 V: W0 J7 X
1866290 CONCEPT_HDL CORE variant editor/DE-DHL crashed when changing a component property
8 S3 T+ J+ ^! n1858139 CONCEPT_HDL OTHER Slow graphic response in Windows10: Icons redraw
6 j: M- Z- l2 T4 @$ }1872703 CONCEPT_HDL OTHER Icon and toolbar in DE-HDL keeps on refreshing for every command
3 d* m8 u* }: ]+ N1 h1873949 CONCEPT_HDL OTHER DE-HDL user interface refreshes frequently; C( e B4 v' K; u8 o" o* T
1871542 CONSTRAINT_MGR INTERACTIV Extracting object with 'Referenced ECSet' does not inherit T-points from the applied ECSet
! d0 l+ v) F- A+ V! t; |1868812 CONSTRAINT_MGR UI_FORMS Cannot Save Log File from CM ECSet Audit.
) E- u# Y/ n }- U( ~ U0 S. K5 C8 i6 O1878574 ECW PROJECT_MANAG Duplicate entries are created in SharePoint users list while creating project on SSO setup+ Y; g$ {! ]9 {% Q2 G
1878619 ECW PROJECT_MANAG Too many mails generated on doing create project
' K6 h! B4 l8 g9 o# |8 H% D1862772 ECW TDO-SHAREPOIN Logical BOM file name not displayed in Changed Files of Pulse Activity Log.; `" c6 J% R9 ]- U# r$ p1 \
1860641 INSTALLATION DOWNLOAD_MGR Download Manager remembers credential settings
+ D g2 v; m: L) o- j1867195 INSTALLATION DOWNLOAD_MGR Download manager crash
5 {3 |! E7 p" w K8 d% o1872187 SIP_LAYOUT DRC_CONSTRAIN Sliding a cline removes DRC markers but updating DRC shows more DRC markers
- ]7 ?7 R( E, I" h: ~& B& J, Z. g- n( W$ i* o& T# g" v- b
+ O+ { z5 \* u, M4 `% qFixed CCRs: SPB 17.2 HF034
2 o/ S; `: e; s1 M3 v! S# f02-11-2018
3 v/ d- P9 a& _ q. Z+ K, [========================================================================================================================================================
- L6 P9 d) Y5 o. U1 @" f w5 I( f7 rCCRID Product ProductLevel2 Title. `2 O6 [& T. i% i
========================================================================================================================================================7 n+ e* [$ F: T# z2 e
1863981 ADW ADW_UPREV adw_uprev is taking a long time after installing hotfix 031' f, Y/ x' r4 r0 o8 [3 ]: K/ `
1868186 ADW DBEDITOR Configured LDAP authentication giving error on launching DBeditor after ISR31 installation+ z) f B# M+ W# m& B
1861524 ADW LIBDISTRIBUTI Library distribution is checking for obsolete classifications every time it is run hence taking more time
( P# L& g& X4 ]: A8 z% x, u1842998 ADW LIB_FLOW Footprint model check-in fails with verification checks failed error, d* Q0 J/ e0 ]1 C4 \
1863047 ALLEGRO_EDITOR DATABASE The layer added above the TOP layer in SiP Layout cannot be deleted from database.
$ k7 u! F& p. z* r7 E/ r0 w6 n1852799 ALLEGRO_EDITOR DFM Refresh symbols crashing inside constraint re-enablement code& z' L( a& q2 e6 A
1865732 ALLEGRO_EDITOR DFM The Thru via hole to Pad check in Annular Ring should check only the Finished hole size instead of backdrill diameter
/ h5 V0 f" G ?1862977 ALLEGRO_EDITOR DRC_CONSTR Differential pair phase tolerance DRCs introduced in release 17.2-2016 DML-independent flow
4 n. S% K# A$ Y1864460 ALLEGRO_EDITOR EXTRACT Running Extracta from outside using command window writes layer name for top/bottom layers incorrectly for SiP designs
5 z1 \) k- Z1 @- g O1859208 ALLEGRO_EDITOR GRAPHICS Pop-up menu remains on desktop when PCB Editor is minimized
# X* c5 l) b4 G' f, G1866422 ALLEGRO_EDITOR MANUFACT Backdrill update taking a long time f- X" T/ a8 X2 c
1867148 ALLEGRO_EDITOR MANUFACT Backdrill update taking longer time to process.
6 K9 E5 R* W- n( u1 n u% q1872127 ALLEGRO_EDITOR MANUFACT Backdrill performance issues - Additional fixes required for S034' N5 Z) b- W. Y. g( }
1866577 ALLEGRO_EDITOR SHAPE Board becomes unresponsive on Shape Update or Slide Trace
2 R6 w$ e% c O e# I# [1867590 ALLEGRO_EDITOR SHAPE The Shape to Pad clearance on multi drill oblong padstacks is not working correctly8 `% o0 }% \0 _7 [8 K
1871902 ALLEGRO_EDITOR SHAPE Void issue during rotation of symbol with multi-drill padstack from hotfix S0324 h. i$ d7 S; N1 e3 W4 u% \
1866778 ALLEGRO_EDITOR UI_GENERAL Unsupported prototype 'Enable_command_window_history' is not allowing text edits using arrow keys9 V) G) g5 l+ _% X- R/ O. V
1865757 ASDA DESIGN_CORRUP SDA hangs when trying to save design or copy page or circuitry( a4 s( F$ i& G9 x
1865872 ASDA DESIGN_CORRUP Corrupt design crashes on editing.
8 i7 z' }" @( J1867039 ASDA DESIGN_CORRUP Design corruption issues
3 l7 }9 a9 v& w8 g9 m& }1831263 CAPTURE OTHER Toolbar refresh is very slow on windows 10 after installing latest windows patch
3 Z3 s5 U, d3 K7 ^1843595 CAPTURE OTHER Icon refresh is very slow on Windows 10 Professional after installing Hotfix 029
5 D5 ]8 a3 A3 R1 ~3 R9 k& L" C/ f; Q9 Y1845003 CAPTURE OTHER Application slow to respond after running for a long time3 q: c- N' d3 ?) R
1847062 CAPTURE OTHER Starting OrCAD Capture redraws the toolbar icons many times.* j- g! E! q; z ^( H' [
1850816 CAPTURE OTHER Capture redraws toolbar very slowly and repeatedly
& Y1 j$ ? z7 m7 S1851346 CAPTURE OTHER Capture CIS redraws toolbars repeatedly
* ]$ K# g8 x2 ~0 U' p1851354 CAPTURE OTHER Capture slows down in Hotfix 30 as tools icons are repeatedly redrawn very slowly3 W7 @% b# y& J
1851883 CAPTURE OTHER Toolbar content refresh is very slow+ h5 D. P3 l* t( b( s. T) N
1852819 CAPTURE OTHER Capture refreshes toolbar again and again; v9 }9 R! M, q, H& j
1853395 CAPTURE OTHER Release 17.2-2016: Capture is refreshing toolbar icons many times at startup with latest hotfix9 ?. V* l: z, S8 L' o8 a; x
1853972 CAPTURE OTHER Capture starts and redraws toolbar very slowly
( k6 x0 j. v, M% \1854735 CAPTURE OTHER Capture toolbar reloads multiple times& |6 j: g: G- }0 f& \
1855850 CAPTURE OTHER Toolbar content refresh is very slow" |5 \3 k' a4 T: R2 k7 u
1857523 CAPTURE OTHER Toolbar icons refresh multiple times and very slowly in release 17.2-2016; `) H9 S2 ^+ O# I' N, k
1859219 CAPTURE OTHER Toolbar is refreshed multiple times while starting Capture CIS
, W* J) v! }) |+ o' p1859626 CAPTURE OTHER OrCAD Capture does not work with the latest Windows 10 update: K, D( O% j7 u/ b8 g! ]1 E
1863341 CAPTURE OTHER Toolbar icon refresh is very slow$ I; g* }7 C0 @1 z7 _
1865661 CAPTURE OTHER Release 17.2-2016, hotfix 032: Capture extremely slow on Windows 10
# C0 J/ f) _1 S0 p1867009 CAPTURE OTHER Slow graphics with Design Entry CIS on Windows 10.; Q9 m! [+ _" k% O$ O8 T# V9 v1 i
1869160 CAPTURE OTHER OrCAD Capture poor performance (toolbar related)9 O9 \! r1 L: E1 f
1869692 CAPTURE OTHER Redrawing of toolbars on Windows 10
( k* X1 i9 h+ L5 @2 B3 m1870310 CAPTURE OTHER Allegro Design Entry CIS redraw issue
2 {9 E5 ^" O( p+ o; Q$ o1870367 CAPTURE OTHER OrCAD Capture Slow Redraw
9 O4 h1 B& h: b, g9 p, L) N1871382 CAPTURE OTHER Schematic will not open and toolbars refreshed repeatedly4 `4 n1 x3 F7 s" l% \9 m
1872427 CAPTURE OTHER OrCAD Capture freeze on Windows 10& r+ X* {2 U! `! y
1862679 CONCEPT_HDL COMP_BROWSER Unable to input property value to search in Part Information Manager% w9 W3 s C/ R7 \% ?
1865039 CONCEPT_HDL CORE 'Save Hierarchy' of a release 16.6 design opened in release 17.2-2016 results in unexpected part changes
2 a6 u. b; E7 S8 d `* x. G+ F0 z1866544 CONCEPT_HDL CORE XNET_PINS added to migrate Design as DML Independentflow does not get saved in the CSA files$ \3 n' t$ e8 i; \' Q* a8 x
1849363 SIG_INTEGRITY SIMULATION Differential impedance calculation shows ZERO when changing dielectric constant
4 v% m/ W: A* ?, g1854195 SIP_LAYOUT UI_GENERAL After setting 'enable_command_window_history' in QIR5/Hotfix 031, Edit - Text no longer functions: Q0 q4 p- K& b' V/ o1 q. g
+ \. _7 b$ K7 y% ~5 P. N/ @6 X$ I; q1 H2 J
Fixed CCRs: SPB 17.2 HF033
6 B: B" r! J: {) R: P01-25-2018/ { }1 ^9 n0 [+ i+ g+ C+ P! e
========================================================================================================================================================; y/ K3 _2 o) V6 q b7 i$ `' W7 u
CCRID Product ProductLevel2 Title
7 |; I6 @# U% P; ?========================================================================================================================================================
9 B; W' C3 H" ?2 c: f1828672 ADW ADWSERVER LDAP connection error while trying to log in to DBeditor" e' |2 x! y' C8 [
1840699 ADW DBEDITOR Unable to release footprint model due to older version being linked to a DE-HDL Block Model
2 p3 R7 g% }: B ]8 l1 V: [1852402 ALLEGRO_EDITOR DATABASE Cutouts are not converted correctly when opening release 16.6 board in release 17.2-2016
" C8 K# o) L9 O( X2 n1855223 ALLEGRO_EDITOR DATABASE Release 16.6. BoardOutline not fully converted to release 17.2-2016 Cutout Layer2 S) g2 R3 t( E' u
1855252 ALLEGRO_EDITOR DATABASE Unable to open a previously saved release 17.2-2016 database
6 i2 `6 n& Q. y. @' k1863025 ALLEGRO_EDITOR DRC_CONSTR Shape voiding to Via pad with backdrill keepout is oversizing the Dynamic shape void by the backdrill keepout, f% ~1 l5 @5 {
1854087 ALLEGRO_EDITOR EDIT_ETCH Sliding arc crashes PCB Editor
- C( r1 d% \! u/ L6 Q& Z+ n6 O, w1840667 ALLEGRO_EDITOR INTERACTIV Choosing 'Change Text block to' from pop-up displays message 'E- (SPMHGE-150): Text font is not defined'
1 d8 }# s# r0 N: t0 X& q1849133 ALLEGRO_EDITOR INTERACTIV On choosing 'Change Text block to' on text , 'Text font is not defined' message appears
D3 @, D8 G0 ^4 ~7 B" u6 O7 a/ h1854695 ALLEGRO_EDITOR MANUFACT PCB Editor crashes while performing nc_route
6 i6 @% P! {: O0 t' B; C _$ q1854634 ALLEGRO_EDITOR NC NC Drill file is generated with half the number of Drill Holes on enabling 'Optimize drill head travel'1 B& h, u, k# [% ]
1856773 ALLEGRO_EDITOR NC Issue with Optimize Drill head travel in hotfix 031: Missing drill holes. q. \" W2 g8 a5 L) [4 Z/ y+ L
1860876 ALLEGRO_EDITOR NC NC route critical difference between hotfix 031 and 022: No slots found warning
% ]4 J! K @4 I' n4 D1758671 ALLEGRO_EDITOR OTHER Export parameters takes long time to export and some times the process hangs! y5 t4 O9 O* `, S9 x
1040989 ALLEGRO_EDITOR SHAPE PCB Editor crashes while editing board outline
- H; c( i: f# s9 E6 g- N9 }1328385 ALLEGRO_EDITOR SHAPE Check for missing thermal reliefs when shapes overlap
( N( B* c3 U! ?1366376 ALLEGRO_EDITOR SHAPE Thermal created for Xhatch shape overlapping another shape, but not created when solid shapes overlap
* M4 Q1 G" [! K8 k& a2 j1716436 ALLEGRO_EDITOR SHAPE Acute angle trim should not violate DRC.
9 r/ p9 @ |- K7 h9 s1822377 ALLEGRO_EDITOR SHAPE Setting shape parameter Acute angle trim control to Full round produces unwanted shape to keepout DRCs, S% P, m& H5 w W
1826436 ALLEGRO_EDITOR SHAPE Same net shape to hole spacing not voiding shape for cline of different net moved close to vias of same net shapes1 v- F6 T' f9 f/ H. I
1834510 ALLEGRO_EDITOR SHAPE Same Net Shape to Via Spacing does not always clear correctly) p. |+ k. R% d8 G& M& w! O
1850716 ALLEGRO_EDITOR SHAPE 'DiffPair combined void for vias added with Return Path option' does not work with fillet and pad suppression
( a+ _0 }: l- q2 ?! O& h: G1852814 ALLEGRO_EDITOR SHAPE Thermal reliefs are not created after placing modules.. ~7 t9 H& i8 m! e, F- R0 J, m
1853453 ALLEGRO_EDITOR SHAPE Route keepout clipping of cross-hatched shapes needs to be corrected& M1 }; S, L/ _3 @: D! d
1859391 ALLEGRO_EDITOR SHAPE Shapes are not using 'minimum aperture for gap width' for voiding after back drill update.8 I' ?- g: {' h# D1 H+ F; s$ i
1859410 ALLEGRO_EDITOR SHAPE Shape to Teardrop is not using same net spacing rules
! R+ K. F2 Z6 P, }5 ]: ~1825397 ALLEGRO_EDITOR UI_FORMS Option panel disappears in release 17.2-2016; i2 q& f( n( a8 _3 J
1854070 ALLEGRO_EDITOR UI_GENERAL enable_command_window_history prevents many aliases and commands from working correctly
: R3 h2 Y8 Y+ t( G1855180 ALLEGRO_EDITOR UI_GENERAL Comma and dot do not work in funckey if 'enable_command_window_history' is set
. E$ H9 s6 R+ D) h) o. M1860003 ALLEGRO_EDITOR UI_GENERAL Icons and features missing or behaving differently in release 17.2-2016, Hotfix 031
) Z' Y& D* s0 K: W' ?1861278 ALLEGRO_EDITOR UI_GENERAL Icons and menus missing in PCB Editor in release 17.2-2016, Hotfix 0313 K) n7 H0 l& k1 W( C" ^$ p) \* U* C
1862292 ALLEGRO_EDITOR UI_GENERAL Layout Pins icon missing in toolbar in Symbol Editor since Hotfix 031& D8 L: j$ y9 }
1793284 ALLEGRO_PROD_TOOLB CORE Limit View (V1R, V2R, COM) for OUTLINE layer.3 g: E8 K" T4 h
1712701 ALTM_TRANSLATOR CAPTURE Third-party translator shows error for missing operand: L! U' X5 m# g1 F% o
1802182 ALTM_TRANSLATOR CAPTURE Imported schematic has connectivity loss. g$ t, w( z1 O% p/ N
1802462 ALTM_TRANSLATOR CAPTURE Hierarchical ports placed incorrectly for imported third-party design z5 Y m& Z2 r- u/ w+ H/ z4 o
1823935 ALTM_TRANSLATOR CAPTURE Translating third-party schematics with hierarchical pages from Design Entry CIS
! t% Q* ]' U+ H7 n- v1830570 ALTM_TRANSLATOR CAPTURE Third-party to Capture translation is translating only one page out of 32
# Z; t6 d" m {/ i1 |1839627 ALTM_TRANSLATOR CAPTURE Third-party translator is not importing complete schematic% _3 q1 h7 N& a% x7 B- a1 |
1846965 ALTM_TRANSLATOR CAPTURE Cannot translate third-party schematic; I& E' ]0 H4 d3 E; `: {
1816767 ALTM_TRANSLATOR DE_HDL Error when translating third-party schematic to DE-HDL
' R7 h! ~- g! g+ w. S/ |1845601 ALTM_TRANSLATOR PCB_EDITOR Cannot operate third-party PCB translation in release 17.2-2016 Allegro Venture PCB Designer license
. O: [% h8 j) E. E6 j4 p9 s: s1841060 APD DIE_GENERATOR Cannot 'die text out' from SiP Layout or Allegro Package Designer6 O: V# U8 F$ q, v% i" A3 v
1793232 APD SHAPE When fillet/taper not connected to a pin, voiding process incorrectly applies shape clearance values1 y L' ~" p2 K- T; _
1846541 APD SHAPE shape degassing does not obey void to shape boundary6 a& R" o7 m1 M9 y ?' B
1863446 ASDA CONSTRAINT_MA A space in the name of a spacing or physical constraint results in the incorrect constraint set name6 {5 N( `, G, j' Q# }7 ~- l3 S
1859678 ASDA VARIANT_MANAG SDA - When hovering over all three buttons, under Preferred Parts in the Variant info it says (Do not install)
6 p- `: W$ ?2 b' A: t/ \1815839 CONCEPT_HDL CORE Allegro Design Entry HDL crashes when entering Location data manually' `2 n" t2 ]6 G; ]4 _
1841857 CONCEPT_HDL CORE Unable to modify Components in non-windows mode: r) ~* e8 d0 {# O
1852096 CONCEPT_HDL CORE Creating a block using top-down approach does not generate the CSB file$ \8 |* X! q0 `8 N
1857390 CONCEPT_HDL CORE DE-HDL crashes on moving symbol
7 e0 r# V0 s) v) F9 x1789070 CONCEPT_HDL OTHER Having folder 'allegro' in cpm root directory gives error while launching layout editor from Project Manager
# _- J3 @: G* ]/ q# T' L: z1862484 CONSTRAINT_MGR CONCEPT_HDL Extracting an ECSet in SigXP is missing a t-point4 D7 V5 E6 a r+ c
1863045 CONSTRAINT_MGR CONCEPT_HDL Pin pairs deleted for a few differential pairs after upreving the design to release 17.2-20164 x. T8 N( x7 h7 F0 |
1863054 CONSTRAINT_MGR CONCEPT_HDL Differential Pairs are treated as invalid objects on upreved design7 [9 d+ A. \ V. ~3 ]6 M' [
1863094 CONSTRAINT_MGR CONCEPT_HDL Pin-Pairs are shown duplicated in the topology for the extracted object (Diff Pair)6 ? h7 I/ P7 A0 [' J
1831998 CONSTRAINT_MGR OTHER 'Tools - Options' settings not saved on closing Constraint Manager
9 Y" Q& Y1 c: c5 w2 t1855324 CONSTRAINT_MGR OTHER Enable the option 'Expand Hierarchy' in 'Find and Replace' dialog, by default" a$ d( i! S$ } ]
1860847 CONSTRAINT_MGR OTHER 'Include Routed interconnect' option once enabled, should remain enabled for that board file1 `4 Y( N. e [7 @$ v% C9 t: C/ o
1843359 EAGLE_TRANSLATOR PCB_EDITOR While importing third-party PCB, many footprints do not convert, even though the log file says footprint created c+ }* m) H& v9 L l1 B5 Y) F
1839978 SCM REPORTS dsreportgen unable to output reference designator from a lower-level hierarchical block if it has a single component
' k2 B4 c1 j7 h6 u. [1850013 SIP_LAYOUT OTHER Environment variable 'icp_disable_cte_auto_update' needs grammatical change
1 E# {( s# g4 i7 M1833742 SIP_LAYOUT PADSTACK_EDIT When creating Die to Die Via using Generate Padstacks, resultant pad stack has wrong Layers
6 A' G6 J8 @ D3 M8 z/ W3 E0 j1619098 SIP_LAYOUT SHAPE Acute angle of shape in design, A7 b0 F# J! Z! \
1728628 SIP_LAYOUT SHAPE Auto-void in dynamic shape does not disappear if object is removed2 r; u8 d% e f* e0 M7 n
1854592 SIP_LAYOUT VIA_STRUCTURE Create via structure returns an error' E1 ?, o4 ^% B( \- `4 { g5 R! }2 c
7 c2 k8 R- E) Y9 S E
% j4 O6 _+ m4 x5 i6 B) C- N! @
Fixed CCRs: SPB 17.2 HF0321 V! i# Q5 I: m
01-13-2018
# W$ P' k3 c8 P- H========================================================================================================================================================7 F! M& S+ N$ K; |8 i% y
CCRID Product ProductLevel2 Title
+ X& h! d7 o# U: k======================================================================================================================================================== E6 ~$ U6 `2 L
1846603 ADW FLOW_MGR Copy project GUI not displaying correct design name after changing the project folder name
- [5 Z0 ?" R; _9 t% U1831152 ALLEGRO_EDITOR 3D_CANVAS New 3D viewer canvas is blank/ P& I% J# l- N9 X& Z
1805870 ALLEGRO_EDITOR COLOR Color file with dot (.) in the filename is not recognized for setting color from the Visibility tab
. {- u# j: v, {5 B( ?1 A1843126 ALLEGRO_EDITOR DATABASE DBDoctor UI is taking very long
7 d+ H' `3 j" k' C' ^5 V1857588 ALLEGRO_EDITOR DFM Design for Fabrication - Aspect Ratio is not taking correct drill hole size* C! w6 P; f; E
1844313 ALLEGRO_EDITOR INTERFACES STEP output viewed in third-party tool has parts sunken into the secondary side
& u: P$ p4 J; X1 ^1801301 ALLEGRO_EDITOR MANUFACT Export IPC 2581 fails if VOLTAGE property is attached to the nets on each side of a RF component. D* N' ~3 A& ~! X' |
1850078 ALLEGRO_EDITOR MANUFACT Choosing 'Manufacture - Artwork' crashes tool; s1 K& M# E: z$ n3 M
1844049 ALLEGRO_EDITOR MODULES Module deletion not removing related component information.: Y7 _. @8 |4 T8 l1 i2 `
1849665 ALLEGRO_EDITOR MULTI_USER Shape rejected by muserver, E# n+ q" g0 {5 q
1782831 ALLEGRO_EDITOR RAVEL_CHECKS RAVEL file does not load when it is located on a network with a UNC path specified
* C! Z2 i8 `; g! d) g- w1 g1830442 ALLEGRO_EDITOR SCHEM_FTB Fail to import technology file with message for failure to read the configuration file& _4 u0 Z5 p+ w/ t' E: z
1837391 ALLEGRO_EDITOR SCHEM_FTB Capture Property cannot rewrite or update constraints in PCB Editor
& P* e, f, Q2 t2 v" K3 C1840643 ALLEGRO_EDITOR SCHEM_FTB Export physical does not work after modifying PCB cross section: N# }- M; D7 [0 t+ ], X6 L; c
1718165 ALLEGRO_EDITOR SHAPE Drill hole cannot be voided by shape
8 T# J# \0 U2 w/ `( k1753245 ALLEGRO_EDITOR SHAPE Update Shape retracts more than the shape to shape spacing- W- V8 i+ h. O' P, _1 R- I
1827366 ALLEGRO_EDITOR SHAPE out of date shape is not flagged as out of date
) ]# V/ b6 _- t( I: ~+ M1828208 ALLEGRO_EDITOR SHAPE Shape remains out of date, but status shows otherwise
( Z/ l3 D4 U4 M: [" d5 W1832098 ALLEGRO_EDITOR SHAPE Skip via shorts to plane at few places even after the necessary keep-outs are assigned to the via pad-stack.
* W( @& E6 T) l1834281 ALLEGRO_EDITOR SHAPE DBDoctor creates a large number of DRCs. p& A7 D$ z6 o' e: _; H4 V
1842121 ALLEGRO_EDITOR SHAPE Unable to clear the Drill Hole to Shape Spacing DRC as Pin is not able void to the shape correctly.; f+ m+ E6 F$ a
1846010 ALLEGRO_EDITOR SHAPE Changing MCAD hole to copper spacing in Analysis Modes - Design does not make shapes out-of-date
6 n4 m! q" q2 W; }/ ?9 x5 L c1839119 ALLEGRO_EDITOR UI_GENERAL On some machines, PCB Editor hangs when launched with a script that uses SKILL to open a design
" _" y. Y' Z8 @5 M- m9 n6 M! g; F5 w1828794 APD SHAPE Setting Shape Fill Xhatch Cells option to HIGH, crashes the application
# {) F& T2 M/ @ h1 W) n1840748 CAPTURE PROJECT_MANAG Capture crashes on opening or creating designs# t' f* p( u1 G5 D
1785298 CONCEPT_HDL CORE Incorrect object access during variant load- C6 Q# _: L0 i9 x# |$ m9 c' ~2 ]
1832119 CONCEPT_HDL CORE Save Hierarchy shows ERROR(SPCOCN-2010) messages but design packages without error1 {/ n2 V( [$ s; U
1833036 CONCEPT_HDL CORE nconcepthdl crashes with a core dump when running an external script
4 Q3 |3 Y, N2 L0 ?1841545 CONCEPT_HDL CORE NO_XNET_CONNECTION properties added to two-pin filters after upreving to release 17.2-2016. C, I8 ?& |1 _2 s, ~
1842289 CONCEPT_HDL CORE Opening a schematic in release 17.2-2016 causes the .dcf file to be overwritten$ o( ^7 p. q, ^9 _& X- J* _' k
1841543 CONCEPT_HDL OTHER DE-HDL crashes when changing a net name/page name/bit bus after installing release 17.2-2016, Hotfix 029. X% t% ]/ T7 K
1843791 CONCEPT_HDL OTHER Table of contents listing does not update for some hierarchy blocks at the top level$ U# Z* ]" z0 j! V: K5 F; ^$ \
1850709 CONCEPT_HDL OTHER DE-HDL crashes on editing text on canvas in release 17.2-2016, Hotfix 030
1 y7 X) a# F1 g3 G3 p1853377 CONCEPT_HDL OTHER DE-HDL crashes on trying to edit bus tap value on Windows 10.# ]2 h/ E1 x. ^% o, l2 S9 @3 m
1857213 CONCEPT_HDL OTHER DE-HDL crashes when changing Power Property" B x4 e5 l8 S+ _/ e% P
1857214 CONCEPT_HDL OTHER In release 17.2-2016, DE-HDL crashes on using 'Change' for a $LOCATION text value on Windows 10' a) K V" S5 z |# E' ]( j
1821982 CONCEPT_HDL PDF Pin number shown in PDF published from DE-HDL
3 h( c! Q4 j6 m- H8 b& r/ y( j% S+ Z1848615 CONCEPT_HDL PDF PDF Publisher shows incorrect pin text values for parts% h; V3 u4 @% y. y
1845996 CONSTRAINT_MGR CONCEPT_HDL Confusing error message regarding 'Auto XNets Off Mode' vs 'DML Enabled'+ P; V: |- r' c5 z0 ]# u
1854190 CONSTRAINT_MGR CONCEPT_HDL 'Audit - Electrical CSets' hangs Constraint Manager after the design is upreved to release 17.2-2016+ V+ w: Q! n: b6 p
1854868 CONSTRAINT_MGR CONCEPT_HDL Match Group getting deleted after upreving the design to 17.2 and removing the signal_models% b' J3 P2 D7 |# z# Y
1854872 CONSTRAINT_MGR CONCEPT_HDL Additional Pin-Pairs getting created on the DiffPair after upreving to 17.2, R0 H, k% X+ C3 _2 M# k( `) r
1822624 CONSTRAINT_MGR ECS_APPLY Cannot copy PCB net schedule from a net to other nets
, K, m# { \; `* p) r1854883 CONSTRAINT_MGR ECS_APPLY Match group showing 0 length for pin pairs in design upreved from release 16.6 to 17.2-2016
0 x. T# J4 m$ P1 N, l- B1855893 CONSTRAINT_MGR OTHER SigXplorer extraction crashes PCB Editor
4 D7 \: R6 I' Y8 h% c0 j* b' |1855917 CONSTRAINT_MGR OTHER SigXplorer extraction does not extract constraints unless the worksheet is opened once in CM
# a, w& L" c' \# x$ E- S1855350 CONSTRAINT_MGR UI_FORMS Constraint Manager significantly slower in release 17.2-2016, Hotfix 031* K6 o$ h8 |( r0 b9 g; W) t# `( s
1855860 EAGLE_TRANSLATOR PCB_EDITOR Cannot invoke a CAD translator in PCB Editor
+ {# o" K: U8 c- V, Q/ R1 W1857745 EAGLE_TRANSLATOR PCB_EDITOR A CAD translator does not invoke in PCB Editor
) f v7 Y3 i5 z* N; y1859005 EAGLE_TRANSLATOR PCB_EDITOR Eagle translator is not invoking at all
: U0 x' W' L B7 _1843091 F2B DESIGNVARI Variant Editor allows mismatched JEDEC_TYPEs in release 17.2-2016
: [; y8 L. w. }& R' D: \% B0 Z5 I. G5 y1719059 FSP DE-HDL_SCHEMA Termination resistors on buses not being drawn efficiently+ X6 C# H# c! c6 _/ X1 ?+ _
1823419 FSP GUI Net Name Template not visible in Change Net Name in Windows 10
# `* ~- O3 F: y1 E, r+ N" l1480035 ORBITIO ALLEGRO_SIP_I Die symbols are mirrored when imported back to SiP Layout
+ ^6 U* _5 @, H& b7 h5 R$ c' m8 T1853331 PCB_LIBRARIAN SETUP CPM file not updated from PCB Librarian setup
" n3 V% Y& J( A$ F0 h1841308 PCB_LIBRARIAN SYMBOL_EDITOR Symbol not updated in Library View
* F! V6 \; z" R1 g1831269 SCM OTHER Blank properties of associated components are being filled with NULL7 s* Q8 J2 H) {# L3 g
1719057 SCM SCHGEN Pins off grid for voltage nets
8 k8 ?0 u9 a7 ^% r' v( C# W4 E1719060 SCM SCHGEN Pull-ups and pull-downs showing upside down in view
+ z; Z, n( W1 T6 }1732687 SCM SCHGEN Schematic generation deletes IO ports; says it's placing them on last page, but never places them) E2 J& \: o2 N" [1 p1 z9 u+ @
1855932 SIG_EXPLORER OTHER For non-DML designs, SigXplorer defaulting to mils when PCB Editor design units and CM constraints are in mm
* \. B( h* M$ ]; i- e9 h0 C5 i1824035 SIP_LAYOUT WLP SiP Layout DRC GUI not reading Tcl blocks in PVS DRC rule deck3 q8 u0 s, q& F+ F* [3 ?1 D
* B- A8 s& H1 q- Z) U
+ ^, r( a3 h4 H" f/ [, pFixed CCRs: SPB 17.2 HF0319 b; U. C& b/ R
12-8-2017+ e/ `( i* T) c5 B6 y" V
========================================================================================================================================================
2 e+ y. V. m6 R8 L" bCCRID Product ProductLevel2 Title
2 E# [% r# }$ ^========================================================================================================================================================' M- k4 \& a. r" A% E
1746108 ADW DBADMIN Adding and then saving a custom rule set in rule manager results in corrupt rules.xml
9 Y- g0 ?( |" Z1609983 ADW DBEDITOR dbeditor should automatically change mechanical kit names to uppercase% X7 W" j$ D- M! I2 h9 i( _
1807139 ADW DBEDITOR Cannot add new properties, though the new properties were shown in dbeditor# T* h- n) E% m5 o3 E* H" I
1807410 ADW LIB_FLOW Checked-in parts not available in database X1 E; ^2 J8 [( @0 S5 B
1797408 ADW TDA TDO crashes without displaying exception during check-in
2 u: F9 z4 [' P, [+ x. j9 @1804500 ALLEGRO_EDITOR 3D_CANVAS Interactive 3D canvas fails to show all placebounds of a .dra1 @, l3 o7 p c" }
1810758 ALLEGRO_EDITOR 3D_CANVAS 3D Viewer represents symbol incorrectly in hotfix 025 but as expected in hotfix 0243 }6 _9 [% n0 j: z, g; b3 G/ P, Z
1795567 ALLEGRO_EDITOR EDIT_ETCH Route menu has same hot key for 'Connect' and 'Convert Fanout'% R2 j' v4 R% h+ W
1796525 ALLEGRO_EDITOR EDIT_ETCH AiPT is not pushing dynamic shape to add bumps to resolve dynamic phase DRC
# J# ^- D5 J: Z, H m( E1818170 ALLEGRO_EDITOR EDIT_ETCH Fanout with Outward Via direction is shorting few pins
8 n1 i. O% _3 j1712658 ALLEGRO_EDITOR INTERACTIV Add connect: Pin remains highlighted even after choosing 'Done'
- n7 D( }/ m1 O& {1727193 ALLEGRO_EDITOR INTERACTIV Logic - Part List truncates device names to 64 characters though database allows longer names0 w1 D: _ L: q, g; Z( K
1775484 ALLEGRO_EDITOR INTERACTIV Choosing Next with persistent snap in Show Measure disables persistent snap
4 d! t: @2 x! Y0 Q1711860 ALLEGRO_EDITOR MULTI_USER Multi-user lock cannot be cancelled
6 ~; G3 ^% E8 G0 I, Z$ j x1812448 ALLEGRO_EDITOR NC Crash when canceling NC Parameters dialog
0 P1 ]( D- Z G6 O; d1792987 ALLEGRO_EDITOR PAD_EDITOR Pad Designer does not recognize flash names longer than 31 characters) H. @5 r! R, n: Z4 V
1810958 ALLEGRO_EDITOR PAD_EDITOR Padstacks with offset holes
9 ]) Z9 h1 {4 }; b; u) f; J5 V787024 ALLEGRO_EDITOR SHAPE Improve dynamic shape voiding in regions% {5 T A6 X5 Y' y& S: y, k/ y
793232 ALLEGRO_EDITOR SHAPE Line to Shape spacing rule outside region affects shape void in region6 e1 f( h' {+ w% _1 v. Y
797245 ALLEGRO_EDITOR SHAPE Line to Shape Spacing with Region not followed! e, Q1 C" s. n# D
865822 ALLEGRO_EDITOR SHAPE The autovoid functionality should use the true line-to-shape spacing value
1 L6 u# n9 j2 t( O/ B912051 ALLEGRO_EDITOR SHAPE Improve dynamic shape voiding in regions& |8 i' G1 a* ?. l2 g3 b7 _& V
965714 ALLEGRO_EDITOR SHAPE Region constraints are not working correctly on dynamic shapes
. v# G3 Z' ]5 ?: s8 I; v3 x5 Q0 X968342 ALLEGRO_EDITOR SHAPE Shape Voiding when crossing constraint region is taking conservative value and not the actual spacing value
, \) U, R* s0 L4 g p1 Y974734 ALLEGRO_EDITOR SHAPE Shape Voiding when crossing constraint region takes conservative value and not actual spacing value2 V3 Z. ~' H1 X
1073908 ALLEGRO_EDITOR SHAPE Allow line to shape spacing in Region
# J9 n, \) L$ X+ T3 e; j# S7 ^1154787 ALLEGRO_EDITOR SHAPE Region constraints not applied correctly to dynamic shapes4 l- h% V9 g# A
1171283 ALLEGRO_EDITOR SHAPE Shape Voiding when crossing constraint region takes conservative value and not actual spacing value, |7 s7 }1 i+ ]. \* x" w5 ^
1181767 ALLEGRO_EDITOR SHAPE Allow override on line to shape spacing in Constraint Region
: `* {3 S" [& O9 X4 ?: H- g( k1183792 ALLEGRO_EDITOR SHAPE Allow override on line to shape spacing in Constraint Region4 V/ H% x5 @, A' _# z
1186210 ALLEGRO_EDITOR SHAPE Line to shape spacing constraint does not follow the Constraint Region value
3 _% I0 l8 s s# i* p5 U1192312 ALLEGRO_EDITOR SHAPE Region constraints are not working correctly.- |0 C7 o8 Z J% M6 J
1387021 ALLEGRO_EDITOR SHAPE Improve dynamic shape voiding in Regions* |7 h0 |/ f; z3 o: p
1447891 ALLEGRO_EDITOR SHAPE Resolved constraint and actual air gap differ
, ~& F1 v+ y. H1465383 ALLEGRO_EDITOR SHAPE Line to shape spacing constraint does not follow the Constraint Region; K6 [# f/ s# u- y ]
1583144 ALLEGRO_EDITOR SHAPE Line to shape spacing inside the constraint region does not follow region rules& y" G: {) d9 X+ n c( D
1591320 ALLEGRO_EDITOR SHAPE Resolve shape to pin constraint in constraint region
' ?) w* k- p5 k/ d* d1627305 ALLEGRO_EDITOR SHAPE Shape Voiding when crossing constraint region takes conservative value and not actual spacing value1 X9 L2 c- n# o: `9 D
1694552 ALLEGRO_EDITOR SHAPE Constraint region not working correctly
- I5 e- V4 p' e' H9 m% J% L, { }+ ~; p* l1764474 ALLEGRO_EDITOR SHAPE Line to Shape Spacing for Region should be used inside region instead of conservative value
- [, v% }' F7 M/ A& D! @$ P1775119 ALLEGRO_EDITOR SHAPE Shape voiding is not following constraint rules for dynamic shapes in a constraint region
9 J- r9 F# j7 h1784916 ALLEGRO_EDITOR SHAPE Shapes are not voiding to other shapes against DRC settings, creating random DRCs.
$ d9 R+ p( V- q" }% |/ r1793179 ALLEGRO_EDITOR SHAPE 'Same net shape to hole spacing' is only detecting the DRC and not voiding the shape
$ M4 s/ [6 P _ Z& l' Y# {1803365 ALLEGRO_EDITOR SHAPE Region shape to shape constraints take precedence when shapes have multiple constraints
4 b% K3 ~& p" S, W/ h. o1800530 ALLEGRO_EDITOR UI_FORMS 3D Anchor menu missing when using new style OrCAD PCB Editor menu
( F7 X: {8 l1 Z1813604 ALLEGRO_EDITOR UI_FORMS 3D Anchor View is not available on OrCAD PCB Editor menu.
' W" J: y Z7 _4 |5 Z1784710 ALLEGRO_EDITOR UI_GENERAL During Place Replicate and saving file with same name, the warning pop-up window does not show on top
3 W( v- ~& e) T1784728 ALLEGRO_EDITOR UI_GENERAL During Place Replicate and saving file with same name, the warning pop-up window does not show on top
4 y p* m; O _# o# }4 N. r5 U1721853 ASDA CANVAS_EDIT Movement of components results in shorts and inconsistent routing
; C, d; T2 Y0 K+ p4 A/ y! L1802120 ASDA CONTEXT_MENUS Ports are selected though filter is set to Components I' s3 u. Q# f8 C4 r: v
1803832 ASDA MISCELLANEOUS Browse and select new libraries without editing cds.lib- E1 c- }) Z/ T
1804643 ASDA TABLE Exception when pasting table data from third-party tool in SDA
: o x1 e: T1 O9 _) @) k1794004 CAPTURE LIBRARY Diode pin numbers different in Capture in release 16.6 and 17.2-2016
8 K* G4 N1 R/ c* Z+ F) ~$ `1735506 CAPTURE OTHER File menu is missing in Capture
4 U# P6 n/ Z% Y0 @- F% |, w1766663 CAPTURE SCHEMATICS Capture crashes during part placement& o- {: t; f. p( X
1762181 CAPTURE SCHEMATIC_EDI Crash on 'Push Occ. Prop into Instance'1 A+ x6 S$ G1 p% B) O$ @0 f
1786762 CAPTURE SCHEMATIC_EDI 'Remove Occurrence Properties' and 'Push Occ. Prop into Instance' corrupt database
: M6 h. u/ g$ {1 O( _1759424 CIS PART_MANAGER Unable to save the link database part from part manager4 X# ~" D& a/ j+ K/ a+ \% f# U4 H
1802670 CONCEPT_HDL CORE Variant commands take 6 to 10 hours to run on a block& |1 o+ ]- }2 q& i
1816798 CONSTRAINT_MGR CONCEPT_HDL CM API ACNS_DESIGN returns the design name in mixed case
: E! c! X+ h% g) G) s7 d1812656 CONSTRAINT_MGR DATABASE Constraint Value specified at the DEFAULT PCSet/SCSet is not shown in bold blue
0 E. a. t- g3 m* Y1635766 CONSTRAINT_MGR UI_FORMS Worksheet views are not changed as per input- |5 z, ]( ]: y; B
1700505 ECW PART_LIST_MAN Shopping Cart Quantity is not read or not displayed in Pulse
9 S, j# u8 |& ]$ M% J/ O: S- g1797371 ECW PROJECT_MANAG Clicking on another project sometimes takes you to the default project instead of the project you click on0 x9 P! d$ Z) p4 n/ }" x8 f
1843526 INSTALLATION TRIAL Trial installer should not check disk space in update licensing mode
0 F! c# T3 J8 z, w6 F1762148 PCB_LIBRARIAN SETUP Part Developer: Text not readable in Setup form
- i. v& a3 ?4 w" D1770760 PCB_LIBRARIAN SYMBOL_EDITOR Symbol Editor does not remember the last size of the window n5 N" T/ U! ?+ {* T% @! r
1773604 PCB_LIBRARIAN SYMBOL_EDITOR Option to switch between the new and legacy Symbol Editors
- C/ H5 F$ K: W1800354 PCB_LIBRARIAN SYMBOL_EDITOR Resistor has too many lines and looks wrong in new symbol editor8 k( \+ g4 ^. c
1813346 PCB_LIBRARIAN SYMBOL_EDITOR Resistor looks different with multiple diagonal lines in new Symbol Editor but looks normal in DE-HDL$ U) J7 B, j; w8 M7 ]9 `
1815279 PCB_LIBRARIAN SYMBOL_EDITOR Unable to change Grid Settings from Lines to Dots K- Z! ?0 F$ x: v
1738603 PSPICE DIG_SIMULATOR Release 17.2-2016 PSpice digital model: Delay defined by PINDLY is not taken into account
# Y: k& }* Z# Q/ p1802905 PSPICE ENCRYPTION Incorrect option shown in PSpiceENC syntax in usage detail
6 h- Y6 B% H. s5 b: u' m$ @' w. Y1765345 PSPICE ENVIRONMENT Custom distributions are not added to the dropdown
# s( O% \8 k) l7 G4 q" f1784856 PSPICE ENVIRONMENT PSpice ignoring directory changes for Save check point in simulation setup session4 z& g9 }" z5 r2 i3 i1 s' _
1817805 PSPICE ENVIRONMENT Incorrect result for PSpice 'Start saving data after'5 M+ r: E( j3 }5 L3 X
1784507 PSPICE FRONTENDPLUGI Spelling of 'Definition' in PSpice Part Search is not correct
$ T) c& f- s- ?0 K$ ?6 C2 ?1801790 PSPICE LIBRARIES SAC model giving errors
) S$ L$ s& T$ _. h1738776 PSPICE SIMULATOR PSpice simulation stops before TSTOP
1 y W3 w) \) f$ H A1795950 PSPICE SIMULATOR Simulation cannot be completed in release 17.2-2016 but is completed in release 16.6 K+ V% U; a' f1 `5 e! d5 j! P
1803407 PSPICE SIMULATOR Getting convergence error on a model4 m# Q# v: j% A% A. R; R" c6 u$ ]
1814759 PSPICE SLPS .INC file is not working with SLPS! l& a# y4 z8 B) B; q
1715859 SIP_LAYOUT ETCH_BACK Etchback mask not overlapping each other; creating floating metal
5 P. r9 ^1 \) _6 J1729523 SIP_LAYOUT INTERACTIVE When creating a bond finger solder mask the results do not match the required settings
0 |1 [6 ]7 b, U4 V! l1800069 SIP_LAYOUT INTERACTIVE Corrupt dra/psm symbol, but the reason is unclear {; e2 v7 C$ h6 p+ z
1756620 SIP_LAYOUT SHAPE Performance issue when moving vias.8 t* ?0 }4 s4 u, J$ L# t
1782928 SIP_LAYOUT SHAPE Shape merging (logical operation) shows error though measuring shows elements are correctly spaced
4 h$ a7 a. X2 j! E: j1816454 SIP_LAYOUT THIEVING Thieving: need thieving as a specific data type in CM to better control the filling pattern
! ` o) i! Q& Z9 R1728026 TDA CORE Check-in should not require all child objects to be checked in specially if they are not checked-out) J f4 B& j1 C9 Y z
1823976 TDA SHAREPOINT Connection to server terminates when joining a project
3 |: V* d% V/ ]$ D; u! m) p4 q0 w& G* c
8 D; |. E% T0 j$ i
Fixed CCRs: SPB 17.2 HF030
# m/ c/ g6 F9 V- R$ V+ }11-17-2017
% v# {4 |1 p% ]& h! |========================================================================================================================================================
x, d% [8 h; lCCRID Product ProductLevel2 Title6 v! h( w+ F' R# E
========================================================================================================================================================. P7 ~4 N" q0 t, K: a% E
1821774 ADW DBEDITOR MPN is tagged Pending Purge after deletion and lib_dist
! s `! |# q3 N+ h1829549 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase DRC marker displayed at the design origin3 B$ H, p- m/ S+ H D& R1 _1 x! M
1690998 ALLEGRO_EDITOR INTERFACES Runtime error when running PDF Publisher
1 \* ^ a& n- L3 U1805203 ALLEGRO_EDITOR INTERFACES Runtime error when exporting smart PDF on a large board with all film layers selected6 |+ X. m6 i/ b5 D, d6 j
1811698 ALLEGRO_EDITOR INTERFACES Runtime error while exporting PDF2 ?$ z/ o! C2 p
1823818 ALLEGRO_EDITOR INTERFACES Cannot map some step models8 Z5 {1 ~( y/ i2 i! @; }0 _
1750654 ALLEGRO_EDITOR MANUFACT Cut marks cannot be generated on cut outline.# g+ l7 ~. J/ Q& ]) q
1828293 ALLEGRO_EDITOR NC Incorrect status returned for backdrill$ c# V9 D; S/ P; C
1825401 ALLEGRO_EDITOR PADS_IN In PADS library translation, pads_lib_in fails to create Placebound_Top as a shape# H- D& T D0 p
1825427 ALLEGRO_EDITOR PADS_IN Symbol drawing files (.dra) created after PADS Library translation are not getting renamed to their decals& |# ~' p* ~$ k
1825460 ALLEGRO_EDITOR PADS_IN Pins are moved from their correct locations during PADS Library Translation
0 f3 q: }! A+ a; ?1831200 ALLEGRO_EDITOR PLOTTING Incorrect PDF output for traces
+ E4 g9 i1 M" f+ u, g1321314 ALLEGRO_EDITOR SHAPE Force update of dynamic shape generates thermal tie that causes net to short k/ I) H S8 ?6 f# d
1647585 ALLEGRO_EDITOR SHAPE Void around holes is not circular but of the shape of the bounding box
. Z- x2 g* }+ S1830676 ALLEGRO_EDITOR SHAPE XHatch Shape not voiding properly5 Y9 Z/ O, r* p L8 J" w9 |0 P+ e
1821286 ALLEGRO_EDITOR SKILL Using axlSetParam to set static shape clearance parameter crashes PCB Editor
; n, n9 I9 I# m2 z' r: ]0 h; @, y1804662 ASDA DARK_THEME Dark Theme: Change color of selected cells in Rename signals dialog so user can see they are selected
" J: a5 i5 s9 o. n5 e! n1817486 ASDA NEW_PROJECT Need to save a project with a new name, 'copyprojectas' does not seem to work
, I& }5 w: a% `0 p7 I/ {' A* V1826023 ASDA NEW_PROJECT SDA requires user to go into project settings window twice to add a library
$ O9 ^' H1 [8 u; ~1 e& c# t1 K1830632 ASDA SCRIPTING SDA crashes when you type 'find -types' in the Tcl command window* S' k- i4 L! K0 ~
1798864 ASDA VARIANT_MANAG Retain default part visibility when substituting preferred part for variant' V& L" x5 }" h; z+ @4 ]
1798865 ASDA VARIANT_MANAG Value attribute of variant is off while printing though on for default and view
% O0 o* ^5 I$ ~1798866 ASDA VARIANT_MANAG Variant Printing: Pin numbers printed though set to off on default part
. M0 l! l5 h( P$ e" N; Y3 `1831836 ASDA VARIANT_MANAG Cannot delete existing variants in design
4 E8 s$ g' x! S. `$ O2 b1821120 CONCEPT_HDL CORE SIGNAL_MODEL attached to a component is not displayed on the canvas in the Attributes form
4 O1 T2 }8 Y, v& h9 z% F5 S) }1824714 CONCEPT_HDL CORE Display issue: Page border disappears when running the command _movetogrid0 U# v$ }4 Q: |* `. d5 V+ z2 P h7 q
1822587 CONCEPT_HDL CREFER CRefer crashes on a hierarchical design using split blocks) G& K8 E0 \1 w5 ^6 ^$ O8 a
1825461 CONSTRAINT_MGR CONCEPT_HDL Uprevving to release 17.2-2016 adds NO_XNET_CONNECTIONS on components having custom models- M, e1 P. a1 P
1825968 CONSTRAINT_MGR DATABASE cmxlGetObjects returns all the aliased nets and the physical net that goes to the netlist
: R v1 ]2 A1 a) y" I" x1819622 CONSTRAINT_MGR XNET_DIFFPAIR Discrete with NO_XNET_CONNECTION removed from topology when extracted with Routed Interconnect
* F4 @3 L7 e; i" e+ W% w1829762 ECW PROJECT_MANAG Pulse log in: Multiple processes triggered, generating many zip file packets and corrupting many of the packets9 x1 U1 f; X& X2 F& }
1810296 F2B BOM BOM includes status column, nothing should ever be forced on a users BOM output% ]4 x! M8 c5 r3 M
1824593 F2B PACKAGERXL PXL crashes and removes the pxl.log file from the Packaged directory9 ~& [; z- C# L/ W
1832005 F2B PACKAGERXL Message stating 'PXL has stopped working' when packaging design! w) _* ]+ S, X
1822912 RF_PCB AUTO_PLACE rf_autoplace fails for RF component containing variable
% {+ O# A y+ P6 V1803731 SIP_LAYOUT DXF_IF DXF export from 'Component Geometry/Pin_Number' subclass not working in release 17.2-2016
4 S/ a! n" B' p+ L- z( x/ U1825478 SIP_LAYOUT SHAPE When running the Shape Islands report it is listing all the Fillets as Islands# {) k1 M# h; k& {7 b# Z. q
$ z) X$ S* H+ q* `% F# p; r0 d. z! O
Fixed CCRs: SPB 17.2 HF029
1 d) H$ m. `5 `; y0 [0 B11-3-2017 U' s' N9 [* f- K0 f
========================================================================================================================================================0 T4 S. k$ _- f
CCRID Product ProductLevel2 Title; Q) `) h$ g" p/ Z4 C
========================================================================================================================================================
3 }1 W8 J* r4 V: i3 p9 t! C1814597 ADW DBEDITOR Associate part classification is very slow in release 17.2-2016 of Allegro EDM. ~. h3 V! m. k1 N9 I0 M2 I
1733482 ADW FLOW_MGR After installing QIR3, Flow Manager prompts with Java Help question
. z" t9 Q* y& E; y3 {- c% a1814789 ADW PART_BROWSER PTF shows data in old component browser but not new component browser
2 E: [% A) i" l0 j6 I1808620 ALLEGRO_EDITOR DFM Missing graphics in new drc browser.' P! k( Y( W/ l, w# \
1814558 ALLEGRO_EDITOR DFM Silkscreen checks do not work if silkscreen is defined as mask in cross section B( g6 Z2 S; `7 C* d5 j4 z: ^/ [
1807996 ALLEGRO_EDITOR EDIT_ETCH Route Clearance View is not using the correct spacing constraint when nets are partially routed in a region, { a# e6 M/ n+ ^/ I* }" h* E
1747929 ALLEGRO_EDITOR INTERFACES Cannot import logo/bmp on a .dra file
+ c& `& p% z# l: B# V5 [6 a2 o1820142 ALLEGRO_EDITOR INTERFACES pdf_out command not supporting UNC paths for the output pdf file
0 X- N) Y) R' V3 p1671865 ALLEGRO_EDITOR MANUFACT Exceeding 20 characters in Artwork Control Form - General Parameters - Prefix displays 'Illegal Character(s)' error
7 `8 L- r: ~) W1710032 ALLEGRO_EDITOR MANUFACT Adding Artwork prefix gives error for illegal characters' [) \4 [9 [. R }' \; F7 T
1714911 ALLEGRO_EDITOR MANUFACT ERROR: 'illegal character(s) present in name or value' while adding prefix in Artwork Control Form
' K( ], \: m( F" f. _, J1813950 ALLEGRO_EDITOR MANUFACT In the drill chart, the titles 'tolerance_drill' and 'tolerance_travel' seem to be reversed
1 q0 }$ H& Q; d2 t1820970 ALLEGRO_EDITOR MANUFACT IDX_EXCLUDE and BOM_IGNORE excluding objects from IDX export
) K3 M* z# u8 F4 d H1822045 ALLEGRO_EDITOR PARTITION Shape fillet becomes static shape and loses fillet attribute after importing partition
* z/ L4 K+ x8 s5 l1776181 ALLEGRO_EDITOR SHAPE Placing via arrays around a differential pair places vias only for one net
6 c1 N! Q2 ^- O9 _$ o+ ^% j, N! G1817283 ALLEGRO_EDITOR SHAPE Allegro PCB Editor Show Measure Air Gap shows a very large number
3 r$ B+ i7 C. t, A9 j1815595 APD DRC_CONSTRAIN Differential pair spacing constraint not propagating to physical cset nets w' L( w" M0 u% v
1785116 APD SHAPE Big size die performance issue
, C0 P/ h, R( E# T' \4 y) M1811134 APD STREAM_IF GDS stream out with 2000 precision has sharp edges along shapes.+ X8 A3 Q) g: P/ h, [5 _6 F4 w
1811882 APD VIA_STRUCTURE High-speed via structure refresh fails, i( a& j; E; x3 V2 j
1814878 ASDA DARK_THEME Part Manager: Difficult to read black text on black background
4 z# i2 ?6 k- ~. L1814889 ASDA DARK_THEME Change 'updating route in progress' message color: a bright orange bar in dark theme is difficult to read
} a3 [5 i6 R: ]% X& Y1817355 ASDA PAGE_MANAGEME Double-clicking a library in project preferences library does not move the library but changes appearance
& ]" w& q- N# I7 i ?1817964 ASDA SHORTCUTS User Preferences shortcut misspelled C# I# p( y4 P8 C
1820247 CONCEPT_HDL CORE DE-HDL crashes while saving a design/ \$ m* c( P6 I
1823187 CONCEPT_HDL CORE DEHDL allows editing of the locked component's refdes using change text editor
+ B$ n! a/ J+ e- V1 s7 |1824052 CONCEPT_HDL CORE Trying to edit on a group containing a LOCK component, deletes the packaging data on the schematic# G* o1 c: L2 v1 `$ e
1813987 CONSTRAINT_MGR OTHER PCB Editor crashes when Constraint Manager is closed$ O D: \/ R* i# v" b. J3 s
1821129 CONSTRAINT_MGR XNET_DIFFPAIR Uprev to release 17.2-2016 adds unwanted NO_XNET_CONNECTION property to discrete symbols
8 @7 D9 c+ Z; W" T1814725 PSPICE PROBE PSpice Measurements crashes PSpice for a digital simulation
4 W0 z. ^6 r6 x- E+ y2 \1808672 SIP_LAYOUT INTERACTIVE create bounding shape command options: 'Min Area' and 'Sync with shape layer'1 Y9 U+ X* @3 Q* u
1817458 SIP_LAYOUT MANUFACTURING Error in DXF conversion after updating SiP Layout from Hotfix 066 to 082 in release 16.6
0 P: W; o# a0 t+ ]/ r1 j" q4 M v* @5 [
( I/ v. z6 N- u! sFixed CCRs: SPB 17.2 HF028
) |: Q. Z- }+ |8 h8 n+ ~6 ~4 [10-14-2017* a# g# b: x* M) i- x* O
========================================================================================================================================================$ P* r8 W% D. u: P/ Y
CCRID Product ProductLevel2 Title' }) m6 t9 O. k" l3 S; I
========================================================================================================================================================: R: w- s5 U+ K
1773530 ADW FLOW_MGR DE-HDL hangs on importing components from another design or copying and pasting components within a design
) Y1 l# H" q4 @$ r" F1790584 ADW FLOW_MGR SKILL code for comparing two PCB Editor .brd files does not work in EDM in release 17.2-2016# r% ]6 z7 i; {1 h
1794116 ADW FLOW_MGR LRM fails to run on project
/ K; V6 _' w Y* W' H% ^1811532 ADW FLOW_MGR The message for missing tools.jar should not appear in adwcopyproject.log; A1 i) N& X1 y q3 y0 o' A! N
1812109 ADW LRM Library revision manager displays errors while re-importing updated sub-blocks, b: ^/ ^2 F! R
1771851 ADW PCBCACHE Problem in packaging upreved imported block7 q% y; P) T% [, H- L p
1814785 ALLEGRO_EDITOR 3D_CANVAS PCB Editor crashes when a bend is created and then viewed in 3D Viewer
- j' q+ _& ?6 K, p4 d( Y1800131 ALLEGRO_EDITOR DATABASE allegro_downrev_library utility fails on Windows 105 d0 h2 I0 G* f9 X0 u
1814607 ALLEGRO_EDITOR DFM DFM check for soldermask does not include Package Geometry/ Soldermask if the soldermask is part of stackup9 V& S# r* h. |
1813996 ALLEGRO_EDITOR EDIT_ETCH Add Connect crashes PCB Editor if clearance view is set to channel$ m7 o" ?" [+ p* d
1810832 ALLEGRO_EDITOR SCHEM_FTB Error while doing Export Physical from DE-HDL to PCB Editor
7 \1 ~0 A, ?* v: g: ?: R1811785 ALLEGRO_EDITOR SCHEM_FTB Import > Logic > Import Directory does not resolve the relative path to the packaged folder
5 h; c) i8 w! N+ t4 N; m1814166 ALLEGRO_EDITOR SCHEM_FTB Error message when exporting design to board using an earlier version of database: }6 B- u) R! N8 n L' L
1817891 ALLEGRO_EDITOR SCHEM_FTB Error message when exporting design to board using an earlier version" z2 s: Y+ e; r1 G0 k
1818954 ALLEGRO_EDITOR SCHEM_FTB Error message when exporting design to board using an earlier version of database
* y- w: |4 J7 g# i- ~1 Y1 r1812808 ALLEGRO_EDITOR SHAPE Artwork is different from PCB board- ?1 O/ m7 m0 I* U. {1 v
1814836 ALLEGRO_EDITOR SKILL Doing zcopy Xhatch pattern crashes PCB Editor in release 17.2-20162 F7 d$ O/ R( N2 U( Q
1772218 ALLEGRO_EDITOR UI_GENERAL PCB Editor stops responding on Show Element$ ~2 J- l& t" O# \7 f0 R/ ^& E) k1 p) g
1778353 ALLEGRO_EDITOR UI_GENERAL Intermittent PCB Editor crashes on loading IDX in release 17.2-2016 Hotfix 0205 {$ u! Q& s2 g: I8 E9 j( D
1818077 ALLEGRO_EDITOR UI_GENERAL axlViewFileCreate disappears behind window or is blank
/ Y6 H( r4 R: @2 N% A1807423 ASDA NEW_PROJECT SDA CPM file has erroneous date4 v3 j- z3 m8 ^# a/ P! `, |
1809597 CONCEPT_HDL CORE Problem auditing SI model in Allegro Design Entry HDL from Hotfix 025 onward, no problem in Hotfix 024
7 W; E4 {. a/ z5 D1810322 CONCEPT_HDL CORE Unable to package design if OK_NET_ONE_PIN property is set3 m( h% a. X- E: N$ W# K
1813436 CONCEPT_HDL CORE Read-only block import issue in same session: displays error message SPCOCD-553$ G) Q* x f6 L+ }! O
1813912 CONCEPT_HDL CORE The response in DE-HDL is sometimes extremely slow
( a1 b7 e9 I0 d9 f }5 z+ Y/ P1812506 CONCEPT_HDL INTERFACE_DES Error messages during packaging followed by a success message though there are errors in design
: G O2 Q+ W T/ O/ D0 g/ X1808677 CONSTRAINT_MGR CONCEPT_HDL Auto-generation of differential pair finds several instances of the same net
$ G5 c0 @. f, x6 H8 H( f: @0 D1808898 CONSTRAINT_MGR CONCEPT_HDL Unable to resolve the ECSet mapping errors if the topology has pin of PINUSE POWER & GROUND
0 _0 N% O- p; Q9 F$ y1810320 CONSTRAINT_MGR CONCEPT_HDL DE-HDL - Constraint Manager: Cannot add group to net class if a net in group is a member of the net class5 x2 L0 H1 O' C _! k
1812459 CONSTRAINT_MGR CONCEPT_HDL Auto-generation of differential pairs has issues) e. [ \- _1 o0 e/ ?
1796234 CONSTRAINT_MGR OTHER PCB Editor crashes on query (ALLOW_ON_ETCH_SUBCLASS) without data type defined
$ c) o8 [" x/ ^: r1811692 CONSTRAINT_MGR OTHER Constraint Manager: Set Topology Constraints - Rel Prop Delay - Pins is empty in release 17.2-2016 Hotfix 026' T5 k+ ], m+ R8 n; X3 {
1816311 CONSTRAINT_MGR XNET_DIFFPAIR Extracting a differential pair into SigXplorer crashes DE-HDL7 h, Y1 \* {) G9 a( }5 B
1807593 ORBITIO ALLEGRO_SIP_I Die symbol shifts when importing die from OrbitIO to SiP Layout* s/ c! L$ F4 I1 {0 w' W
1800763 PSPICE SLPS Error while running co-simulation in MATLAB for PSpice-SLPS demo designs" U T: @+ g, ]) _9 X6 r5 h
5 J. L' B0 P! X8 s6 N0 a' h
1 {6 g. j" |* B! R/ T3 D1 tFixed CCRs: SPB 17.2 HF0270 K2 p3 u8 T$ H. P$ _
09-29-2017
/ |3 @) n2 N0 A$ @3 x$ N, t( C========================================================================================================================================================
# m6 F: a# r+ e7 vCCRID Product ProductLevel2 Title
/ s! [4 s1 S/ O m& Y! {========================================================================================================================================================, C/ I! v9 `; K N$ ~
1795353 ADW FLOW_MGR Tool unable to find project in windows_project.txt! R1 d2 b# b$ L6 E$ h0 n9 U# {; f
1810386 ADW FLOW_MGR Error regarding not finding project in 'windows_project.txt'
% W1 T; e0 b' l$ o4 n1743732 ADW LIBDISTRIBUTI adwserver -install does not give error if it cannot connect to server.! L7 B& I- A" c% t! v
1804378 ALLEGRO_EDITOR 3D_CANVAS Bend area issues in 3D Viewer( Y* l* v3 L, y. J9 F1 Y2 R( w6 v* r
1795312 ALLEGRO_EDITOR DATABASE Cannot unlock symbols as status is changed to View on opening design9 p5 g) Q8 w' x3 A
1803262 ALLEGRO_EDITOR DATABASE Donut pad With DYN_THERMAL_CON set to FULL_CONTACT has connectivity issues" `% n' C3 O1 J1 d# V$ n2 U- S
1802183 ALLEGRO_EDITOR DFM Using mouse wheel to scroll error information in DRC Browser changes font size" P: T0 A* t) B8 E7 K. y# k
1797222 ALLEGRO_EDITOR DRC_CONSTR Updating DRC results in error 'SPMHDB-403'
: Z, I/ e6 i7 z, m1 _$ |9 y6 y1792163 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes on moving components
6 N v* Z: u( ^0 ^$ A1 d ]1806640 ALLEGRO_EDITOR INTERFACES Step Mapping not working in release 17.2-2016 Hotfix 025# X4 b/ T9 }# ?4 k6 o7 x
1807278 ALLEGRO_EDITOR INTERFACES Running 'step_export_product_asm.exe' displays 'vcruntime140.dll' missing error% ^. C' v5 j/ L/ L
1807286 ALLEGRO_EDITOR INTERFACES The facet file (.xml) for the STEP model 'modelname.step' cannot be found.
' M. x Q5 {/ U+ @2 V/ ]. R( w Z- x1808006 ALLEGRO_EDITOR INTERFACES Facet file for step model cannot be found
( V4 g/ h: q* k% J* S1704335 ALLEGRO_EDITOR MANUFACT Documentation Editor shows an error about backdrill while no backdrill was used in the design2 d% b' I5 E2 F3 N
1800115 ALLEGRO_EDITOR MANUFACT IPC2581 Export giving error that backdrill is out of date even though no backdrill is defined in the design
3 t& y y/ a7 d$ b- z4 ^3 \) v* s+ }1799444 ALLEGRO_EDITOR PLACEMENT Via Array - Boundary placement fails with error
8 v: H0 @3 c2 u1725242 ALLEGRO_EDITOR SHAPE 'Same net shape to hole spacing' is only detecting the DRC and not voiding the shape: m4 Q. b0 c% w( q3 V8 V! {
1804129 ALLEGRO_EDITOR SHAPE XHatch Shape not voiding properly
% r' P: c* |- W* G! S1805238 ALLEGRO_EDITOR SHAPE PCB Editor crashes while importing netlist
$ ]' a& Z1 m% U: A b9 w" `3 `/ G9 b1803542 ALLEGRO_EDITOR SKILL Using axlPadstackEdit to change drill size causes via net to change in release 17.2-2016 Hotfix 025- C# e! A% s5 R( p. M
1800774 APD STREAM_IF Only one pad in GDSII when running 'stream out' with the Flatten Geometry option# m1 u* g/ I# z" o* U9 k
1804196 APD STREAM_IF Component is mirrored by X-axis instead of Y-axis on enabling mirror geometry
3 A' ]9 n8 H$ @0 y: P, j/ a8 n8 s1803375 ASDA IMPORT_BLOCK Import HDL Block fails with message regarding Xnet states and DML independence
?6 R! j/ O1 J! z: i1807423 ASDA NEW_PROJECT SDA CPM file has erroneous date
+ A7 v8 g; L* d) H* `* q; c! M# W1789400 CAPTURE SCHEMATIC_EDI Capture schematic opens unannotated pages on search
! y* b1 _# t: R" w2 M1801573 CONCEPT_HDL CONSTRAINT_MG Upreving release 16.6 design to 17.2-2016 adds NO_XNET_CONNECTION to some components. k/ J6 C) j6 d' \4 ~& _9 _
1810586 CONCEPT_HDL CONSTRAINT_MG DE-HDL crashes when transferring XNET properties to similar components in a read-only block9 h3 o" N! k Q
1794169 CONCEPT_HDL CORE _automodel command crashes DE-HDL if PACK_IGNORE is set
' u/ Z* g" f; M V! R1798672 CONCEPT_HDL CORE Dashes in design name creates an extra design folder in worklib after upreving to release 17.2-2016
5 ~4 A9 P8 V; X& x; d6 k3 E3 @1802258 CONCEPT_HDL CORE Locking unlocked components results in a warning (SPCOCN-3403)9 A6 Q" u1 E; _! \+ s
1803019 CONCEPT_HDL CORE DE-HDL crashes on backannotation0 o3 {! l! w6 Z
1803615 CONCEPT_HDL CORE After running 'Mark for Variant', the block cannot be changed to blue
/ R7 c) X3 N" q2 d1804029 CONCEPT_HDL CORE Visibility issues when using the LOCK functionality
5 D6 ^- ?; U! c7 H4 u6 B1806352 CONCEPT_HDL CORE Group Mirror is causing design corruption.* Z) u% a0 K" Z4 A2 g4 ?
1806978 CONCEPT_HDL CORE Cannot mirror a group of objects5 C! A" |( O4 G
1810387 CONCEPT_HDL CORE Mirroring groups causes erratic display and may corrupt database if project is saved
' i0 X' T; X5 F$ }1812811 CONCEPT_HDL CORE Schematic group mirror not working
# o7 s7 C) M3 v( ]! W& ^1810401 CONCEPT_HDL INFRA Add Signal Name: Cannot select suggested net name4 D0 ^4 H: f8 w+ l& s, B6 G& R: s
1787409 CONCEPT_HDL PDF Minus character at the end of netname causes unexpected string concatenation during PDF Publish
) ?4 R- s+ a# ^3 k9 ]! A1800931 CONSTRAINT_MGR OTHER Even after removing NO_XNET_CONNECTION on parallel termination, topology extracted has duplicate capacitors
0 ]6 Q$ N: H- r; a5 s+ b1790106 CONSTRAINT_MGR SCM Cannot find the constraints file (0) in the schematic project
) ~2 j, E+ Y$ [; k1787117 CONSTRAINT_MGR UI_FORMS Creating bundle in Constraint Manager crashes PCB Editor4 P' Q: F; x4 Y* o8 f7 J7 D/ @3 x
1797384 ECW METRICS Pop-up metrics value tool tip is translucent, making values hard/impossible to read
1 l* F K0 R. m( z7 J C+ b1803226 ECW METRICS Pop-up metrics value tool tip is translucent, making values hard/impossible to read1 Q# D: n) V/ B6 Q5 E2 ]0 U; h: o
1664059 ORBITIO ALLEGRO_SIP_I Incorrect connectivity after .brd import0 P! H. D+ x4 Z
1799338 SIP_LAYOUT DRC_CONSTRAIN Multi-threaded DRC fails with internal memory error even after setting shape_cache_size) z, o; M& R2 e! E G8 a
1799499 SIP_LAYOUT DRC_CONSTRAIN Multi-thread DRC fails J) `( }% j3 M
1806585 SIP_LAYOUT DRC_CONSTRAIN Multi-threaded DRC update aborted: internal memory resource depleted: E. z0 R' R# r
1809804 SIP_LAYOUT DRC_CONSTRAIN Error message while updating DRCs in release 17.2-2016 Hotfix 026 regarding shape_cache_size. M5 }2 ]) B7 ~. ]8 S( @8 I
1788770 XTRACTIM ENG Translated bump / ball conductivity is wrong (PowerDC and XtractIM)
" i' @3 q/ K/ `. o
. s% k$ ~, h! b
# [) V% D. u7 p3 r8 C9 bFixed CCRs: SPB 17.2 HF026
; C; i: C2 g1 H" W& G5 D) {09-15-2017( ~0 H @# H+ s: k \- }8 f
========================================================================================================================================================+ u( E: F% }- V1 ]1 b% B% T# C* d: }
CCRID Product ProductLevel2 Title
$ T3 I+ B' l4 Q! ]4 N0 t& J' M========================================================================================================================================================2 J }$ E( Y* x' ^2 l! Z
1765398 ADW DATAEXCHANGE Duplicate MPNs are created when updating MPN classification properties with data exchange) e, T ?/ j9 A9 S
1780147 ADW DBEDITOR 'Associate Footprint from Tree' does not log the information0 H1 l- R# n$ y4 f8 N
1790134 ALLEGRO_EDITOR DATABASE Correct spelling in Layer Function definition) h, [, d/ f+ j: v* k! s, I! M
1792345 ALLEGRO_EDITOR DATABASE Pastemask is added to bottom layer on backdrilled pins
3 I4 d# n4 V' r4 T( K, s0 B1792930 ALLEGRO_EDITOR DATABASE Uprev required for all libraries and padstacks to use release 16.6 DRA in release 17.2-2016
( Y: I# a5 V1 D4 f# g7 a1781203 ALLEGRO_EDITOR DFA DFA Spreadsheet Editor not starting from Windows Start menu3 k* U) b7 a4 x5 D
1797422 ALLEGRO_EDITOR DFA DFA Spreadsheet Editor not starting from Windows Start menu
; ?1 l0 \3 @3 ]& o+ ]1770694 ALLEGRO_EDITOR INTERFACES Incremental IDX does not place unplaced components! |" @7 l( x2 n/ T: E4 j8 t d4 U- b& r
1776791 ALLEGRO_EDITOR INTERFACES STEP file not displayed in PCB Editor for mapping- _# I/ p/ D2 }* z7 K9 B8 a
1783515 ALLEGRO_EDITOR INTERFACES PCB Editor reading step model incorrectly7 Q: x6 B% t8 b2 |3 D. {
1781485 ALLEGRO_EDITOR MANUFACT Setting ipc2581attrpath results in error 'E- ipc2581attrpath: Variable not defined'9 i5 b I4 t1 [7 w* V3 A
1772713 ALLEGRO_EDITOR MULTI_USER Allegro Symphony Server rejects group moves" ?9 j- P" o1 e5 c) x
1789853 ALLEGRO_EDITOR MULTI_USER Symphony Server rejects updates and hangs frequently4 k: e4 G/ k r% y3 @
1725591 ALLEGRO_EDITOR OTHER File - Export PDF crashes on the design attached
# S8 ~5 w! A$ u) }! ]3 ]! r; B1736324 ALLEGRO_EDITOR OTHER Export - PDF fails to export PDF
5 T7 [ `. t4 I% ^1794071 ALLEGRO_EDITOR PLACEMENT The placement of component is very slow and takes around 3 to 5 minutes per component.
6 E7 l2 Y3 ~. {+ _: P/ G6 k$ t1496199 ALLEGRO_EDITOR SHAPE Overlapping route keepouts result in a broken shape.1 G: w( m9 o2 ^6 e
1760146 ALLEGRO_EDITOR SHAPE Void offset in Artwork but not in board for a particular instance only, w; t2 O: \% h( N- x1 Q5 n
1770372 ALLEGRO_EDITOR SHAPE Overlapping shapes merged in artwork shifts void causing a manufacturing short/ l; p! I* ^, w, V9 @- q
1793419 ALLEGRO_EDITOR SHAPE Unexpected shape void in artwork in release 16.6
i- I9 R4 g% u w1796666 ALLEGRO_EDITOR SHAPE DRCs for out-of-date shape while placing single via
5 A/ G, _0 f% _0 n1786386 APD EXPORT_DATA Exported dra and pad files do not have right stackup3 O; O0 ] ~' q, D5 `
1765673 APD SHAPE Shape in Cu1 and Cu3 cannot void correctly& ?+ y5 d& S/ N) y3 V( Q
1782418 APD SHAPE Artwork is showing unnecessary horizontal lines$ R$ V* b6 [5 ]) @# S i! m
1778366 CONCEPT_HDL CHECKPLUS CheckPlus not printing logic design name
/ ] x1 x3 K' \# ?! L- `! G! @/ P0 C1723855 CONCEPT_HDL CORE Cannot use Rename Signal for unnamed wire segment if the wire has a branch to the same instance
- f0 T8 P' ]7 ?" R C$ X5 r1755174 CONCEPT_HDL CORE Unable to create XNETs on the read-only blocks
$ H8 Y0 b @- I6 Q0 S1765533 CONCEPT_HDL CORE Strokes are slow to respond in release 17.2-2016
5 x4 i8 U4 B6 C1780253 CONCEPT_HDL CORE In Windows mode, with copy command still active and symbol on cursor, DE-HDL stops responding on pressing Delete key1 r' S$ \/ @# Q4 ~
1785069 CONCEPT_HDL CORE Warning box for SPCOCN-2251 needs to be resized and the text formatted correctly5 V0 S" N% B3 o4 d' d4 I' E
1786030 CONCEPT_HDL CORE Packager fails in release 16.6 but runs successfully in release 17.2-2016
! B4 y$ M. q* ]1 M2 m9 f1788077 CONCEPT_HDL CORE Creating new window (new tab) in DE-HDL resets view of original window
7 e- X* w4 t2 i; B5 x1788591 CONCEPT_HDL CORE Wrong pin number displayed after running packager
6 v0 M1 U& ]. p* E( R/ N4 r+ u9 z1776774 CONCEPT_HDL CREFER CRefer crashes without error entry in log file
; v- r8 d; C: c, t1 Q6 G% u7 ^1328320 CONCEPT_HDL PDF Cannot select/search sig_name in published PDF, j' [. C$ Q, A* f. Y% e6 M
1787409 CONCEPT_HDL PDF Minus character at the end of netname causes unexpected string concatenation during PDF Publish2 G+ I/ E1 E7 d: l$ @! X5 X
1758122 CONSTRAINT_MGR ANALYSIS Extracted topology for a differential pair is missing a pin-to-pin connection in the top file
. T! `- f& f! [2 W! o- {1786161 CONSTRAINT_MGR CONCEPT_HDL Random crashes in release 17.2-2016 while working on the schematic editor along with Constraint Manager
" _4 l* ~% P% t3 V1788877 CONSTRAINT_MGR DATABASE Constraint Manager API cmxlImportFile looks for sub-string during replace mode and not explicit names" u/ B; U! e8 ~6 y
1800263 CONSTRAINT_MGR OTHER DE-HDL and CM crash when deleting regions
6 }/ r- U' _3 Q. r- V$ y! \) v5 A1792000 CONSTRAINT_MGR UI_FORMS Data type of constraint not shown in GUI2 q$ n3 C. Z4 p0 ]* m3 O7 s6 J
1744828 FSP CAPTURE_SCHEM Button appears during 'Generate OrCAD Schematics'
# {! w' e4 b( M1 J% {- q( R1747568 ORBITIO OTHER Import of .oio file in SiP Layout takes a long time% P* Y% r8 b: V
1765229 PSPICE AA_FLOW Not able to run PSpice MC after setting Assign Tolerance
* z- e/ L9 ^, r2 K- t% z# b1770174 PSPICE MISC Issues with DMI Template Code Generator+ W$ T' v6 X" n$ J
1 o% B. U, \6 M+ v
7 `. t: X/ U$ e# X# ?Fixed CCRs: SPB 17.2 HF0258 Z- o$ N; ?6 R0 Y" d2 S1 q. J0 o
08-25-2017" g2 X2 G1 ?! {" F' o2 S
========================================================================================================================================================! i# y/ m7 B7 d9 x+ Y3 v) A6 i
CCRID Product ProductLevel2 Title
6 S; l! C( i3 e' k: I) f' l" D========================================================================================================================================================! f3 J7 p, t/ n$ s
1258913 ADW ADWSERVER Copy project message: Unable to locate tools.jar
2 i1 J) G7 |& o. E2 D5 h& o, Y1760866 ADW ADWSERVER Metrics dashboard in Allegro EDM Configuration Manager does not show updated SPB 17.2 hotfix" D) o( b' Z' [) r8 f
1055946 ADW ADW_UPREV Set PTF_SUBTYPE SEARCHABLE to false and default value to exclamation mark) W9 R2 }( P3 O5 x% K- |4 S
1508163 ADW COMPONENT_BRO Manufacturers Part tab disappears on clicking anything other than the part number in the left tree
$ u+ e- i; I# ~" U M! Z3 ]0 s5 n: _5 L1774164 ADW COMPONENT_BRO In release 17.2-2016 Hotfix 22, DE-HDL crashes on using Generate View4 P) `( |! C7 Y0 u) K
1345018 ADW DBEDITOR Database Editor does not catch empty mandatory properties if no changes are made to the part
3 o5 N N* D* T% b7 e) \; w1586858 ADW DBEDITOR 'Access Denied' Error while opening Datasheet Model using Launch Viewer in Database Editor
9 D: t& O: S8 x# `2 y, j1754185 ADW DBEDITOR Max Height value in DBEditor is different from PCB Editor# ^- z K/ {6 O3 Q4 y0 b
1719260 ADW FLOW_MGR Configuration error on a fresh install of EDM in release 17.2-2016 Hotfix 014: R9 e5 s& e, w O8 `5 @
1743730 ADW LIBDISTRIBUTI .lis file error in install_model while using MLR.
3 [: p s' }1 d1 a! [1757178 ADW LIBIMPORT back-end libimport failed, crash and existing flashmodel not found9 R7 w) w2 { h+ \
1648609 ADW SRM PCB Editor stops responding when launched with -s option in release 16.6-2015 Hotfix 0788 F' r! \1 p- \ g
1731152 ADW TDA TDO coredumps after a new object has been checked in as minor and deleted.
7 c) E( W) y3 u/ L* E' D1766998 ADW TDA TDO-ASA: Cannot enable the project for team design until a component is added to the new ASA/SCM design0 a: R3 L0 A& `/ J5 N9 q/ s2 a* e
1695240 ALLEGRO_EDITOR 3D_CANVAS Interactive 3D View of a package symbol not showing the correct mapped STEP file attached to the package symbol
; @; U% f0 E0 G4 c/ t \# a- X# b1698148 ALLEGRO_EDITOR 3D_CANVAS Allegro 3D Viewer crashes on Windows 102 M3 L C8 s1 n2 W0 [! e* q
1738655 ALLEGRO_EDITOR 3D_CANVAS Interactive 3D canvas crashes on Windows 10. S4 m$ v* m) O
1750001 ALLEGRO_EDITOR 3D_CANVAS Interactive 3D Canvas crashes on selecting in symbol view4 P5 w: U$ H6 \. w q8 \
1751796 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas shows component placed at wrong layer for Embedded components
* R3 C7 ~/ i" h l" y" B& i1768775 ALLEGRO_EDITOR 3D_CANVAS Allegro 3D canvas closes when Update Symbol is done and cannot be re-invoked
/ i S- Y; H- m V" q) ?% J1695025 ALLEGRO_EDITOR ARTWORK Artwork film show shorts.; O, k) B% L6 {9 z( G/ x
1708674 ALLEGRO_EDITOR COLOR Dehighlight all should disable the check boxes in the color dialog/nets y$ T7 R1 Z. L0 O4 K
1735522 ALLEGRO_EDITOR COLOR In release 17.2-2016, PCB Editor crashes when not being able to write the CVSettings.xml file.% N0 T! d1 c5 m/ Z4 t4 j+ c
1764475 ALLEGRO_EDITOR COLOR Allegro PCB Editor hangs when selecting OK on the Color Dialog form6 K4 t$ M0 m& E0 q P
1718438 ALLEGRO_EDITOR CROSS_SECTION User interface is inconsistent for the Mask Layer Subclass site file editor., g1 u2 A# O/ W7 `/ I8 W5 |8 N
1765387 ALLEGRO_EDITOR CROSS_SECTION Cross Section Editor does not retain or remove layers added/removed from Setup-->Subclasses* C3 a# Z& s; x5 n( q7 B$ T+ }
1714910 ALLEGRO_EDITOR DATABASE PCB Editor crashes with blank allegro.jrl file when a release 16.6 board is opened in release 17.2-2016 Hotfix 013
: l4 J6 C/ q c$ P1 J1769534 ALLEGRO_EDITOR DATABASE DBDoctor unable to delete invalid subclass( N7 |, d* R$ b2 c" F: g. E! }
1775705 ALLEGRO_EDITOR DATABASE Updating stackup in PCB Editor does not change backdrill status to 'Out-of-Date backdrills'
! \- `9 \: k$ @, u' K1778608 ALLEGRO_EDITOR DATABASE Rigid Flex design: Components with pads defined on the TOP and BOTTOM layers are not placed on the correct layer
2 Q% c0 Y" N* d# u K: J1778644 ALLEGRO_EDITOR DATABASE Allegro PCB Editor crashes while trying to place dimensions
) S" N* a/ N/ v/ P4 F7 p5 K1698695 ALLEGRO_EDITOR DRC_CONSTR Line to Mech-Pin DRC not displayed
( V: r: I+ l1 e% ]! X5 F1705214 ALLEGRO_EDITOR DRC_CONSTR Shape to drill DRCs not getting void and 'cns_show' does not report constraint value) w* f0 e! I# { @5 C7 b( U2 [
1722841 ALLEGRO_EDITOR DRC_CONSTR Inconsistent soldermask to soldermask DRCs on vias as compared to board geometry/soldermask
; o: P6 `: E$ K/ v$ I: A1736116 ALLEGRO_EDITOR DRC_CONSTR Shape Voiding and DRC error on layer with no hole or pad definition+ [5 Q5 D& F' S1 u1 M
1744248 ALLEGRO_EDITOR DRC_CONSTR Release 16.6 to 17.2-2016 DML Independent Flow does not resolve differential pair pin pairs Correctly
0 i i( Y2 v8 B! z1776848 ALLEGRO_EDITOR DRC_CONSTR Negative plane island DRC reported in release 17.2-2016 Hotfix 23% V3 P& c, l6 V) T
1730806 ALLEGRO_EDITOR EDIT_ETCH Element 'vias_allowed' is not valid for content model adding high speed via structures
( L, l5 u6 v1 m0 a. G1745332 ALLEGRO_EDITOR EDIT_ETCH In release 17.2-2016, PCB Editor crashes when starting Add ZigZag Pattern" }8 I/ e9 i3 J) ]
1765555 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes during contour routing% C6 U4 R. u8 T
1644401 ALLEGRO_EDITOR INTERACTIV PCB Editor crashes on running the z-copy command3 z& @8 n4 F. u; s! { b
1657621 ALLEGRO_EDITOR INTERACTIV Copy cline and via cause redundant vias% ?; K+ M. E1 Z4 E* D8 R
1688556 ALLEGRO_EDITOR INTERACTIV Limitations with editpad boundary
2 B" F( Z/ q+ g5 Y6 X- T. z1704901 ALLEGRO_EDITOR INTERACTIV Changes cannot be done when 'Design outline' is selected. d9 R) t7 {0 R0 J* ?
1710731 ALLEGRO_EDITOR INTERACTIV The Edit > Change command does not select or change the text on a block9 k" J# N7 h: C
1714855 ALLEGRO_EDITOR INTERACTIV Placing two objects on the Design_Outline subclass causes PCB Editor to crash: F! S3 z& C" }" b A" j" Q F
1725736 ALLEGRO_EDITOR INTERACTIV Edit>Change cannot change silkscreen line to a different class, but works in preselect mode* j1 ^/ A2 }. E5 Y- W* Y
1728004 ALLEGRO_EDITOR INTERACTIV Text cannot be edited if the Design_Outline subclass is in the selection box
0 M# ]7 V2 t3 T5 E" Z' Z1728794 ALLEGRO_EDITOR INTERACTIV The Oops command and the Esc key do not work when moving components in the Temp Group mode" \" \+ o7 t( {- ~# ?
1738070 ALLEGRO_EDITOR INTERACTIV Copying shape after Shape Operations results in error 'E- (SPMHDB-72): Current active shape must be filled first'# G5 Q G. Q; x3 w% A! T8 I
1750696 ALLEGRO_EDITOR INTERACTIV Add notch angle option fails to update if changed while add notch command is active.1 e h* W+ q& H! e3 x8 g& {
1755240 ALLEGRO_EDITOR INTERACTIV Copy via does not work/ s! U, o/ B2 Q3 Y
1777416 ALLEGRO_EDITOR INTERACTIV Running shape operations results in database corruption
^. w( Z2 x0 S4 B' l3 V1715835 ALLEGRO_EDITOR INTERFACES When IDX is imported in PCB Editor, all the shapes are created on package keepout on all subclasses
0 D2 ~# Q- A; D, x. \1744111 ALLEGRO_EDITOR INTERFACES Pads rotating 90 degree when exporting DXF file from Allegro PCB Editor
9 E6 N8 n* D2 @& D1736045 ALLEGRO_EDITOR MENTOR Third-party import crashes PCB Editor with error stating that .SAV file will be created3 @4 e, \5 O) a5 | k6 F
1751914 ALLEGRO_EDITOR MULTI_USER Find Filter options get disabled while creating symbols
6 T6 @1 n9 z3 m1 q3 X5 n4 B- y$ H1770811 ALLEGRO_EDITOR MULTI_USER In release 17.2-2016, axlTriggerSet('exit 'routine) causes a crash while exiting+ h1 S/ q& p3 n0 _' R5 \
1736545 ALLEGRO_EDITOR OTHER Spelling mistake in description of no_dynamic_zoom variable in user preferences Editor8 o# m$ E/ ] f
1761610 ALLEGRO_EDITOR OTHER Dynamic shape is not voiding as expected." v: n3 r) }' T. p+ w
1702535 ALLEGRO_EDITOR PAD_EDITOR After modifying a padstack in Pad_Editor, the Update to Design function fails to update the dra file" C. S, r/ u, C' s. J* k
1713461 ALLEGRO_EDITOR PAD_EDITOR Padstack editor default geometry not working when cell is preselected
; z& y# e, V! r! ]$ V/ H! D1715702 ALLEGRO_EDITOR PAD_EDITOR Donut shape is lost on cutting the pad shape of the donut pad7 G! t2 E7 f/ m) |/ S# d$ z0 P2 o
1720300 ALLEGRO_EDITOR PAD_EDITOR Multi-drill staggered pattern: Different hole placement for first and second rows for releases 16.6 and 17.2-20169 C) `8 p, m! C, y/ l& A
1724896 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor shows flash symbol for regular pad on selecting 'Shape Symbol'8 F7 o. [- u( D' w3 c
1714839 ALLEGRO_EDITOR PLACEMENT Selecting an alternate symbol (alt_symbol) in a group, in the Placement Edit mode, removes the symbol from the group2 {7 o( q. z. ]! D6 E
1781502 ALLEGRO_EDITOR PLACEMENT Quickplace by room crashes Allegro PCB Editor( O+ W/ [: v6 t! m7 J
1699690 ALLEGRO_EDITOR SCHEM_FTB 'view_pcb directive' no longer working as expected
7 G4 s+ ]; t1 `7 x5 |1758796 ALLEGRO_EDITOR SCHEM_FTB PCB Editor launched from Project Manager does not read the relative paths specified in the view_pcb directive2 r, M i% E- R
1761101 ALLEGRO_EDITOR SCHEM_FTB On saving a board after import logic in PCB Editor, the file is saved in the cpm location and not in the physical folder
* R9 f7 M( v: e- e. s1761394 ALLEGRO_EDITOR SCHEM_FTB Working directory for PCB Editor changes after import logic+ y2 T, `; D: ~9 b4 n( _; P# G8 Q
1714922 ALLEGRO_EDITOR SCRIPTS Running script in the non-graphic mode runs the tool graphically: A7 g) h; y! i- ]/ r/ `2 f
1726550 ALLEGRO_EDITOR SHAPE Shape failed to connect to pin2 q2 j7 |7 ?' ~$ d' N2 k8 |. a
1754945 ALLEGRO_EDITOR SHAPE In release 17.2-2016, Delete islands fails to add DYN_DELETED_ISLAND to voids on Windows 10 systems
) y. e/ }( Z" [9 ]1766280 ALLEGRO_EDITOR SHAPE SPMHGE-300 Polygon operation failed because of an internal error) x5 }' j @/ s
1768307 ALLEGRO_EDITOR TECHFILE Properties defined in the technology files are not being imported in a new design
, p0 M! q4 r$ b! `1771584 ALLEGRO_EDITOR TECHFILE The tech file import command does not update user-defined property immediately
9 L, J5 d' o* b9 t ~: f8 ^1730104 ALLEGRO_EDITOR UI_FORMS Change description of Title bar option variables in User Preferences: s& X. r) O( Q% P1 F
1749272 ALLEGRO_EDITOR UI_FORMS etchlen_ignore_pinvia variable needs to be updated) ^ T Z- J+ r/ Y; ^
1649254 ALLEGRO_EDITOR UI_GENERAL Using wildcard to open padstack file generates error SPMHA1-161 in Padstack Editor in release 17.2-2016
9 B6 H) I( H+ n1685985 ALLEGRO_EDITOR UI_GENERAL Funckey not working for Display - Measure* W# \' h3 s+ J+ C$ K0 u+ E+ s% `" c
1687073 ALLEGRO_EDITOR UI_GENERAL Show Measure command shifts focus to Search field in result window after selecting first element
P" v5 Y) N2 ^: [0 u Q2 Y j4 y1699272 ALLEGRO_EDITOR UI_GENERAL File Viewer not displaying HTML files correctly when 'allegro_html_qt' is enabled* }: T r, A) j% N
1711321 ALLEGRO_EDITOR UI_GENERAL Database settings do not change on changing color settings using the SKILL function axlDBDisplayControl()' a5 k6 k. q! b, W7 h( @
1728468 ALLEGRO_EDITOR UI_GENERAL The Show Element window takes the focus away from the PCB Editor window
6 s; j0 Z5 r0 ? J% f1733690 ALLEGRO_EDITOR UI_GENERAL Performance issues in Visibility dialog if called repeatedly in release 17.2-2016, Hotfix 0179 x; `* Q9 V8 I( |& r( U4 s
1734176 ALLEGRO_EDITOR UI_GENERAL Unable to sort padstacks to open in the padstack editor using wildcards- r: ?. u: `$ l0 S4 \, i
1735733 ALLEGRO_EDITOR UI_GENERAL RAVEL checks slower in release 17.2-2016, Hotfix 017
* H' C3 S+ Y7 Z% A7 z) X! L9 p1737545 ALLEGRO_EDITOR UI_GENERAL axlVisibleSet is slower in release 17.2-20167 i1 L& j8 u# r9 `1 M8 P& z$ @
1744655 ALLEGRO_EDITOR UI_GENERAL SKILL code with axlVisibleSet slower in release 17.2-2016 compared to 16.60 @4 N# o3 S9 }- E- n2 a+ R
1759380 ALLEGRO_EDITOR UI_GENERAL axlLayerPriority API changes layer visibility and colors
" |0 {9 V( _: ?7 K8 p' A9 E9 T0 W1775071 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, dialog boxes are not displayed in the right order on using SKILL- k) N k: T7 y, b, E6 x( P" U
1708554 APD GRAPHICS MCM shape lines are almost short and different with DXF and Gerber files4 o. G1 m% e2 W% f. ?
1678824 APD SHAPE Updating dynamic shape fails to void all elements on layer L2.
q9 [; L$ ^: m& k1742335 ASDA COMPONENT_BRO Libraries missing from new Component Browser4 Y5 H' e! c, k( m1 b
1779777 ASDA CONNECTIVITY_ SDA: Net name and physical net name are different+ ^+ o; X: d* {8 r/ r
1721919 ASDA CROSSPROBE Cross-probing a net from the .brd file highlights the entire bus in the schematic
6 O3 p) T4 l' p" M ]! F6 C1714313 ASDA EDIT_OPERATIO Filter does not work correctly in the Change RefDes form) ?0 q. u4 `- h9 n
1730809 ASDA FORMAT_OBJECT Image transparency slider does not update the number in the combo box correctly' S7 }0 M. l8 F5 H
1747397 ASDA GRAPHICS Pop-up DRC descriptions are too small and cannot be read) [' ~$ R) l9 g3 _2 I Z* x
1640061 ASDA HIERARCHY Incorrect message received when invalid characters are specified for subdesign suffix
2 b! J7 M |6 g8 E, u1723535 ASDA MISCELLANEOUS Clicking in the Command window should place the cursor at the last line to avoid editing previously run commands
7 \& B2 ?0 z5 B: e v1699936 ASDA PAGE_MANAGEME Page gaps created while moving pages7 ]7 g5 m. E0 |* M! P
1737180 ASDA VARIANT_MANAG Deleted variants are removed from the variant.lst file but displayed in SDA% Z: h p, m: Z$ R- k. s
1763247 ASDA VARIANT_MANAG Changes in Variant Editor are not reflected on the schematic page.
5 v5 F; N; e0 ?9 S, L' T2 s' d1733971 CAPTURE CONNECTIVITY Auto connect to bus not working in the attached design6 m" b; a1 p, T- s0 g$ l
1236010 CAPTURE DATABASE Capture is very slow in processing designs.4 e* p! U) Q6 A" a0 X5 K0 F
1518560 CAPTURE DATABASE Large schematics are slow to respond2 }, T8 c1 u# y) p0 f
1705592 CAPTURE DATABASE Capture hangs when switching between schematics that contain nested netgroups
. D" v# N- m$ f3 E, W4 e- J) D1770687 CAPTURE GENERAL In release 17.2-2016 Hotfix 021 and 022, selecting Help - Learning PSpice throws Java Script error
]+ v' w8 l* h8 `# F2 ~1692435 CAPTURE HELP Version Info Window is empty
4 w) X8 i Z; W/ K- Z1767374 CAPTURE NETLIST_ALLEG Capture crashes on canceling the netlisting process
$ N: E# V* J$ t; V4 ~1719613 CAPTURE OTHER Moving a wire in OrCAD Capture CIS or Allegro Design Entry CIS results in design crash; @3 o) h" W: F% D( h. \9 y% R$ {: k
1746663 CAPTURE OTHER Capture slows down significantly in release 17.2-2016 Hotfix 017 and 018
% w0 A4 s1 C T3 a' s1709179 CAPTURE PROPERTY_EDIT Unable to delete unwanted properties associated with Ground and VCC nets.
( C# E4 M/ h6 I! L1 K. L; p1714121 CAPTURE SCHEMATIC_EDI Mirroring and moving a symbol resets the position of a newly added pin property
, x {) W8 h& c w1729861 CIS OTHER The 'Refresh Part Types' icon is alternated with 'Refresh Symbols From Libs' icon+ p+ {; J4 @+ g/ T4 y8 F
1333600 CONCEPT_HDL COMP_BROWSER Sort the sections numerically in Part Information Manager0 h+ ]: Z" c( K3 K( U" K8 ~/ N! H* z
1758761 CONCEPT_HDL COMP_BROWSER Incorrect Version showing in Component Browser in 17.2
; F Y& L) o6 @ M5 P, W. X1769591 CONCEPT_HDL COMP_BROWSER Modify Component / Project Information Manager (PIM), parts take longer to load in EDM3 ~: @+ _- i4 u4 w3 j
1479711 CONCEPT_HDL CORE Mirroring symbols causes alignment issues
$ F2 ?* {3 c: x) B% B1696208 CONCEPT_HDL CORE Display issue with the grid visibility after a save hierarchy# Q; I9 Y4 K0 @, M+ ?+ ^. C
1698802 CONCEPT_HDL CORE Pin number overlap with the pin stub when the component is mirrored.
, x/ E! L* E/ D) K1708917 CONCEPT_HDL CORE nconcepthdl crashes on a design with a core dump
6 \4 j' ^2 `6 f. t) N* Q& J1744815 CONCEPT_HDL CORE Deleting a page crashes DE-HDL
7 K4 E# y1 Z7 T; G' q9 @5 l1751863 CONCEPT_HDL CORE 'Move' does not move body but only properties of selected part8 a& q L# D# F
1763556 CONCEPT_HDL CORE Component Alignment and other graphical feature not working in Windows 10- [! p J3 c |4 k' [
1725121 CONSTRAINT_MGR CONCEPT_HDL Audit report of ECSets reflects some gaps in certain columns
% q1 K7 z( w a- X8 K" T1758740 CONSTRAINT_MGR CONCEPT_HDL Extracted topology does not populate the gather control used in the ECSet: ]3 ^7 a2 v* q! E/ g) ?
1759580 CONSTRAINT_MGR CONCEPT_HDL Class to Class assignments are incorrectly displayed in the 'CSet Assignment Matrix'
: y" Y( b2 o8 b6 q; C- U1759590 CONSTRAINT_MGR CONCEPT_HDL Unable to create bookmarks in Constraint Manager) p4 |0 I# O' Q. ?" }
1764597 CONSTRAINT_MGR CONCEPT_HDL Copying constraints from a SKILL-defined CSet copies the automation flag/attribute ('A' in UI), as well.
5 K6 N+ l: _, j* l( P; R1771427 CONSTRAINT_MGR CONCEPT_HDL Decimal units specified in the precision settings are not applied correctly
3 V5 e" u' r* H1700402 CONSTRAINT_MGR DATABASE Parallelism violation DRC not reported until cline is moved
6 q }# s" E) M4 _2 E. \1700370 CONSTRAINT_MGR OTHER Constraint Manager: Expanded nodes collapse on restart; `6 z, x. L5 m1 E$ n& t! v: J5 H
1735636 CONSTRAINT_MGR OTHER Inductors are extracted as resistors in the topology
4 L. o: G7 j4 i& q/ i1776917 CONSTRAINT_MGR OTHER Creating advanced formula causes the tool to crash
* P o* o$ t+ [/ D0 D7 t1762979 CONSTRAINT_MGR TECHFILE Constraint Manager does not retain values after importing tech file6 W) P, [' Q6 B- C7 i4 l
1699275 CONSTRAINT_MGR UI_FORMS Constraint Manager: Dialog boxes opened from the File – Import menu show files and folders in incorrect order
6 q+ B1 p' k' p& M( C1699312 CONSTRAINT_MGR UI_FORMS Typing *.* in the File name field does not display all the files in the Import Constraints dialog box* F! c4 ?; v. Y n, w/ K5 F" a, |$ `3 b
1742134 CONSTRAINT_MGR UI_FORMS Editing a cell from any of the constraint set in Constraint manager is filling other cells that should not be selected
- _) e. ?, \9 e: A- _! K x1 j1755576 CONSTRAINT_MGR UI_FORMS Constraint Manager: Physical CSet filter not working correctly0 R# B/ F; ]' n, f
1775333 ECW DASHBOARD Activity Log is not accessible to ECAD_Integrators if they are not part of the project team I: Z1 n7 r* j7 C3 D$ B1 l
1749220 ECW OTHER Remove 'Role' column from Users web parts& t( X1 H+ V8 @/ c: @& G. n
1716527 ECW TDO-SHAREPOIN Allegro Pulse: Mismatch between metrics with components on schematic and components in layout( ]1 Z h) I$ x9 ]
1724195 FSP SYMBOL_EDITOR Device pins are not correctly aligned after being moved in Schematic Symbol Editor
6 Q/ O1 z, z1 Z7 Q$ |1725479 INSTALLATION DOWNLOAD_MGR Download Manager error prompts user to close downloadmanager.exe
# K p# ]$ U( n) I9 L1738952 PCB_LIBRARIAN SYMBOL_EDITOR Pin table must allow for Copy/Paste of Rows
# S" ?5 I4 e' c1638740 PSPICE FRONTENDPLUGI Set minimum height for the search field in PSpice Part Search
6 E8 P& n( K& }' U7 T& P1699822 PSPICE FRONTENDPLUGI Set minimum height for the search field in PSpice Part Search
# @6 `4 R; S8 g1 c* k1652265 PSPICE MODELING_APPS Cannot place PWL source from PSpice Modeling App. O( F% g9 Y3 ?- O/ a5 i
1685967 PSPICE MODELING_APPS Getting error when trying to place PWL source from PSpice Modeling App
0 C7 n% g, E$ u2 b1716313 PSPICE MODELING_APPS PSpice PWL Sources not working correctly in release 17.2-2016 Hotfix 014/ N5 v6 {9 X2 o/ K, P
1738747 PSPICE MODELING_APPS Inconsistent file type for PWL part in modeling application and source library
/ X5 }8 Q# s7 G% o1762202 PSPICE MODELING_APPS PSpice modelling app Tcl issues
# E8 }! K# J, z) k% Q, r1736605 PSPICE SIMMODELS BSIM4.6 model parameters incorrectly handled by simulator
4 B* Y6 w# |( Z( I1 p9 b1442623 PSPICE SIMULATOR Bias points are nor correct in attached circuit. }, v! a& b0 _0 B D* U
1618815 PSPICE SIMULATOR Bias Point calculation appears incomplete- u' c: W2 E, C5 _" I
1723039 PSPICE SIMULATOR PSpice crashes when curly braces are specified for the ETABLE parts1 [# I9 S" x7 T& z$ m2 t* w( X
1782353 SIG_INTEGRITY SIGWAVE SigWave crashes when opening .sww file in release 17.2-2016 Hotfix 023
: G8 _% D4 D4 g9 U+ d* i0 a& m1745940 SIP_LAYOUT DATABASE Cutting a part of a tapered cline does not remove the connectivity on the dangling cline
! D+ ~# l- ~' _0 W3 d3 o* B1780072 SIP_LAYOUT DIE_ABSTRACT_ Export->Die Abstract File causes a crash
$ m# E9 H% L( V1736396 SIP_LAYOUT SYMB_EDIT_APP 'No such child' error message when deleting pins in symed
/ ~, \; V; H& O$ d9 z% t% K1 I1769728 TDA CORE Default policy file needs to be fixed u" ]1 c+ J C4 Y" f
1735682 XTRACTIM GUI XtractIM translation is incorrect: adds anti-pads
) W+ ^+ y% m$ y: `, s1 {; B ^& h/ N5 Y- l) a
' v/ h! r7 ]- O& sFixed CCRs: SPB 17.2 HF024) [: `" j% k4 S: l
07-28-2017
: |, ], B- b5 ?0 v! `========================================================================================================================================================
) L c4 T' A$ ~; N& c- UCCRID Product ProductLevel2 Title
& |7 a( ]+ G( Q, L3 d) P. M========================================================================================================================================================
9 f' S2 L+ ^: u; V2 X1762143 ADW COMPONENT_BRO Part placed using the 'Add' button does not populate 'PART_NAME' property
: f6 g/ I: J' O0 _, H$ a1765790 ADW PART_BROWSER Fail to extract component part number and footprint information
9 L# M. Z" j/ g) S5 _1757719 ADW TDA TDO and Windchilll Work Group Manager out of sync at times
' v( `2 S# g3 V6 y1760607 ALLEGRO_EDITOR DATABASE Value for number of decimal places changes in Pad Designer in release 17.2-20160 ^/ C8 [# G& b4 F
1775160 ALLEGRO_EDITOR DFA Loading DFA spreadsheet crashes PCB Editor in release 17.2-2016
0 P! g" |* i5 x0 o/ N1765984 ALLEGRO_EDITOR OTHER Cannot view System Info! V& R1 D1 C q/ e- L7 P, z! {
1729350 ALLEGRO_EDITOR REPORTS Net loop is not listed in report
) B7 O- B- m/ z/ J" S1725242 ALLEGRO_EDITOR SHAPE 'Same net shape to hole spacing' is only detecting the DRC and not voiding the shape
2 p1 D# k( g. ^/ Q# f8 P# Q7 g1754402 ALLEGRO_EDITOR SHAPE Illegal arc radius error (SPMHA1-85)
5 I4 a8 H. y& w8 l: i4 J1762888 ALLEGRO_EDITOR SHAPE Border line missing for some crosshatch (xhatch) shape voids
+ l7 a9 e& v" p- i4 W0 s) |1769188 ALLEGRO_EDITOR SHOW_ELEM 'Show Element' with the 'Groups' option used on certain modules crashes PCB Editor
6 e, ~9 t7 Y" x3 @3 x2 S' U2 ]1767690 ALLEGRO_EDITOR TESTPREP PCB Editor crashes when running automatic Testprep+ j$ }. U9 P6 U E. k. O. t
1737337 ALLEGRO_EDITOR UI_FORMS Pinned Show Element window closes when opening new design in release 17.2-2016
' v; b) q7 W1 W& |" h7 m W. i1736642 ALLEGRO_PROD_TOOLB INTEGRATION Cannot change accuracy to 4 for 'Change Width' in Productivity Toolbox9 @( Y2 \' }( w4 X
1685216 ALTM_TRANSLATOR CAPTURE Third-party translator placing symbols off grid
! e2 a* s) j/ ~" ?1738679 ALTM_TRANSLATOR CAPTURE Connectivity loss in imported schematic
- r1 S& d' b) d- T# e" Z) j1738705 ALTM_TRANSLATOR CAPTURE Connectivity loss in imported schematic. I( H( u+ u1 A2 d5 O( b
1748583 ALTM_TRANSLATOR CAPTURE Crash on importing design using third-party translator
; J* r5 W3 s& R/ O1679310 ALTM_TRANSLATOR PCB_EDITOR Third-party translator should fix off-centered connections6 f7 W. T2 R: t5 p0 O3 j
1686845 ALTM_TRANSLATOR PCB_EDITOR Third-party translator does not place parts after successful translation
, y* D' ~& c4 \" ?/ W( M1723141 ALTM_TRANSLATOR PCB_EDITOR Placement outlines are rotated in third-party translator
- I, Q @& w1 g; C8 p& a+ e( [, L$ [1723164 ALTM_TRANSLATOR PCB_EDITOR Third-party translator creates board with missing data: vias, traces, and so on$ p: l3 Q+ U' Z* G$ |) k1 D
1723190 ALTM_TRANSLATOR PCB_EDITOR Third-party translator changes design origin
0 _% J# t; C8 t. k' n0 x1750496 ALTM_TRANSLATOR PCB_EDITOR Third-party board with arc tracks not correctly converted to arc clines
* b \; k% {4 D- U/ Z! W1769624 APD DATABASE Attempted symbol delete crashes APD
8 J- n$ V% b ?" Z5 s3 o0 f1727206 APD SHAPE Merging two shapes results in an incorrect shape
; m1 H6 f9 D5 Z3 b* w1707756 ASDA VARIANT_MANAG Scrolling in Create Variant closes tool8 O+ U& q7 y, t. y6 j& _
1753699 CM RELEASE installDebugger() does not work in release 17.2-2016 as SKILL kit is not installed
* T" G* t* L% v+ [! M0 `( K1741534 CONCEPT_HDL CORE DE-HDL freezes when selecting a net that contains many connections$ W4 Z! O0 l: w7 g, K k
1752687 CONCEPT_HDL CORE The move command changes the connectivity of the schematic/ I' o! t0 X, x8 T# H% T! _: U
1763525 CONCEPT_HDL CORE Genview crashes when generating split symbols
' s+ B2 z2 ^- t& ?3 d3 H1766797 CONCEPT_HDL CORE Schematic not refreshed after using the clear xnet overrides feature
5 m& x1 v+ R# S: _7 X) g. B" I' O1770852 F2B PACKAGERXL ERROR(SPCOPK-1138): A hard location was found on instances of different physical part types
' G0 a5 S) o0 u1 E0 V1754473 FSP DE-HDL_SCHEMA Provide an option to generate symbols with custom attributes9 z7 V) F" G" y1 C" g/ x# f1 {: [" |. {
1748106 FSP OTHER Create protocol from existing protocol error message needs clarity
! V4 X2 K+ j; M/ z1724201 FSP SYMBOL_EDITOR Unable to change 'Pin Direction' in symbol editor$ F2 F( u- {# W" j [+ r
1772429 ORBITIO ALLEGRO_SIP_I Import - OrbitIO: Translator cannot create bundle in PCB Editor
' W1 U0 \4 y+ |) Q: K$ U1725759 SIG_INTEGRITY OTHER PCB shape/plane capacitance
! S( X* I1 c8 t8 X1760924 SIP_LAYOUT DIE_STACK_EDI Package height of die .dra file reset to 110um when placed
9 g( ~4 ~/ W' C- P9 L. V1764385 SIP_LAYOUT MODULES Embedded components are unplaced in created modules (.mdd)
4 y2 H( a: }5 n. p9 `$ } z1733679 SIP_LAYOUT OTHER 'metal density scan' does not use select window
1 C) }; D& }3 S9 x1763707 SIP_LAYOUT OTHER SiP Layout exits with error message in release 17.2-2016 ^+ b& ?- R* x- O; K
1763515 SIP_RF DIEEXPORT Virtuoso writes incorrect width for 45 degree path segments in XDA file
- E. u* k1 G$ I) O" n3 g1772397 TDA DEHDL DE-HDL crashes if license is not available for team design
/ ^2 b i& y9 g( _; M9 F9 l5 I* U L2 [! _. n
' v' z! q7 @7 W2 T
Fixed CCRs: SPB 17.2 HF023
. v6 P0 g! `# z& m5 B( h# P$ X; w07-7-20175 U: k( v7 V6 Z+ |' T
========================================================================================================================================================
7 {. h" ^3 C& F# Y0 Q( [3 k+ TCCRID Product ProductLevel2 Title$ ]6 Q: n& k. Y
========================================================================================================================================================
0 R( o# C8 Y6 l0 b. ]3 y) h1 T1703281 ADW ADW_UPREV Design_init needs to support the -cb command8 ^0 d C( E, @4 b8 F) m, L. t
1762238 ADW COMPONENT_BRO DEHDL crashes without reason9 n* E! O3 K4 E4 X
1759467 ADW DBEDITOR DBEditor does not recognize that 1.10 is a higher version than 1.9
- [0 @8 Z8 [2 y/ J5 v3 \ {2 @ [1731459 ADW FLOW_MGR Cannot open LRM from Flow Manager
+ R7 t/ c# Q: d1731460 ADW FLOW_MGR Cannot open LRM from Flow Manager
" |" `! f' }4 |! y1757443 ADW LIBDISTRIBUTI Blank PHYS_DES_PREFIX in PTF file
8 \( | S q4 U( [( g6 y4 o+ C$ ]1752126 ADW LRM cache not getting updated with std models when moving from 16.6 to 17.2
2 Q% Y/ m5 O+ G. ]! Y5 G1754444 ADW LRM Update Standard library in LRM causes an error, "Cannot proceed with update as don't have permission to delete."
, J6 C9 F0 a# h( }1715861 ADW SRM symbolrevchk.par has incorrect variable name for SRM to ignore the tool version1 `# U9 I/ c9 ]. K. G" }& D0 S" t
1628403 ADW TDO-SHAREPOIN Objects remain checked-out after multiple failed 'check in hierarchy' attempts
6 j1 l9 }' A$ G( L1759250 ALLEGRO_EDITOR DATABASE Flex-rigid placement does not move bottom pads to nearest layer' W5 d) h, b7 a, z: b; x/ s' g5 q
1762782 ALLEGRO_EDITOR DATABASE PCB Editor crashes when creating artwork
& }* Q( T9 G# w3 V& E; }( w1746665 ALLEGRO_EDITOR DFA Cannot scroll in DFA Constraints Dialog if the DFA constraint file is read only8 H% k% h9 r0 d. e8 W% G
1750084 ALLEGRO_EDITOR DFA DFA spreadsheet disappears from the DFA library if hyphen is present in the name* c, W/ i6 c5 Y& V' A& g0 \
1697155 ALLEGRO_EDITOR GRAPHICS Position and size of Show Element and Measurement windows not saved in PCB Editor
0 K* g3 q+ `* s9 d' C1 J1734282 ALLEGRO_EDITOR GRAPHICS Placement of reports and pop-ups not retained in PCB Editor* r0 | X7 z! s. m$ X4 C( u* W
1740863 ALLEGRO_EDITOR GRAPHICS Show Element and Measure windows do not retain position
0 \3 H0 r1 x/ s: p1749687 ALLEGRO_EDITOR GRAPHICS Position and size of Show Element and Measure windows are not saved in PCB Editor in release 17.2-2016. K- T# t& N7 C6 E: o7 v4 r+ c' v7 [
1764124 ALLEGRO_EDITOR SCRIPTS Replaying recorded script file crashes PCB Editor5 {4 l$ V5 F7 b/ B, ?# |+ U: B0 E
1762888 ALLEGRO_EDITOR SHAPE Border line missing for some crosshatch (xhatch) shape voids2 n& S( R, N- a3 g
1763619 ALLEGRO_EDITOR SKILL Incorrect text block name when extracting text parameters using SKILL A; j( l$ f* T- R/ B
1685826 ALLEGRO_EDITOR UI_GENERAL Reports when opened from Status Form disappear behind PCB Editor canvas when clicking on canvas
0 w! q9 b$ Z, u# h# y: `. L1733552 ALLEGRO_EDITOR UI_GENERAL Although F1 is defined as an alias for another command, pressing F1 opens help
) A% N; O+ d1 u) b$ O3 ?2 M2 e* g1735098 ALLEGRO_EDITOR UI_GENERAL axlUIYesNo displays garbled text when customized for Chinese in release 17.2-2016
; ?0 r0 f# a4 C0 K9 G1753430 ALLEGRO_EDITOR UI_GENERAL 'Tools - Quick Reports' opens only one report at a time. V: f! w( f0 L2 H. C' @) ?
1754283 ALLEGRO_EDITOR UI_GENERAL Call multiple reports from a function key7 F5 F0 k, A) E& d
1742822 APD STREAM_IF Component pins are not mirrored properly when mirror geometry option is checked and component is mirrored at 90/2702 t( C2 K% l2 @& Q. O# G0 o# `) I
1762284 ASDA COPY_PASTE Copying testpoint crashes tool and eventually the operating system
/ B( h- w& n. X8 u1655057 CONCEPT_HDL COMP_BROWSER ADW Part Manager and Component Modify hangs6 t F0 U9 j H* e" C
1689740 CONCEPT_HDL COMP_BROWSER Bad response time using Dehdl component browser& @* R' P* ]% n% R5 s: M- j; }
1735332 CONCEPT_HDL COMP_BROWSER Sort in mathematical order Symbol list in Component Browser7 B% G& J+ \0 t2 ?, i- R6 X6 ?
1739197 CONCEPT_HDL COMP_BROWSER Part Information Manager can`t sorted symbol version% `; B* |( c) Q
1764605 CONCEPT_HDL CORE Signal added from the console should be 'Left Aligned' instead of 'Center Aligned'2 o5 w+ ]4 y/ G- U, t2 Y
1761706 CONSTRAINT_MGR CONCEPT_HDL cmDiffUtility has a typo in the usage statement
6 A* b# p7 v6 ?9 s! U; V1758426 ECW DASHBOARD Behavior of 'Apply Label' for Dynamic and Status labels should be same in TDO and DE Webpart( R5 n7 i) p3 o
1764096 ECW PROJECT_MANAG Renaming project using the ETD window randomly hangs the edit window, refreshing bring backs the page+ H c- O H4 R# X
1764070 ECW TDO-SHAREPOIN Join Project: Multiple entries shown for workspace/project with multi-hierarchical structure
- ^ x! R" H! m& C- g* Z0 E4 I; H7 y1754473 FSP DE-HDL_SCHEMA Provide an option to generate symbols with custom attributes9 h5 T! G3 X+ @# h
1724124 FSP DESIGN_EXPLOR Provide Tcl command to filter data in Design Connectivity Window
6 d4 C( A- q2 U: M0 h ?* k1726548 FSP OTHER Unable to open FPGA system planner if username/log file path has Cyrillic letters
- U6 Y5 b- o$ }; B1719133 SCM SCHGEN Voltage symbol not getting placed for some of the voltage nets: [9 e' z6 E: G: H" R8 h5 C4 P
1680989 SIP_LAYOUT ARTWORK Artwork film set-up: Match Display including invisible layer
0 k! F. h" e/ h0 S$ D& q& C% i# R1732218 SIP_LAYOUT DEGASSING Shape will not degas as needed - not all voids degassed
" E9 ?: _1 A ?& {/ m1 c1763280 SIP_LAYOUT DIE_ABSTRACT_ SiP Layout does not recognize width of segment when importing .xda
( o5 B( i* {' S9 }+ D1 `1762992 SIP_LAYOUT OTHER Saving a design after adding a solder mask layer in the cross-section crashes tool7 C# h) {# P' ~. I+ j
" P+ d5 Q! Q/ N+ W. h& \6 C2 ?% u% g C, \6 E: W: W
Fixed CCRs: SPB 17.2 HF022
0 }8 o1 ^1 `( I% |2 t4 g9 J0 Z; |06-16-2017
2 x, m* C e' H% F2 k========================================================================================================================================================- D/ `% x' i! ~* X0 F5 u+ L9 ~$ g3 _
CCRID Product ProductLevel2 Title
9 V: @1 z3 W! O9 \$ D========================================================================================================================================================2 v2 C+ |+ Y, w. i
1755789 ADW DBEDITOR Checking in HSS Block returns 'Failed to create archive'
# @% x' k' V4 r* C7 u1731459 ADW FLOW_MGR Cannot open LRM from Flow Manager
, _, n9 d1 d. ~2 _5 V1731460 ADW FLOW_MGR Cannot open LRM from Flow Manager
% }5 t ]4 m- x; B6 ?" u! ?/ p3 t1744081 ADW FLOW_MGR Error regarding configuration file when trying to open Workflow Manager/ h+ C9 @( J/ Y/ _$ u! k
1756727 ADW LIBIMPORT EDM Library Import fails with java exceptions when merging classifications
Z2 ?7 J* @) G1743763 ADW SRM Find filter is grayed out when Allegro PCB Editor is opened from EDM Flow Manager/ @! t: u8 i. r0 p9 `( [3 _
1748399 ALLEGRO_EDITOR DATABASE In release 17.2-2016, end caps not visible for certain clines in PCB Editor, z" X- ]7 `+ @9 K! ]
1748522 ALLEGRO_EDITOR INTERACTIV A component mirrored using the 'funckey' command jumps to (0,0) position when the 'move' command is used on it# D2 V0 _ a& B' `/ [" _
1734983 ALLEGRO_EDITOR INTERFACES Secondary step model does not stay mapped after drawing is reopened9 H- K( s1 X% Q/ b7 r7 J- O
1753704 ALLEGRO_EDITOR REFRESH Refreshing symbols crashes PCB Editor! Z- |1 {; Q, _: D- J) g6 L9 L
1493721 ALLEGRO_EDITOR SHAPE Voids on negative planes are not adhering to constraints5 V) z y: k& C% |5 n8 [
1711242 ALLEGRO_EDITOR SHAPE Route keep out leads to partly unfilled shapes with gaps
- l2 \- L2 I3 L+ j/ Z1726865 ALLEGRO_EDITOR UI_GENERAL Pop-up Mirror command does not mirror at cursor position
. S3 z0 L* L$ a, h" ~. E3 a( J, O) G1752987 ALLEGRO_EDITOR UI_GENERAL axlUIViewFileCreate zoom to xy location not working while in user created form.! _0 f3 U# H+ X/ l
1755638 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, zoom operations using mouse button not working when axlShellPost() is run
% ?3 K) `4 ?* `1719792 ALLEGRO_PROD_TOOLB CORE Productivity Toolbox Z-DRC hangs or crashes PCB Editor0 p7 q( V' Y8 ?5 c6 Y3 g. j
1624869 ALTM_TRANSLATOR CAPTURE A structure file is required to translate a third-party schematic to OrCAD Capture* p4 r- \8 k2 w# O% m: K( w
1707416 ALTM_TRANSLATOR CAPTURE Missing components and pins in the OrCAD Capture schematic translated from a third-party tool1 P8 m* T1 p7 u! Y4 U3 e
1708825 ALTM_TRANSLATOR CAPTURE The third-party translator fails to translate the schematic
8 I0 _% x+ V0 w; _* F: ~5 f% I1719200 ALTM_TRANSLATOR CAPTURE The third-party translator fails to translate all the pages of a schematic
+ B6 W# ?5 `( r0 O3 ~1546070 ALTM_TRANSLATOR CORE Third-party to DE-HDL schematic translation fails
$ e/ K6 p: n. c1700508 ALTM_TRANSLATOR CORE Third-party PCB translator does not work in release 17.2-2016/ z9 q: v: W% r$ R j$ K2 ]/ V" G
1699340 ALTM_TRANSLATOR DE_HDL Unable to import third-party schematic into DE-HDL using Import menu in PCB Editor$ ^& E. _) ]0 [- @, U# _% W2 `' G
1630379 ALTM_TRANSLATOR PCB_EDITOR Third-party translator is not importing clines and vias6 }. G9 S: o$ O6 u0 b/ Q
1708615 ALTM_TRANSLATOR PCB_EDITOR All items of third-party PCB not imported in release 17.2-2016
* _3 P9 z2 _5 s! w1758296 APD DXF_IF DXF OUT: Rounded rectangle pads mirrored incorrectly4 R" c3 Q8 Q8 V! g; Q$ r
1756040 APD IMPORT_DATA The 'die text in' command ignores values after the decimal point2 x6 d+ j: |( t+ b) G7 W
1727206 APD SHAPE Merging two shapes results in an incorrect shape5 Y) E* N8 a T( K( G- S; n
1753682 CONCEPT_HDL CONSTRAINT_MG Constraint Manager stops responding while cross probing DE-HDL' Z' @( c- k/ ]& E& H8 }5 ]; {) \
1721334 CONCEPT_HDL CORE dsreportgen not able to resolve gated part on schematic
: b: b+ [3 l" ~! W$ X! D1747559 CONCEPT_HDL CORE Copying a logic symbol without a part table entry results in ERROR(SPCODD-53)3 v$ L1 ?) S+ z6 u: G- E% k* F6 k
1749644 CONCEPT_HDL CORE In release 17.2-2016 Hotfix 019, 'align components' is not working on Windows 8 and DE-HDL crashes
) H4 O2 }' j0 D5 N4 m1746910 CONCEPT_HDL GLOBALCHANGE Global Component Change unable to identify part data when using schematic pick option# Y5 t3 z/ m1 R' L. B" t- ^
1743572 FLOWS PROJMGR Project Manager displays incorrect values in Project Setting
' I8 l8 J( y) p1724124 FSP DESIGN_EXPLOR Provide TCL command to filter design connectivity window
3 |& K& P8 Q. C1719105 FSP GUI Tabular sorting not working in FPGA System Planner3 _% {3 K4 a* A. y" s
1755750 PCB_LIBRARIAN GRAPHICAL_EDI In release 17.2-2016, unable to delete _N pins in PDV Symbol Editor
2 \* V; \9 M5 b1722993 PCB_LIBRARIAN IMPORT_CSV Part Developer crashes while importing part information stored in a .csv file9 M3 o0 j/ W* D( j8 B# p3 Q
1758856 SIP_LAYOUT 3D_VIEWER Correct the spelling error in the 3D Viewer Design Configuration window
' T) d) ?7 @: M) E+ |4 \1755179 SIP_LAYOUT ARTWORK PCB Editor crashes when creating Gerber files2 c. I! O% d8 ^5 r$ ]/ `: L |
1743511 SIP_LAYOUT MANUFACTURING Package Design Integrity shows non-redundant padstacks in the Redundant Padstacks check. q( D) [8 [: t! }7 I
7 A1 x' H2 s0 D( J4 j1 i1 o U
4 M7 V: e6 ~* B3 I0 }7 h1 B' j
Fixed CCRs: SPB 17.2 HF021
0 n4 r8 v+ v) `6 D% p0 P06-3-2017
7 J; V$ U; Q. C) a+ h2 S$ W1 P========================================================================================================================================================4 \; G1 A* O. }5 c2 B. |& `9 ]
CCRID Product ProductLevel2 Title
2 W+ s" a' q1 ~5 J========================================================================================================================================================7 m- I& O) j+ B% z: n! v# M! s6 {
1401318 ADW DBEDITOR Bulk Edit - Previously modified cells do not turn blue when selected
1 S: y6 |. e* k3 |6 ]1621446 ADW DBEDITOR Bulk Edit - sorting highlights incorrect cells to mark them as changed
% }6 e6 l! @- K3 S6 ]& J l1743997 ADW LIB_FLOW Match file for standard models is incorrect
3 u- b7 ?5 d" e* o+ }1746052 ALLEGRO_EDITOR DATABASE PCB Editor crashes when applying no drc property
7 ~/ c! P1 K. _& u' L! S% r7 a1736067 ALLEGRO_EDITOR DRC_CONSTR Interlayer checks not reporting DRCs between cline and mask layer* f. A ?7 S( h+ y) o5 P
1738587 ALLEGRO_EDITOR EDIT_ETCH Line width changing on slide for ETCH - Conductor (Not on a NET)
" o) ?5 y4 }4 j8 n4 @0 B$ O; j1745277 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes on using the slide command8 x- N7 e7 h6 `' Y8 k5 t
1747942 ALLEGRO_EDITOR EXTRACT Fabmaster Out does not export arc in pad_shape* U! ]4 D @: w' L" I: c8 Q
1737202 ALLEGRO_EDITOR GRAPHICS Setting the variable display_raster_ops
9 q$ j+ n/ c8 c+ `' Z1744042 ALLEGRO_EDITOR GRAPHICS Unused pad suppression is not working on few nets/ I O; D. H. @" ^* U {$ m
1703848 ALLEGRO_EDITOR INTERFACES IPC 2581 fails with error 'E- (SPMHGE-268)' and the log file is empty: `3 k% K8 z" x9 d; a2 `$ S; }6 R7 a& p
1743899 ALLEGRO_EDITOR MANUFACT Glossing dangling vias crashes PCB Editor
K: g. s: T4 k/ H+ n$ a( \1744467 ALLEGRO_EDITOR OTHER The 'logical_op_new' variable is not displayed in User Preferences Editor# w& c" Z4 K* [$ \- g
1748520 ALLEGRO_EDITOR OTHER TDP fails to load on an empty database
& N8 h3 K& {" B. L& U" ?1748581 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor crashes when changing default pad geometry9 t; q. a3 {$ y4 m/ Z
1751469 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor crashes/freezes when browsing for a shape symbol
$ P( T8 G, [8 Q# b. ~! t1 E9 a! P1725948 ALLEGRO_EDITOR SHAPE Shape differences after conversion from release 16.6 to release 17.2-2016: G, H& W( t+ k! n: ]/ f* ~: |
1729306 ALLEGRO_EDITOR SHAPE Seting shape_rki_autoclip variable causes no void to be generated1 O4 ?( [, b: q
1698876 ALLEGRO_EDITOR UI_GENERAL Tabs are large and text is compressed in release 17.2-20163 r9 {/ v! w; X' r+ ^# u6 l5 n
1698883 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, enlarging icons makes selection boxes/text unreadable on 4K monitors
' Z4 o3 J+ Q; c# K% s. |1707933 ALLEGRO_EDITOR UI_GENERAL axlUIMenuFind not locating menu as per x_location6 @: J( C3 f$ P$ M+ R2 p0 u3 C$ _
1741460 ALLEGRO_EDITOR UI_GENERAL Right-click, context menu options grayed in some cases after choosing Edit - Copy) ^- |# s. I, {
1747588 ALLEGRO_EDITOR UI_GENERAL Interacting with PCB Editor by sending messages is not working o9 e" e. }& O' R
1747488 APD EDIT_ETCH Route connect is improperly affecting existing routes in locked high speed via structures
- `5 V: S4 S! P( f1750182 APD STREAM_IF The stream out settings are not saved% j. q- X& H5 G: t
1752067 ASI_SI GUI Links to differential waveforms do not work in Sigrity SI report
( L. Z/ R6 F# x0 S5 k1752131 CONCEPT_HDL COMP_BROWSER Symbol view in part manager doesn't match the symbol version
$ s2 B$ R. l& K3 v; |1754116 CONCEPT_HDL COMP_BROWSER Default Symbol selected is n°2 instead of n°1 in component Browser) x& H& A+ n6 y) B
1754949 CONCEPT_HDL COMP_BROWSER Part Information Manager displays preview window with the wrong symbol and missing footprint; T# p0 x4 Q1 g" T6 i. D
1721334 CONCEPT_HDL CORE dsreportgen not able to resolve gated part on schematic
5 [. o4 m: C# C/ Q X1750916 CONCEPT_HDL CORE DE-HDL crashes when trying to uprev a project in release 17.2-2016, B+ z H$ p2 \$ P# v# s# u
1711487 CONCEPT_HDL INFRA Restrict opening of release 16.6 designs from a release 17.2-2016 design using File - View Design
q N' T$ w6 l1746915 CONSTRAINT_MGR CONCEPT_HDL Unable to copy a Physical and Spacing CSet generated from the Constraint Automation flow
4 B5 }6 I& l! D" z8 j1743523 CONSTRAINT_MGR DATABASE Suppress warning pop-ups from the constraint automation script
9 t; P& T9 |9 k& W7 U1746941 CONSTRAINT_MGR UI_FORMS 'Go to Source' from DRC tab is not working in release 17.2-20160 o/ b' g5 U3 k- q% |6 w8 D
1753010 ECW METRICS Metrics not getting collected due to old license in use
+ e* z, W- h3 t1 `8 q1713052 FSP GUI Pin/Port Name and Group Name are not aligned properly in FPGA Port and Use Pin Mapping for DeviceInstance/ U0 ^6 I! B' u$ x
1719099 FSP GUI Net naming wrong after building block
4 N9 m/ R8 d$ K! C+ a4 H1719105 FSP GUI Tabular sorting not working in FPGA System Planner/ K* C( b9 a3 ^5 \
1720479 PSPICE ENVIRONMENT Probe window does not open consistently on Windows 10 systems4 y" } c8 t1 R) O; X* m( ]
1723411 PSPICE ENVIRONMENT Probe window does not open consistently on Windows 10 systems. l+ I# `2 }: F+ A+ p4 J" r
1746628 PSPICE ENVIRONMENT PSpice Simulation Manager displays same message for all simulations in release 17.2-2016, Hotfix 016
8 u7 R1 `- T2 ^/ e4 ?* y1745976 SIG_INTEGRITY GEOMETRY_EXTR Arcs with coplanar waveguides are extracted with incorrect spacing
% r/ a/ s& Y$ M$ h1690820 SIP_LAYOUT PLATING_BAR Cannot add fillets to pads with plating bars in release 17.2-2016
2 |& u0 `- b: U# ?1725042 SIP_LAYOUT PLATING_BAR Creating a plating bar removes dynamic fillets" ~3 y% L+ X, }( a* s
1747534 SIP_LAYOUT SHAPE Moving fiducial crashes SiP Layout
& U! w/ `8 [4 ~; }4 Y6 s6 J. P0 N! J @
; o8 I+ w W. K; I7 n, `Fixed CCRs: SPB 17.2 HF020' B+ I0 S, G8 I" ]" }8 c
05-21-2017
) u* p' ~8 O* s. S9 k% V- e8 X========================================================================================================================================================
. |( @( F3 \1 bCCRID Product ProductLevel2 Title5 S! r7 s% ^6 J' @' a; t9 V, @& D
========================================================================================================================================================- z# L6 M8 N# p4 g" ?
1737443 ADW DBEDITOR Revising the schematic model classification for one category causes all parts in the library to be revised
' F& t9 l! d; j1 `1734123 ALLEGRO_EDITOR 3D_CANVAS Interactive 3D canvas crashes Allegro PCB Designer in 17.2 S0163 {8 L' e& b% n9 o& C+ Q
1742084 ALLEGRO_EDITOR DATABASE Running DB Doctor on DRA files with custom pad shapes resets some of the custom padstack shapes in release 17.2
6 F8 O: o# _8 {1739397 ALLEGRO_EDITOR INTERACTIV In release 17.2, running the SKILL function axlImportXmlDBRecords causes Allegro PCB Editor to crash$ k, ]4 Z% l' ?/ W7 N- _, Z
1724588 ALLEGRO_EDITOR MANUFACT Backdrill Route keepout suppressing existing Route Keepouts E) }) R# o$ {( Y$ [
1740036 ALLEGRO_EDITOR MANUFACT Generating the cross-section chart does not provide information about the overall board thickness0 U9 z4 B1 y E$ t8 T3 M2 G
1743726 ALLEGRO_EDITOR OTHER IDF file export: In release 17.2, only one design outline is exported as against multiple board outlines in release 16.6, a: k3 ]9 ~/ |1 N
1744467 ALLEGRO_EDITOR OTHER The 'logical_op_new' variable is not displayed in User Preferences Editor# Q4 }* |# p/ w( t4 F7 d( J
1729350 ALLEGRO_EDITOR REPORTS Net loop report is not working. h# e' I3 n% ` W( i& C' V
1713014 ALLEGRO_EDITOR SHAPE Incorrect behavior of donut shaped pads at certain rotations- e8 o$ d X8 F, L; G& _7 w
1739870 ALLEGRO_EDITOR SHAPE The artwork is different from the PCB in release 17.2 Hotfix 17! v8 f0 {, w' m- N) s2 F; ~" _9 O# W/ ~
1698869 ALLEGRO_EDITOR SKILL PCB Editor crashes when trying to open another .brd file after running SRM on first .brd file
/ v6 L; n' Q$ p8 N2 B) w% M1739307 ALLEGRO_EDITOR SKILL axlCNSDFAExport fails after first run
+ V$ {1 T! O# v; e5 Z8 W' }; N1743385 ALLEGRO_EDITOR SKILL SKILL APIs for STEP model mapping are not available in release 17.2 Hotfix 17 or 18
5 [, b, O6 p3 R8 j5 d( ^5 S1685826 ALLEGRO_EDITOR UI_GENERAL Reports when opened from Status Form disappear behind PCB Editor canvas when clicking on canvas
1 ~ P5 p& |1 @( `3 B8 ^1687797 ALLEGRO_EDITOR UI_GENERAL Cannot open two HTML windows, one after the other, while using SKILL function; M: t# g5 o. X5 E- M3 s
1696229 ALLEGRO_EDITOR UI_GENERAL Setting the 'allegro_html' environment variable in User Preferences Editor overwrites existing popup text windows: X* l: H0 j- j# x7 d) P- R2 s" R
1708636 ALLEGRO_EDITOR UI_GENERAL In SPB 17.2 release, keyboard focus automatically shifts to the newly opened dialog box
/ G. D5 m( T5 M" Z. P1 N( P1711367 ALLEGRO_EDITOR UI_GENERAL Launching two report windows using SKILL is not working in 17.2) g4 }9 j$ I9 k- _; U3 Z7 S; C1 I
1742856 ALLEGRO_EDITOR UI_GENERAL Allegro PCB Editor crashes if Project Manager is open for a design in release 17.2 Hotfix 18
Y" X2 j \2 u1729519 APD SHAPE shape degassing does not generate all voids to cover entire shape+ I6 x% U, R6 e B* V Q
1711375 CONCEPT_HDL CORE Copy-paste of schematic between two instances of DE-HDL is not working as expected
: t3 [; |. {; N* u1737230 CONCEPT_HDL CORE On the Linux platform, copying of schematic objects does not work between designs of releases 16.6 and 17.2
9 d6 r, D* S- ?1741375 CONCEPT_HDL CORE Inconsistent behavior of the Move command when moving a symbol7 f9 Q1 G; S/ [3 v( J, W! [
1743992 CONCEPT_HDL CORE Inconsistent behavior of the Move command when moving a symbol& v5 x$ h) h/ N! ]6 \' U( R
1736093 CONSTRAINT_MGR CONCEPT_HDL Incorrect topology extraction and mapping errors related to MUX parts! s7 t8 P8 N7 N+ h) e
1743518 CONSTRAINT_MGR CONCEPT_HDL Lag observed in expanding and collapsing the net classes in Constraint Manager- O0 n; Y1 _5 x5 {2 E
1730159 FSP ALLEGRO_INTEG FSP diff engine does not read PF Thevenin connections in FSP
/ k% E i9 a, F% }: ]9 o1664070 ORBITIO ALLEGRO_SIP_I Display pads of SMD components on correct layer* G" c! s$ q) I, }
1709319 ORBITIO USABILITY OrbitIO issues an error about Device template while importing brd with Bundles5 I% O! T& k2 }& h
1741150 PSPICE ENVIRONMENT Need a way to prevent the 'pspSimSetting.js' file from being overwritten by a hotfix installation in 17.2! K2 R, e, H. A- ~3 ]1 |: X
1735354 PSPICE SIMULATOR Access to custom nom.lib is not working as expected# W# M3 u. y7 e# v6 f* E8 O& o/ A
1716523 SIP_LAYOUT COLOR Tool crashes on using the PageUp, PageDown, and Tab keys in the Color dialog box.7 E# F; ]% f/ v9 T2 B5 ?3 u
6 M. z# }2 N* l0 S* q" L1 d( B3 p; W. p3 P( i+ H
Fixed CCRs: SPB 17.2 HF019
9 f& o; k* A$ N( j& B$ \. l05-6-2017
9 \% c" n; r* |# t: }========================================================================================================================================================0 e) K: N, \; e% \7 g7 W e
CCRID Product ProductLevel2 Title
9 p' _5 H! m/ o5 n========================================================================================================================================================8 Y9 ?/ L7 ]5 t, Q$ t+ a7 k, @
1701785 ADW ADWSERVER Getting 'Unable to locate tools.jar' error while using 'Copy Projects'
- I6 a! `' c+ N+ g! \1706782 ADW ADW_UPREV Design uprev failed with error 'ERROR (FM-107): Failed to run adw_uprev'. A1 \" |. j' A. R6 N0 O' m& `
1508159 ADW FLOW_MGR Flow Manager 'Open Last Project' option points to a deleted project L. b0 u0 E+ Q: L
1690903 ADW FLOW_MGR Flow Manager library project list empty after 'Remove From List'7 i$ x" \8 ^4 d
1705224 ADW LIBDISTRIBUTI Cannot migrate Library Footprint Models having subdirectory to release 17.2-2016
. O' T8 b5 K) W1672037 ALLEGRO_EDITOR EDIT_ETCH Add ZigZag Pattern crashes PCB Editor* ~0 M/ X* E& Q& V+ @5 S+ J
1695711 ALLEGRO_EDITOR EDIT_ETCH In release 17.2-2016, Fiber Weave Effect - Add ZigZag Pattern crashes in Windows 10
" v# G3 M1 l- K# D1706522 ALLEGRO_EDITOR INTERFACES DFX import displays error message '*Error* eval: undefined function - cloneID' but imports outline
4 \" N# X6 W; {- z I3 T0 R) A3 m1716336 ALLEGRO_EDITOR INTERFACES DXF file is not correctly imported into PCB Editor( t! p6 @7 }" k% j( p
1720290 ALLEGRO_EDITOR INTERFACES Incorrect rotation of padstack after dxf import) N! Q& v/ K" e- p R9 r) N; T
1724683 ALLEGRO_EDITOR INTERFACES DXF OUT: incorrect Rounded/Chamfered rectangle pad rotation( d8 F4 k4 o: A- K' ]9 |- @/ C
1732587 ALLEGRO_EDITOR INTERFACES Format/content of ipc356 files exported in release 17.2-2016 different from release 16.6
$ @: P5 s' e- Q4 f4 S' B. D. r6 g0 S1737516 ALLEGRO_EDITOR INTERFACES IDX Import works differently for placed and unplaced parts
; {1 g( O6 H7 _1715152 ALLEGRO_EDITOR SCRIPTS Clicking Layout in Project Manager fails to load PCB Editor and gives message 'Word too long'
0 b- r, l+ A# D9 w940699 ALLEGRO_EDITOR SHAPE Update shape to smooth fails to void a few clines.
* [+ S j! {, O/ B; e* s' u1706581 ALLEGRO_EDITOR SHAPE Dynamic shape void clearance errors with vias1 [: e2 [* u2 t9 J
1638300 ALLEGRO_EDITOR UI_GENERAL Version information set in $cdsversion truncated on title bar for some tools
4 g6 J- C8 E0 O/ J1697732 CONCEPT_HDL CORE Pasting a signal name results in warning (SPCOCN-922) if the wire is too close to the edge of the page border
9 G( l* y! Q2 G, N6 b6 \, {5 A* ]1729510 CONCEPT_HDL CORE Changing the name of a split block adds pages that are part of the page gaps: y$ |6 \: R {; e$ ^) Y' v) Q
1721065 CONSTRAINT_MGR CONCEPT_HDL Physical import errors on changing plane to conductor in stack-up
& x8 V7 J- d. Y8 U0 d9 r. ^1734875 CONSTRAINT_MGR OTHER 'Create Spacing CSet' crashes tool from existing CSet context and grayed out in design context. y; ?3 w6 }4 v# G
1473104 ECW PART_LIST_MAN Pulse does not filter capacitor values correctly
3 e( E% F( d3 _# |' f* }9 m8 u7 f1736580 PCB_LIBRARIAN SYMBOL_EDITOR Grids are not displayed correctly in Symbol Editor
) P: q" J9 _! d, C; B7 s1738955 PCB_LIBRARIAN SYMBOL_EDITOR Need ability to edit Symbol Properties4 t* e" _. N& W9 E/ J6 d9 J" }0 y% p7 E
1735215 PSPICE FRONTENDPLUGI PSpice part search customization CDN_PSPICE_ODBC_SRC environment variable is not working) o) g* s- b: n- `! Q- V
1733198 PSPICE PROBE Probe crashes when exporting trace expressions with multiple plots to CSV files9 g w) R' d2 R7 w+ W" S
1737060 SIG_INTEGRITY SIGNOISE signoise fails for the AllegroSigrity_HS_Base_Suite option in release 17.2-2016 and release 16.6-2015
- i2 K$ v4 k6 M/ b8 R+ V) s" o: U1707443 SIP_LAYOUT WIREBOND Moving bondfingers violates spacing constraint
$ q" w8 ^2 a9 l8 w. {. ?; {/ C9 q1 H& I) S% j
' R, [: N2 u* M" U- lFixed CCRs: SPB 17.2 HF018
: ^( W" x: }: e1 r, g, i04-23-2017
9 {$ Y. [! _2 E' k========================================================================================================================================================
3 I& J Q9 d' e; U3 w! {CCRID Product ProductLevel2 Title
7 t! P* W: `0 w3 X========================================================================================================================================================
Z4 N7 _" i2 Z+ U1721773 ADW ADW_UPREV adw_uprev updates all versions in history log to the new version. Should only insert note about uprev.
! _" a3 k) L' D5 r) m Q1684346 ADW LIBDISTRIBUTI lib_dist_client fails for new release 17.2-2016 design server- v1 D3 Q1 ~$ @3 ?, H
1696632 ADW LIBDISTRIBUTI lib_dist_client fails on release 17.2 Designer Server having release 16.6 Master Server
* ~% z- J3 r# x3 {6 q1705224 ADW LIBDISTRIBUTI Cannot migrate Library Footprint Models having subdirectory to release 17.2-2016
3 q( L; S, t* h; z( @6 F+ k1 q$ i8 M1721017 ADW LIBDISTRIBUTI adwserver -install fails intermittently during Master Library Server or MLR distribution
1 y2 }+ s' a/ ~% o1711373 ALLEGRO_EDITOR COLOR Cannot interact with Allegro PCB Editor when Color dialog is open
6 t9 u `2 ^. i" N9 U1710772 ALLEGRO_EDITOR DATABASE Mirror command not working on zones* N% l: |0 r. \, p! g
1725621 ALLEGRO_EDITOR DATABASE PCB Editor crashes when moving a group of components or clines6 O! n, S. [" k. e, P. I; f8 @* q" {( z k
1699796 ALLEGRO_EDITOR EDIT_ETCH AiDT fails and reports there are no timing constraints even when propagation delay is set
+ z4 G: c% x& R1726483 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashing when converting corners to arcs
/ r$ r) g3 o% H. `5 H- P7 W1726678 ALLEGRO_EDITOR INTERFACES IDX copper layer export does not export all pin pads2 J' \/ a; k: g" [- W
1691036 ALLEGRO_EDITOR MANUFACT Fillet not centered on trace8 q3 M2 g7 ]' w! @
1732304 ALLEGRO_EDITOR MANUFACT Countersink does not have drill figure on NCCOUNTERDRILL-1 subclass
# _& s7 T. ^8 r& ~5 c* o1719564 ALLEGRO_EDITOR OTHER Cannot open PDF published in release 17.2-2016 in third-party software
) s4 E7 v# a3 p# A) D1723065 ALLEGRO_EDITOR OTHER PDF out does not print the outline correctly9 a3 m$ g2 {3 J" `0 H8 ^! I4 I
1729247 ALLEGRO_EDITOR OTHER Cannot delete shape on Route Keepout layer
8 G7 {4 V1 D# C1722747 ALLEGRO_EDITOR PAD_EDITOR Option to enable 'Connect by Touch' in Pad Editor
/ K' |* \0 K9 X) N% g1731643 ALLEGRO_EDITOR PAD_EDITOR Changes to secondary drill are not saved on padstack update
! L- l, s* i, b' w: }& _6 T1727303 ALLEGRO_EDITOR REPORTS The 'Shape Dynamic State' report has changed to 'Shape Dynamic Status' in release 17.2-2016! K0 k% F0 ]7 ]) X5 S& I# b
1695879 ALLEGRO_EDITOR SHAPE Dynamic shape priority error creates shorts.
9 b9 w: T* r5 ]1713014 ALLEGRO_EDITOR SHAPE Incorrect behavior of donut shaped pads at certain rotations8 K8 N# w6 B, l0 {) R5 x
1588769 ALLEGRO_EDITOR UI_GENERAL Alt+key shortcuts are not available in release 17.2
6 o2 ?- k8 T9 |9 M; o( s5 K1602563 ALLEGRO_EDITOR UI_GENERAL Shortcuts to menu items not working in release 17.2
# f% ]9 v+ F7 A, p/ s1603776 ALLEGRO_EDITOR UI_GENERAL Alt key not working with menu commands, S: q% c. D1 I3 _$ r7 W. N
1611516 ALLEGRO_EDITOR UI_GENERAL Keyboard shortcuts have no response
0 J% V, a! @2 ?" n9 z1647271 ALLEGRO_EDITOR UI_GENERAL Preselection is not working for docked Find window
( J& }0 a8 S" h0 y" z& L1650044 ALLEGRO_EDITOR UI_GENERAL Keyboard shortcuts are not working properly in release 17.2
8 G$ A7 E1 i+ Y9 W; |" r& H+ D1651912 ALLEGRO_EDITOR UI_GENERAL Inconsistent response when using the Alt key% i- y3 }$ k( a; V" d0 B v( s
1679964 ALLEGRO_EDITOR UI_GENERAL Many dialog boxes are blurred in Allegro PCB Editor% d! [+ s ^9 X S/ O+ @
1692416 ALLEGRO_EDITOR UI_GENERAL Underscores in menu commands denoting shortcuts are missing in release 17.2
; H4 L- b, R" D$ ? I( {0 ~+ ^* |1693055 ALLEGRO_EDITOR UI_GENERAL Reports with html links end with an extra > at the end ^7 \$ [& d9 b4 N/ R
1693968 ALLEGRO_EDITOR UI_GENERAL Batch process that uses SKILL is taking too long to process files and generate reports
# ? l# |7 ?0 p/ S! f1698840 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016 Waive DRC report, selected coordinates of a Waived DRC remain blue" g* ]( i& q3 O5 x) W* A: L
1703065 ALLEGRO_EDITOR UI_GENERAL Menu shortcuts do not work as expected. e' P3 _. p$ w2 t. x- a3 w3 z. S
1707547 ALLEGRO_EDITOR UI_GENERAL Release 17.2: The Alt key function is not working in PCB Editor
1 K" ]3 h+ c* M I! \1709280 ALLEGRO_EDITOR UI_GENERAL Alt+Function key not working in release 17.2.: h: u! ^5 f- Y' Z
1711203 ALLEGRO_EDITOR UI_GENERAL Color does not change for selected coordinates in reports and Show Element
9 E; Z/ x% N$ c9 E8 G) ^1 o1711724 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, custom interactive menus stop responding when invoking another custom command& C5 A2 a, e0 T( x4 Q" z. P
1715613 ALLEGRO_EDITOR UI_GENERAL With undocked Options window there is a mix up of entered text and funckey' h( a+ h+ y9 W, U
1719301 ALLEGRO_EDITOR UI_GENERAL Selected coordinates do not change color in reports and Show Element
" d' V2 y) `' D" @8 f; W( {% M1724197 ALLEGRO_EDITOR UI_GENERAL Short cuts and hot keys not working in PCB Editor in release 17.2-2016* C5 {; D5 G& L1 l r" j/ U
1728724 ALLEGRO_EDITOR UI_GENERAL Funckey is not working in release 17.2-2016
& M; v. k3 t& B- L. A! L, k1673703 ALLEGRO_PROD_TOOLB OTHERS Design compare not reporting the Top and Bottom layer differences
: p k6 g; Z9 \1 s% h1704474 ALLEGRO_PROD_TOOLB OTHERS When using Productivity Toolkit - PCB Design Compare, 'Override undefined width' is incorrectly applied
" v8 ]5 W) A' s5 `0 b8 @" y5 H5 ~" K1571035 ALTM_TRANSLATOR CAPTURE Circles in third-party schematics not getting translated into Capture
; h5 }& `" c; s$ z1588911 ALTM_TRANSLATOR CAPTURE Capture crashes when translating, project and libraries are empty- p7 d0 X+ M+ i5 F
1589394 ALTM_TRANSLATOR CAPTURE Schematic getting shifted off the page after translation
3 ^2 O) o2 \# J! z' q7 V1631294 ALTM_TRANSLATOR CAPTURE Errors while translating third-party design when original design is in metric units
& T# q; }! @' H* D1663176 ALTM_TRANSLATOR CAPTURE Only first sheet of design getting translated from third-party schematic into Capture; H0 d, K8 \7 |* T% `+ j- e
1694363 ALTM_TRANSLATOR CAPTURE Capture is unable to translate third-party designs
8 b3 W" S" B1 }1539739 ALTM_TRANSLATOR CORE Capture crashes on importing a third-party project
$ q z1 I- B3 n: i- O+ Y% M. w1542860 ALTM_TRANSLATOR CORE Capture crashes on clicking Translate after selecting a third-party design
/ P9 Q' H1 N4 s) b$ F! [1551642 ALTM_TRANSLATOR CORE Unable to import third-party schematics into Capture5 d3 D( n1 N0 F6 r: g% {- {5 Y8 L
1572929 ALTM_TRANSLATOR CORE Footprint names getting altered during translation
# t2 U: _; J1 g7 g/ x, f: Y7 c1568436 ALTM_TRANSLATOR PCB_EDITOR Unable to translate third-party layout data into PCB Editor
; E/ A+ v; y9 G" }1629256 ALTM_TRANSLATOR PCB_EDITOR Getting empty symbol and devices folders when importing into PCB Editor0 I- h' }" t9 h2 s1 L& Z. |6 T5 y
1664120 ALTM_TRANSLATOR PCB_EDITOR Import from third-party to PCB Editor is not translating data correctly
$ t, z% O- O0 D7 W# k- ?; ?6 g1701537 ALTM_TRANSLATOR PCB_EDITOR Import does not complete and reports errors
# M" S; Q- V+ \; u1698706 APD DIE_GENERATOR When using Compose Symbol from Geometry, circle from DXF cannot generate to pin- {2 M. n3 j" p3 x& ]- P0 g
1714528 APD DIE_GENERATOR Getting 'illegal pad pointer' warning when creating die from geometry$ x* e3 ~1 w& O& P# q+ g9 J
1714532 APD DIE_GENERATOR Compose Die from Geometry creates incorrect pad shapes
% V4 M0 d0 ~# q+ l1734310 APD MULTI_USER Symphony server mode malfunctions when die layer present.
' B6 I. O. U/ b R* m B9 r: `' D1725506 APD SHAPE In release 17.2-2016 Hotfix 015, void is not generated in Artwork for BC7 layer causing short
8 w- |' |' T: E" n; {1724395 APD WIREBOND Running axlBondWireDelete returns error message
1 T; s; p$ C" q# @. T1726609 ASDA CANVAS_EDIT Paste should not be allowed in the Current Refdes column of the Change Refdes form
' |9 h# ~# Y" i% [6 J& `1719754 CONCEPT_HDL ARCHIVER Path stored in the compressed file starts from /home instead of the current working directory
& |. ~' Q8 L/ T3 ^1726570 CONCEPT_HDL CHECKPLUS Checkplus crashes on Windows 103 f6 s/ o3 y' T+ q8 m
1697977 CONCEPT_HDL CONSTRAINT_MG Differential pair disappears when it is packaged3 D# c2 t7 ^6 Q, I
1679575 CONCEPT_HDL CORE Page numbers are duplicated in Hierarchy Viewer when editing page names9 d/ X3 z* e: Y$ {
1697732 CONCEPT_HDL CORE Pasting a signal name results in warning (SPCOCN-922) if the wire is too close to the edge of the page border
3 m- r% [8 ~8 {1 A6 o5 n) v' t1711564 CONCEPT_HDL CREFER CRefer crashes while processing a hierarchical design containing subdesigns
$ z2 _0 F1 r Q. r% M+ {3 l0 C1730736 CONCEPT_HDL OTHER Crash on generating BOM from design
7 I9 w) k: c* ~, J# l$ d8 h1608350 CONSTRAINT_MGR CONCEPT_HDL Name of buffer model is not passed from Constraint Manager of DE-HDL to SigXplorer$ H7 u# ~9 S0 c3 U
1715803 CONSTRAINT_MGR CONCEPT_HDL Extract a net from constraint manager to SigXplorer, the models assigned are not displayed in SigXplorer; H6 z" l: b% C/ ]# Y. a
1718073 CONSTRAINT_MGR CONCEPT_HDL ECSet mapping errors on an upreved design in release 17.2: Pins in XNet and CSet do not match6 t& X, x9 F) U: y. G
1720886 CONSTRAINT_MGR CONCEPT_HDL SigXplorer does not extract assigned model from the schematic
$ j1 F0 b1 P# X6 [1718514 CONSTRAINT_MGR ECS_APPLY Extracted topology does not use the PINUSE overrides specified on the canvas
1 H5 _, w7 R _7 g- F1722306 GRE CORE Boards with Total Etch Length constraint only should not include z-axis when budgeting pin pairs
) E9 ^) L3 B( i/ [1710049 PSPICE SIMULATOR Functions are not taking parameters in correct order
. T2 y' k4 @: y6 M8 a1693021 SIG_INTEGRITY OTHER PINUSE is not updated correctly at model assignment with specific steps2 w" q3 v/ M8 l' a% c! y8 C5 K! @
1730854 SIP_LAYOUT SYMB_EDIT_APP Cannot delete all the die pin from a symbol using the Symbol Edit application mode
0 V X1 Z. R- d* n( P' O
7 ~+ L+ ~5 K. l; t- B, T) c0 { v! ? w& \# s! Y/ F" a
Fixed CCRs: SPB 17.2 HF017
% b' t! }1 O* p04-13-2017( T9 d9 d: Y/ o5 T3 q
========================================================================================================================================================
6 J! G3 F0 P' i4 OCCRID Product ProductLevel2 Title6 _1 A1 {) [8 z' I5 d
========================================================================================================================================================
7 Y& D5 f3 D3 [8 w1732877 ALLEGRO_EDITOR SKILL The 'axlXSectionGet' function fails in release 17.2 Hotfix 016
- p8 H* d8 X( Y9 J" f, u" r! q* ^( E7 U* }0 b1 _
& @" e2 _2 W( n( ?
Fixed CCRs: SPB 17.2 HF016- I' d; l" n9 C
04-6-2017
% K- `! w6 ]/ R6 l' S========================================================================================================================================================& n2 Q: y6 |( l1 m. W
CCRID Product ProductLevel2 Title
8 m0 _' n8 \5 B+ d1 o/ b========================================================================================================================================================
5 I) A9 `0 D% _6 h8 l1673128 ADW COMPONENT_BRO Directive is saved in project CPM
" M& b1 w N# S7 w& f2 d. i1673510 ADW COMPONENT_BRO Lifecycle status color column is not sorted correctly in Component Browser search results
6 n, ~- V6 O5 ^' ]9 L4 v9 x1604734 ADW DATABASE Parts displaying non-key properties and values in the Component Browser in ADW
+ s% A0 J) W2 W, O$ f! T1142957 ADW DSN_FLOW No Help available for schematic design verification7 R* d+ h( X; k/ N
1609186 ADW DSN_MIGRATION ADW Design Migration utility should handle ADW board reference projects and manage atdm.ini
% g0 o/ ]& `& ~' {1591757 ADW GENERIC_UI Running 'Create Test Schematic' in ADW Flow Manager results in Error SPCOCN-1736/ k. k" Y8 \7 Y3 s& C
1588111 ADW LIBIMPORT Library Import fails with Java errors while processing .csv files* t h2 k7 a2 R6 t/ Y' }7 Q
1642367 ALLEGRO_EDITOR 3D_CANVAS Component height is not correct in new 3D Viewer9 V( n5 s# w6 N; }
1642668 ALLEGRO_EDITOR 3D_CANVAS The new 3D canvas does not show STEP model of the drawing (.dra)$ h2 L9 n$ l% O4 P5 L" c
1653247 ALLEGRO_EDITOR 3D_CANVAS New interactive 3D Viewer shows wrong placement
* L* m1 l4 R1 k! n6 L1658275 ALLEGRO_EDITOR 3D_CANVAS Components on the bottom side are shifted in the new 3D view
7 h q8 c0 b% q% \5 `+ g& J1639244 ALLEGRO_EDITOR ARTWORK When importing an artwork, a sub-folder is created with the value of the ads_sdart environment variable1 S- A* f, t& c# q7 S3 j- G
1658173 ALLEGRO_EDITOR ARTWORK ARTWORK: Value of Scale factor for output.
0 ]& P9 ~8 y5 M" d, O- w; A1661760 ALLEGRO_EDITOR ARTWORK Import artwork to Design Outline layer does not give error in Allegro prompt.
/ k' S: |* r5 e& V2 `- z1 }$ y* z1667778 ALLEGRO_EDITOR COLOR Add option to set FORM mini dehl_retain_color to NO, b4 A9 Q$ n1 a5 H. K
1669462 ALLEGRO_EDITOR COLOR Changes made to the Visibility tab are not reflected in the Color Dialog window0 q; O/ d. e3 t% Q
1641265 ALLEGRO_EDITOR CROSS_SECTION The differential impedance value for a layer is not getting updated! @! J- F$ M# n ^7 P
1648149 ALLEGRO_EDITOR CROSS_SECTION Getting warning when calculating impedance in mixed stackup- u: l; o! Q: o9 t$ B
1671441 ALLEGRO_EDITOR CROSS_SECTION Enhancement request for cross section dialog box: P0 v2 l q" t6 u
1673320 ALLEGRO_EDITOR CROSS_SECTION Diff impedance calculation fails0 D. I4 P8 X; }& z1 `( Y% r
1690021 ALLEGRO_EDITOR CROSS_SECTION How to keep settings of expanded/compressed columns in the Xsection* P0 X& P! q2 I4 x. y
1703831 ALLEGRO_EDITOR CROSS_SECTION Calculation of Diff Z0 fails in flex designs
3 [" ~* f6 x2 m; r8 T1 X u& G0 P1711484 ALLEGRO_EDITOR CROSS_SECTION ShowAll Column does not retain its status
4 L; w7 v1 C9 C/ w! O. u; K, a; p1672841 ALLEGRO_EDITOR DATABASE ERROR(SPMHDB-153): Table corrupt; current/maximum mismatch
8 y0 w/ ?- R9 [" E; M1673613 ALLEGRO_EDITOR DATABASE COVERLAY_TOP not present in the Non-conductor section of Color Dialog window
3 x5 K# O0 A6 F6 o" s1688123 ALLEGRO_EDITOR DATABASE Drill Plating Issue; Q) B% v$ }# `+ q
1701995 ALLEGRO_EDITOR DATABASE When upreving a 16.6 brd to release 17.2, lines drawn on OUTLINE are translated to CUTOUT and not DESIGN_OUTLINE
: _4 P5 v$ G7 m' |- I! c1710772 ALLEGRO_EDITOR DATABASE Mirror command not working on zones. H) K' R( `3 A2 Q
1713335 ALLEGRO_EDITOR DATABASE Defining Adjacent_layer_keepout_above and/or Adjacent_layer_keepout_below and then saving the .dra file giving error
. M8 ~" x6 }" p0 z8 N1 ^1693289 ALLEGRO_EDITOR DFA File - Save As script does not save the DFA file3 _3 I; g4 P. [% m" C
1644004 ALLEGRO_EDITOR DRC_CONSTR Unreported DRCs from dynamic copper to line and dynamic copper to SMT pin! F! ]1 t0 l" X; s% p
1651425 ALLEGRO_EDITOR DRC_CONSTR The .brd file crashes when moving text controlled with minimum metal to metal constraints
( s9 \. E8 M; `3 I" o1663494 ALLEGRO_EDITOR DRC_CONSTR Reported Mechanical Pin to conductor spacing DRC constraint value is incorrect leading to false DRCs$ U! o+ `0 _' K7 N
1687049 ALLEGRO_EDITOR EDIT_ETCH Create a Via Structure disconnects nets- o9 ]4 W( Q. m; N4 P% J6 G
1704296 ALLEGRO_EDITOR EDIT_ETCH Asymmetrical fanout created for BGA Quadrant style
; P/ w5 H9 _/ ?4 m. [1686873 ALLEGRO_EDITOR EDIT_SHAPE Merge static shapes deletes both the shapes selected.
9 I% \% g/ ~' B" E% J1629925 ALLEGRO_EDITOR GRAPHICS Errors reported and no layout data drawn in PCB Editor in release 17.2 Hotfix 003 on Ubuntu 14.04
) q9 A- b6 k& p/ H/ v, \1628895 ALLEGRO_EDITOR INTERACTIV Shape Edit mode: An error message is required when attempting to edit a Shape with the FIXED property
5 e6 o B6 [" @9 ?4 u2 N& w1666379 ALLEGRO_EDITOR INTERACTIV Place replicate is not working on the attached test case% u- N/ e9 T# ]
1668282 ALLEGRO_EDITOR INTERACTIV Grid display incorrect for repeated grids
& `: R% x( G8 { v$ h% X# s! K+ i1675531 ALLEGRO_EDITOR INTERACTIV Design Entry CIS: Cross Probing with PCB Editor and Constraint Manager is not working1 j* D2 z( n" z1 J8 @
1694470 ALLEGRO_EDITOR INTERACTIV Update description of variable padstack_nowarning_display0 A/ \0 W7 }0 D2 b
1696855 ALLEGRO_EDITOR INTERACTIV Mixed grid setting is not displayed correctly on Define Grid screen.+ Z6 I4 ]& B4 j/ e
1698192 ALLEGRO_EDITOR INTERACTIV Deleting and replacing a component causing database corruption in Hotfix 009
* U% J% n }# }" u Q$ a" B @1703671 ALLEGRO_EDITOR INTERACTIV An error occurs when defining grids with zero increment value
* w( J# u2 Y( }: I; A1 w3 c3 [; r1703812 ALLEGRO_EDITOR INTERACTIV Crash during move when using the 'snap pick to' option set to symbol origin
# n. a8 [* p+ B% E+ R+ I M% o8 S1719276 ALLEGRO_EDITOR INTERACTIV Setting variable grid for 'All Etch' displays an error in the Define Grid form. f' R2 d! r% j% |
1663422 ALLEGRO_EDITOR INTERFACES Shape loses group membership after importing through sub-drawing T4 u" @) l8 m
1637959 ALLEGRO_EDITOR MANUFACT Thieving uses different clearance values around the route keepin.6 b8 `: I- b7 N& ^
1716431 ALLEGRO_EDITOR MANUFACT Test points generation stops due to an error
7 Q% w8 n* _. \1641994 ALLEGRO_EDITOR OTHER DB Doctor: Incorrect spelling of 'eliminated' in the log file messages
, @# K, e2 [3 w1660496 ALLEGRO_EDITOR OTHER SiP Layout crashes when trying to generate abstract level view by using export chips and connectivity+ ?0 j; o: a1 y/ ^1 O& |
1685464 ALLEGRO_EDITOR OTHER The 'alias ~S save' command is not recognized when set in the local env file
% ]1 d7 N4 m. P/ Q7 s' U5 O+ u: L1696486 ALLEGRO_EDITOR OTHER STEP export results vary between releases 16.6 and 17.2* M1 T$ z" e; L2 H1 I, L
1706623 ALLEGRO_EDITOR OTHER axlBackdrillGet crashes for invalid argument
/ z4 B- p; l/ R% z0 Q+ `. [1586957 ALLEGRO_EDITOR PAD_EDITOR In Pad Editor, selecting a pad geometry is not showing up in the Design Layers tab) e5 M: n* W( j7 N; A) j
1610984 ALLEGRO_EDITOR PAD_EDITOR Geometry set in tabs not read, only initial value set in Start page is used
! F6 r) ~+ r7 b: X1614015 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor in release 17.2 does not auto fill geometry in design layers; ^# I& \0 `! q C
1636012 ALLEGRO_EDITOR PAD_EDITOR Keepout should not be allowed if antipad is not defined for outer layers& @8 J9 M d& n9 L
1641973 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor: Path to the previously opened .pad file is not seeded in the File - Open dialog on a fresh launch/ D# ^4 H- ` |6 |
1642789 ALLEGRO_EDITOR PAD_EDITOR In release 17.2, 'Units' and 'Decimal Places' in Padstack Editor are not updated as per the .pad file) U8 r; y4 m1 @6 [2 F' }* z
1646914 ALLEGRO_EDITOR PAD_EDITOR The 'Save' button is grayed out in Padstack Editor
/ M$ j% a; U$ ~1657553 ALLEGRO_EDITOR PAD_EDITOR No possibility to specify Padstack Editor default library path at invocation
0 l% D* }# |6 r' |" U! \1657609 ALLEGRO_EDITOR PAD_EDITOR Changing Tolerance field in Padstack Editor does not activate the Save button
6 O9 S) y1 m3 Y/ w% T& h) h2 f( f1662225 ALLEGRO_EDITOR PAD_EDITOR Padstack editor dialog message doesn't match available options; P4 _6 A- Y; L5 d5 ], v( x& v+ f
1667062 ALLEGRO_EDITOR PAD_EDITOR Padstack editor does not retain the decimal places from the previous session
& \/ X8 V$ F3 s1672774 ALLEGRO_EDITOR PAD_EDITOR Pad Editor graphics appear to show offset incorrectly
1 R& e9 l) o3 K& f1674157 ALLEGRO_EDITOR PAD_EDITOR Update Symbols does not update Pad Type Information
- p$ x/ T7 v* r# G5 d1675438 ALLEGRO_EDITOR PAD_EDITOR Drill hole size warning for the SMD pad6 Z W0 ^# v9 J @* e3 G! R( T
1684376 ALLEGRO_EDITOR PAD_EDITOR Pad Editor issues with settings, such as decimal places, layers, and so on! k K7 _5 l- r3 L; p2 v, [3 p
1690376 ALLEGRO_EDITOR PAD_EDITOR Variable padstack_nowarning_display fails to suppress warnings
3 P# \/ o$ s3 D0 h2 b* s% x" a1694649 ALLEGRO_EDITOR PAD_EDITOR Change Cancel button to No in warning generated when updating padstacks in design layout) ?. K* R) F6 |3 V4 {
939242 ALLEGRO_EDITOR PLACEMENT Cross probing between Capture and PCB Editor is inconsistent8 @# W/ X5 {: h
1103945 ALLEGRO_EDITOR PLACEMENT Place Replicate Create does not include the etch connected to pin" x) d, `$ _* g; U
1233019 ALLEGRO_EDITOR PLACEMENT Allow cross probe object selection apart from highlighting during place replicate1 f) |$ d2 G" _7 W9 X+ I- N S
1643078 ALLEGRO_EDITOR PLACEMENT PCB Editor flags an error message when a module is placed at a specific angle
5 [( T4 B& H2 b+ K% Q% Z; B1696932 ALLEGRO_EDITOR PLACEMENT Inconsistency with Snap pick to when selecting Segment Midpoint& v3 S1 `* X4 A# ]
1654500 ALLEGRO_EDITOR REPORTS In release 17.2 Hotfix 006, display of Netin (back anno.) report fails when variable ads_sdreport is set% _4 Q+ B! m' D/ x
1643992 ALLEGRO_EDITOR SCHEM_FTB Export Physical fails with the 'netrev.exe has stopped working' error
: n. U+ o6 J* H" s( p1653400 ALLEGRO_EDITOR SHAPE Dynamic shape does not void a via.6 N, ]7 h- B" Q+ A7 v% C6 B
1668262 ALLEGRO_EDITOR SHAPE dynamic shape does not void custom route keepout with arc) u- o. d0 D" Q# g. K& d" k% x/ d
1682569 ALLEGRO_EDITOR SHAPE Variable 'dv_squarecorners' not working correctly. i6 c2 S: k5 S3 e7 ^
1696240 ALLEGRO_EDITOR SHAPE SKILL error when merging polygons
! Y/ C( F6 k7 N1709968 ALLEGRO_EDITOR SHAPE In release 17.2, DB Doctor reports error in shape when no error was reported in release 16.6 for the same shape0 T R! l- ?3 [2 S
1632505 ALLEGRO_EDITOR SKILL In release 17.2 Hotfix 004, PCB Editor crashes after SRM update and save
: ?# e. \: e% P9 T8 G& |$ Q3 U1651701 ALLEGRO_EDITOR SKILL Cannot set the etch factor value in the cross-section using the axlXSectionModify() SKILL command
* s; g% H" i3 f1658419 ALLEGRO_EDITOR SKILL PCB Editor crashes after running SRM. v" r1 g' z" j, z4 z
1658948 ALLEGRO_EDITOR SKILL axlIsLayerNegative() is not working in release 17.2
2 ]- m8 {# i3 ?- I0 M5 m6 f# l) {1670956 ALLEGRO_EDITOR SKILL axlIsLayerNegative() always returns nil' S8 w% B7 v+ Y8 K. Z3 l/ R4 L
1687239 ALLEGRO_EDITOR SKILL Problem with SKILL function axlCNSGetPhysical - incorrect parse string9 d9 ?4 l0 Q/ m" [& D
1692345 ALLEGRO_EDITOR SKILL The axlGetParm documentation example for deleting an artwork record is incorrect.
" U0 d0 N3 @) Z1707878 ALLEGRO_EDITOR SKILL Object rat_t does not work with axlDBPinPairLength.
, _+ [$ q" @8 N6 b' e S! ]- O1598061 ALLEGRO_EDITOR UI_GENERAL Adjust menus to allow side by side view
' f% r! V0 m: F( _# v1599901 ALLEGRO_EDITOR UI_GENERAL Color Dialog box is not updating according to visibility tab.* y& h. m. J7 {/ G+ U
1602563 ALLEGRO_EDITOR UI_GENERAL Shortcuts to menu items not working in release 17.2
8 w% k0 g, A J) c/ x1603776 ALLEGRO_EDITOR UI_GENERAL Alt key not working with menu commands6 q5 c# c# l& \0 ~9 f* b* }+ W. l) z
1611516 ALLEGRO_EDITOR UI_GENERAL Keyboard shortcuts have no response, n; ]% N: O* @5 A3 Q8 u+ {
1614763 ALLEGRO_EDITOR UI_GENERAL Cannot scroll to the bottom of an undocked command window in PCB Editor6 L) i$ @9 d: b$ S
1619873 ALLEGRO_EDITOR UI_GENERAL Command Window scrollbar does not reach its end
0 j6 x$ M/ n8 v5 h2 Q6 u- U0 P! z1624617 ALLEGRO_EDITOR UI_GENERAL Dialog box title under Setup > Outlines > Design Outline... Design is misspelled as "Desgin"3 \6 T& b$ R* H/ f
1631646 ALLEGRO_EDITOR UI_GENERAL Visibility pane not retaining the correct layer view* \! w( z' P3 f2 [0 ]
1637062 ALLEGRO_EDITOR UI_GENERAL The last line of the floating command window in release 17.2 is hidden behind the command window frame
$ n, p/ T, S3 l5 d' K6 g) A1642645 ALLEGRO_EDITOR UI_GENERAL Cannot scroll to the bottom of an undocked command window in PCB Editor+ U( U% g7 U5 s4 C
1645335 ALLEGRO_EDITOR UI_GENERAL PCB Editor crashes in Hotfixes 004 and 005 if ODE and Allegro Manufacturing options are installed8 b4 s- I1 T+ R* c' a# @5 M# h, N9 Z
1647520 ALLEGRO_EDITOR UI_GENERAL PCB Editor crashes after installing release 17.2 Hotfix 0057 U1 X$ S' @. `- X$ ]; s. Q6 s2 j
1647541 ALLEGRO_EDITOR UI_GENERAL Release 17.2 Hotfix 005: PCB Editor crashes immediately after launch& ^' y |' M& \: {6 |3 K X+ t* G
1650044 ALLEGRO_EDITOR UI_GENERAL Keyboard shortcuts are not working properly in release 17.2! r# I, {7 i/ R2 c
1651912 ALLEGRO_EDITOR UI_GENERAL Inconsistent response when using the Alt key" b. p* X; C+ ?# i& Z/ D
1652423 ALLEGRO_EDITOR UI_GENERAL Using the F1 key does not display the help document
0 T" P$ x+ N0 z' i2 u& g0 ^6 B1 W1654600 ALLEGRO_EDITOR UI_GENERAL Spelling Mistake in "Design Outline" dialog box, Setup->Outlines->Design Outline, misspelled as "Desgin"
. R- {% u& x% G t1 [8 [+ s1654777 ALLEGRO_EDITOR UI_GENERAL Reports UI does not work properly when writing a report file.
" q6 b# {" t) ]1655500 ALLEGRO_EDITOR UI_GENERAL Visibility selection ignored after color change% |, v) t+ L1 J0 H7 V
1655514 ALLEGRO_EDITOR UI_GENERAL Artwork Film is available in the View section only after you restart PCB Editor3 e$ Z" A( G$ k; g! h# R
1663819 ALLEGRO_EDITOR UI_GENERAL In release 17.2, SKILL function, axlOpenDesign(), does not work as expected/ a0 G( N! o; r0 W0 o5 q8 p9 k
1671334 ALLEGRO_EDITOR UI_GENERAL Design outline is not shown in 'World View' window1 A, q: ^+ H Z6 U, `4 J/ Y" ^
1672148 ALLEGRO_EDITOR UI_GENERAL Add option in release 17.2 to change the placement of the Find, Visibility, and Options tabs similar to earlier release
' ^+ b9 k- R* S# ]0 y! G5 M1679418 ALLEGRO_EDITOR UI_GENERAL On choosing Edit - Move, the 'Symbol pin #' box is obfuscated
0 x; L$ D! H! q" l1679761 ALLEGRO_EDITOR UI_GENERAL Choosing Edit - Spin hides 'Symbol pin #' partially
M: _ w" V1 e, u* ]1686887 ALLEGRO_EDITOR UI_GENERAL Hyper Text no longer selects coordinates for easy copy, j8 V3 w" q6 ?0 E$ U0 v! p
1687286 ALLEGRO_EDITOR UI_GENERAL In 17.2 Hotfix 009, the Static Phase meter shows up in the middle of the screen instead of the lower-right corner8 E$ m: I$ r1 @$ @) P! x/ t
1692416 ALLEGRO_EDITOR UI_GENERAL Underscores in menu commands denoting shortcuts are missing in release 17.2
4 M9 E3 P+ u# _8 u3 ^1693968 ALLEGRO_EDITOR UI_GENERAL Batch process that uses SKILL is taking too long to process files and generate reports( i9 s4 Y& {2 {! Q( H" T
1702420 ALLEGRO_EDITOR UI_GENERAL Unable to maximize reports viewer in 17.27 Q! ^( {+ ~" F3 _0 u3 S1 j$ }; E
1703065 ALLEGRO_EDITOR UI_GENERAL Menu shortcuts do not work as expected
/ E A; {+ A4 K6 ?' r# N9 y3 W1703107 ALLEGRO_EDITOR UI_GENERAL Scripting using regional settings for decimal separator+ | H1 n4 A+ b D4 e
1707547 ALLEGRO_EDITOR UI_GENERAL Release 17.2: The Alt key function is not working in PCB Editor- w! x7 E0 s) h) L0 a
1709280 ALLEGRO_EDITOR UI_GENERAL Alt+Function key not working in release 17.2.
9 X( z; f; \$ ~1639896 ALLEGRO_PROD_TOOLB CORE MFG collector does not move files to subdirectories
8 q6 P {- E& O) x8 E h# s: n1608804 ALTM_TRANSLATOR DE_HDL Translation issues in symbols with multiple physical pins mapping to a single logical function
$ I5 ^8 w, Q* [' n0 c3 c+ O1658525 ALTM_TRANSLATOR DE_HDL Invalid characters in pin names
& x; b! s" s4 {6 h% l- W9 A8 d& }1658536 ALTM_TRANSLATOR DE_HDL All cell names should be generated in lowercase letters1 q* U5 p/ p0 g
1609962 ALTM_TRANSLATOR PCB_EDITOR Errors reported during design translation
) }! l+ \+ e3 D2 N7 D# v, M1661562 APD DRC_CONSTRAIN The wrong space calculation on finger to trace3 y. h* M ^5 ]4 e9 f9 X; Y/ V
1682398 APD SHAPE Deleting islands causes out of date shapes
5 b+ m3 U" |7 E6 h+ j# ]3 g+ J1638112 ASDA CANVAS_EDIT Unable to rename multiple selected buses using the 'Assign Name' command
1 A# p3 D; w% ~3 t8 r1645571 ASDA CANVAS_EDIT Various routing inconsistencies with synonym bodies on the canvas
/ w2 {0 J6 G0 g% U: b1656336 ASDA CANVAS_EDIT Presence of illegal characters in the net name removes the entire net name
, A v! f& `4 I0 u1 z' G0 i6 z1667176 ASDA CANVAS_EDIT Unable to add the port symbol in a specific scenario! ^. l' {! A1 W9 S( Q
1641473 ASDA CONSTRAINT_MA Importing a tech file into SDA makes the tool unresponsive8 Z2 t7 g; ?9 S3 X
1661350 ASDA CONSTRAINT_MA Unable to create physical & spacing class from the docked CM* U5 N) U6 q5 q* s' w1 l- r7 s' N
1645557 ASDA IMPORT_DEHDL_ Importing a DE-HDL design into SDA adds the COMMENT_BODY attribute to nets
6 U1 w0 M0 w* \3 X! q" g; N6 J, A- {1652753 ASDA MISCELLANEOUS Tcl command window should display correct casing for autocompleted command& ^' K. R# P) d$ w6 Z2 f% `
1654973 ASDA MISCELLANEOUS If there is a casing mismatch in the Tcl command name, correct command is not picked from the list6 U5 n8 m& l( R S8 Z' M+ ?
1652718 ASDA PAGE_MANAGEME Page numbering on the page border does not update correctly when pages are moved, added, deleted7 F' B/ `9 L6 }& J) e S( X; r( y' t
1699454 ASDA TABLE In the table object, cursor skips a cell on the first use of the TAB key
. F- |6 W! H5 Y$ b# s1702702 ASDA TABLE Copy-pasting table objects to a new page fills the headers and rows in black
5 i$ Y* Q y7 |. s1668877 CAPTURE ANNOTATE Using Ctrl+drag does not preserve the reference designator value
2 _; k+ Y& y! D8 l3 X) o0 K1665454 CAPTURE NETGROUPS Incremental copy for alias does not work anymore.) Z( `% j6 ~* r$ a
1634598 CAPTURE OTHER The ‘OrCAD_Capture_CIS_option’ license not released even after selecting another product option* }* E4 D3 Q1 ^5 V, F
1636090 CAPTURE OTHER Capture crashes after switching from release 17.2 Hotfix 003 to 004 due to some Tcl files
$ T3 [9 K4 @' ?8 q" v G1650029 CAPTURE OTHER Crash while archiving a newly created PSpice project without adding simulation profile
" C4 n( j1 l) h2 t1659602 CAPTURE OTHER Saving CIS BOM via TCL command window% ?5 I- C. o. ~5 C& Q F
1678715 CAPTURE OTHER Capture.ini [WebResourcesMenu] is not working in release 17.2: @0 _! A* O2 l% W0 e' m. I) O
1619449 CAPTURE PROJECT_MANAG Search not working in a PSpice project
& s: r Y( E8 ]8 t# C" m( N* {: g1670133 CAPTURE PROJECT_MANAG Start Page showing wrong Software Version* ~" f, L/ M+ C! P" O
1670766 CAPTURE PROJECT_MANAG autoreference does not work properly
2 |6 L( q8 X/ d1676095 CAPTURE PROJECT_MANAG (SID:22758) OrCAD Capture Start Page reporting wrong hotfix installed9 e2 V& P. [8 |4 b% n) q+ ?
1658315 CAPTURE TCL_INTERFACE Inserting text with double quotes is not working as expected in PDF created from Capture. _$ `" Z [! s8 V3 y+ G
1642601 CIS OTHER Design Entry CIS: SQL server password is required each time the tool is launched
7 I' O$ q8 b; \1712279 CONCEPT_HDL CONSTRAINT_MG Differential pairs are dropped from Net Classes when upreved to release 17.2-2016" X5 y0 N7 C+ o+ A$ l. G) w
1665449 CONCEPT_HDL COPY_PROJECT Copy project fails with error COPYPROJ-77- q$ H; E' @/ Z1 }7 h
1661778 CONCEPT_HDL CORE Advanced Find will not find pins with the SIG_NAME property attached
0 @( N3 F9 X p, S/ _* A; V4 R; p1666084 CONCEPT_HDL CORE All user-defined properties are not listed in the Customize columns in Variant Editor" Q/ r9 T+ D. |/ D5 R( v) F) {
1667043 CONCEPT_HDL CORE Incorrect information in cpm.log file) X1 g6 w. g8 R/ P I( N* l% ]- m
1670659 CONCEPT_HDL CORE SIGNAME text off grid when pasting copy using ctrl+v.
+ |2 I, l- w9 o+ E+ x' ^! d1697732 CONCEPT_HDL CORE Warning (SPCOCN-922): The object is being placed towards the left edge of the schematic. Ensure that the objects are pla
% `6 O" T _# j0 k1697955 CONCEPT_HDL CORE Rename Signal places sig_name at an incorrect position for an unnamed net* \( W! z( q& L$ X/ ~$ j
1711635 CONCEPT_HDL CORE The arrow keys do not work as expected in Windows mode' f4 t2 N+ v- z
1713091 CONCEPT_HDL CORE Difference in the behavior of 'Add Signal Name' in DE-HDL between releases 16.6 and 17.2
; N/ z) m% s6 Y# M1708820 CONCEPT_HDL OTHER In a board cache flow, component bodies are missing when importing another board cached flow project.9 k1 K7 e0 d2 M! R
1639928 CONSTRAINT_MGR CONCEPT_HDL The '-filterFile' argument is not recognized when cmDiffUtility is run as a command line operation1 V" A; j7 f+ @; V' A
1657048 CONSTRAINT_MGR CONCEPT_HDL Unable to navigate through the search results in the CM Reports3 X7 g3 l( a2 Z/ d( `9 Q( w+ X/ J" V
1718073 CONSTRAINT_MGR CONCEPT_HDL ECSet mapping errors on an upreved design in release 17.2: Pins in XNet and CSet do not match" r3 k" X* ^4 e* F
1717336 CONSTRAINT_MGR DATABASE Netclass members change during logic import; it's a toggle switch1 a! ~$ C0 B6 j/ s9 ?5 E
1718514 CONSTRAINT_MGR ECS_APPLY Extracted topology does not use the PINUSE overrides specified on the canvas' u& G2 E5 c1 P3 n$ s9 b
1682885 CONSTRAINT_MGR INTERACTIV Constraint Manager worksheet switching does not work correctly in Linux
; B& J+ _1 `: m$ a3 S8 s6 q1669523 CONSTRAINT_MGR OTHER Select is disabled in Constraint Manager when a command is active in PCB Editor
, l$ U2 A8 g; c+ K1670802 CONSTRAINT_MGR OTHER Selecting a list of nets using the shift key does not work in Spacing and Physical domain5 ^6 g( B- I% g$ s- w( G
1670922 CONSTRAINT_MGR OTHER Title of the Layer Remove window is Constraint Manager6 A" U0 P- v. u* f$ n
1678235 CONSTRAINT_MGR OTHER Select option grayed out in Constraint Manager if a command is active in PCB Editor* K" D" l. T" W W0 `5 B
1680917 CONSTRAINT_MGR OTHER In release 17.2, nets cannot be selected in Constraint Manager when a PCB Editor command is active' r0 _" v: ^1 M) a& M% ^ R
1691125 CONSTRAINT_MGR OTHER Highlight command no longer selects the net in CM; @1 W/ _8 f( {% L4 r; Q3 N
1703791 CONSTRAINT_MGR OTHER Cross highlighting and assigning color to nets between PCB Editor and CM does not work6 _/ v6 s" O* w* h
1649603 CONSTRAINT_MGR UI_FORMS Expand and Collapse commands do not work when multiple objects are selected: U: }" @( B( U4 y
1654931 CONSTRAINT_MGR UI_FORMS Expand, collapse only works on one of the multiple selected objects.
8 s( p# U$ S# H5 _3 [. M* u1668794 CONSTRAINT_MGR UI_FORMS Incorrect via name shown when filtering via list
+ B# F5 }3 F! E) e" e- \1678305 CONSTRAINT_MGR UI_FORMS Unable to use the CM worksheet customization (wcfx) from the CDS_SITE area# d. Q, K- L+ U2 k7 L
1679909 CONSTRAINT_MGR UI_FORMS Incorrect layer order getting saved when defining BB vias in Constraint Manager PCSet2 b: K! s6 P; E) l8 u6 Q3 j
1691906 CONSTRAINT_MGR UI_FORMS Display Issue: When you use the filters, the horizontal scroll bars are duplicated# ~" r+ X. H/ B2 E0 P) I2 x# t
1677893 ECW INTEGRATION Integrations list update is not working as per scheduled time5 _/ H4 `6 Z: K5 [3 _0 [. p
1652707 ECW METRICS Incorrect date and time displayed in mouseover tooltip on the Metric Trend chart
" K1 z' F) ^3 Z3 c1654512 ECW METRICS Incorrect date and time displayed in mouseover tooltip on the Metric Trend chart
; T) K: @: g+ E) t- J( Z1668953 ECW METRICS IE11 Swedish only: Incorrect date and time displayed in mouseover tooltip on the Metric Trend chart/ P, j2 ^8 g: S6 a1 q
1677443 ECW METRICS Queued up metric packets on Pulse server are not processed if there are any packets related to a deleted project* E2 u) f+ ]. Z- o: X
1663676 F2B PACKAGERXL Physical net name (PNN) errors in the log file
6 k# c& f- C H: H1669583 GRE DETAIL AiDT always fails push when there is a connect shape attached to the cline being tuned5 R! F$ J% C6 E; Q4 D- C
1686350 INSTALLATION SPB InstallDiagnose fails to repair some errors3 G @7 w x1 }4 j5 U
1672369 PCB_LIBRARIAN EXPLORER Cannot create a New library build in Library Explorer.
7 R* l/ y" ?* n' j/ ^1631034 PSPICE ENVIRONMENT When simulating the design in release 17.2, Capture crashes but works with release 16.6
( q* c7 t) `- L4 |$ w1648284 PSPICE ENVIRONMENT PSpice project crashes when a design is opened in release 17.2 k8 u1 R v. K
1663336 PSPICE MODELEDITOR Ibis translation not supporting paths with spaces E( W7 H$ m9 R; F" d- |4 S
1679376 SIG_EXPLORER OTHER Topology created in OrCAD PCB SI license cannot be reopened with the same license- ?' y& |- p) E( \
1666484 SIP_LAYOUT CROSS_SECTION On converting a design from release 16.6 to release 17.2, a Dielectric thickness of ‘0.2032’ is added to another layer.5 n4 Q# G1 Y9 I3 G
1687988 SIP_LAYOUT DIE_GENERATOR 'compose die from geometry' does not retain the user-defined padstack name7 _$ v* W; s8 {: x! S
1715016 SIP_LAYOUT DIE_GENERATOR Using Die Text-In wizard to replace a die reconnects wire bonds to the wrong die in stack-up0 H3 j" K9 M/ x2 R2 J5 J! P$ B
1620601 SIP_LAYOUT MANUFACTURING Need the ability to create LINES with round end caps in the same way as the LINES appear in the database
9 a7 P7 p& E v& V/ y4 F$ G+ K* I1705963 SIP_LAYOUT PADSTACK_EDIT Pad Designer: "None" changing spontaneously into "Circle 0.000" in a pad stack definition and unable to save h% y# V9 G; P0 k3 z
1713767 SIP_LAYOUT REPORTS Reports in release 17.2 for the Verilog Port Name are adding incorrect data that was not found in release 16.6
7 h; l; @, S5 o4 J1696218 SIP_LAYOUT SKILL SiP Layout crashes on reassigning nets
# S* |) c. g1 J- J0 y1695885 SIP_LAYOUT UI_GENERAL Visibility Tab check box: unchecked "All" disables access to "Shp" check box
6 \' Y; s4 f2 m7 W3 S! G, y1639838 SIP_RF DIEEXPORT Enhance the error message, SIP-1507, to include that overlapping pins within tolerance are included during die export
3 I" T/ d7 _2 _, S! O1653894 SIP_RF DIEEXPORT Redundant error message for die export, when view name is other than "layout"1 k0 w' l: b+ Y6 M6 H4 h
1681332 SIP_RF OTHER Running die export causes Virtuoso to crash
+ B! z9 \7 z J7 A3 M8 {1679336 SPECCTRA LICENSING Min/Max Propagation Delay cannot be routed by PCB Router using OrCAD PCB Designer Professional# _, W6 u! P7 O3 C8 S( E- B
7 {; l. o$ }' @' D
% C7 l- C8 s/ ?+ g8 ?Fixed CCRs: SPB 17.2 HF015
- T9 e- B5 W, ]! o03-16-2017
5 F3 ~; J- ^4 p8 R========================================================================================================================================================
; v" C* z# F7 T7 t. I1 `CCRID Product ProductLevel2 Title
- [! ?) w5 Y( r8 P# o8 _- C- M2 |( a========================================================================================================================================================" Q+ a- B. ?- d+ b/ i
1653366 ALLEGRO_EDITOR INTERFACES Unable to attach step model to symbol2 q9 {/ O% F4 r; Y' V9 l, Q, I% S
1671760 ALLEGRO_EDITOR INTERFACES Step package mapping window unable to display step model
0 z+ m0 E- { I8 L9 m# h' t) e1706879 ALLEGRO_EDITOR MANUFACT Trace gets moved to dielectric layer after using the Gloss function' R* T; J/ ~$ K5 b
1708685 ALLEGRO_EDITOR MANUFACT Incomplete ncdrill holes data in drl file# {' Z M- K* ]1 w* |0 F% D) w
1712057 ALLEGRO_EDITOR PAD_EDITOR Changing text size and restarting Padstack Editor results in incorrectly scaled forms& V' G0 b3 ?8 ?2 P1 M9 a# }
1709335 ALLEGRO_EDITOR SCHEM_FTB Cannot import netlist from attached design
7 Z$ ?' B! y5 @# r" u( y8 [! _1687329 ALLEGRO_EDITOR SHAPE Shape is not voiding uniformly when component is rotated in 30 degrees k/ c, z, y Y0 T7 ^8 ~
1698539 ALLEGRO_EDITOR SHAPE A thin shape is left when dv_fixfullcontact is enabled.- h5 m. ^/ C/ o+ N. }$ U
1620210 ALLEGRO_EDITOR UI_GENERAL Need to run PCB Editor from both 17.2-2016 and 16.6 releases simultaneously' T3 x" G" ]: E& M
1687819 ALLEGRO_EDITOR UI_GENERAL Change in Region and Language settings of Windows impacts decimal character in Padstack Editor! ]+ u0 S& l4 O m: q7 m9 g* U
1699326 ALLEGRO_EDITOR UI_GENERAL Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not
" D9 N0 w; L7 ~1711341 ALLEGRO_EDITOR UI_GENERAL Incorrect pad size in Padstack Editor when the German regional settings are used/ D% B+ |8 J* J5 w
1712496 ALLEGRO_EDITOR UI_GENERAL Padstack Editor shows incorrect values when using comma and 3 decimal places- `, y: [2 t" e" K8 @
1714744 ALLEGRO_EDITOR UI_GENERAL Using comma instead of dot as integer separator results in incorrect diameter value& {2 r$ H) G# w
1715714 ALLEGRO_EDITOR UI_GENERAL If the 'Decimal places' field is set to 3, values in PAD Designer change automatically: h" Q( q! ?+ c/ O# m, h( h m7 z
1713292 APD WIREBOND Allegro Package Designer crashes when adding wire to a die pad8 m" B; Z$ M$ M: j/ q
1710973 ASDA PACKAGER Unable to export Allegro SDA project to PCB Layout
9 ?; ^' u6 H$ R6 ^9 Y6 S* ^$ ~/ \1698697 CONCEPT_HDL COPY_PROJECT Copy project corrupts the .dcf file
; o7 Q( m0 i' S' a# h/ j6 z, {# e1705401 CONCEPT_HDL CORE Alignment issues while pasting signal names in 16.6 Hotfix 0847 D ~. ?( \( u8 W, ~( T+ A! W
1707116 CONCEPT_HDL CORE SIG_NAME is placed on non-grid position E- l& A: P6 ~1 z j, W
1710486 CONCEPT_HDL CORE Rename Signal places sig_name at an incorrect position for an unnamed net
`( ^& p. {$ ?6 A1667786 CONSTRAINT_MGR XNET_DIFFPAIR Parts with NO_XNET_CONNECTION getting extracted into SigXplorer; v' x6 \$ ?% w" V
1709508 SIG_INTEGRITY REPORTS Allegro Sigrity SI crashes when running a reflection simulation
& E# w2 N# C: n* w& c1710097 SIP_LAYOUT DIE_STACK_EDI The IY option of the 'move and stretch wire' command moves the die to incorrect coordinates3 M& D4 W1 R( O/ W0 _
1712964 SIP_LAYOUT SYMBOL SiP Layout crashes when using Renumber Pins in Symbol Edit application mode* f# P$ m, q+ O2 }1 c. D2 q8 A
9 K* B/ ?3 U U% l$ T
1 v! L. t, d; S
Fixed CCRs: SPB 17.2 HF0148 s6 h- C, ~+ ?/ E) T: A( U
03-4-2017
3 @: m0 s5 K* O$ [0 e- T7 A========================================================================================================================================================
+ ~% j0 s3 w% U" HCCRID Product ProductLevel2 Title
/ r$ c% _. j B========================================================================================================================================================; A; ^9 X, |6 M+ m! {
1691828 ADW COMPONENT_BRO Part Information Manager displays incorrect data related to attributes on relationships
! C# r) o# J4 m- U& O9 {7 @9 X1700963 ALLEGRO_EDITOR DATABASE Running the 'slide' command results in the cline segment losing connectivity% S( z' H: \ v) i1 b9 y. _# ~2 r
1685502 ALLEGRO_EDITOR INTERFACES The Export - PDF command fails to export the TOP etch subclass with error code SPMHGE-2685 u% ]/ Q; z, ?- F1 T. J; Q6 {
1644643 ALLEGRO_EDITOR MANUFACT The NC drill legend does not match the drill customization data
1 ^- s4 ^4 l; O/ m1700557 ALLEGRO_EDITOR MANUFACT DXF output does not contain drill figure data( u9 r5 B! o9 Y& f. b
1660252 ALLEGRO_EDITOR NC NC Drill file generated with errors6 e/ g, o2 b: F% V% B- ?/ K; }
1677775 ALLEGRO_EDITOR NC Merging of drills not retained in database.
$ b' ~8 ^2 i: w. C" D/ B1701554 ALLEGRO_EDITOR SHAPE Shape spacing clearance is not updated unless the shape vertex is deleted9 r8 B4 H5 V$ d$ w2 P
1704669 ALLEGRO_EDITOR SHAPE Route Keepin is not getting created at a specific location
3 r; \. f' i0 \+ H" t- h" s" n1685995 ALLEGRO_EDITOR SKILL All film sequence numbers are returned as 0 when using the SKILL function axlGetParam3 a' m% V) S& _9 |
1621336 ALLEGRO_EDITOR UI_GENERAL Changing the color visibility does not refresh the screen color immediately
$ b7 P. @- T! i }+ U" n1668817 ALLEGRO_EDITOR UI_GENERAL Changing the visibility or the color on the canvas in release 17.2-2016 takes longer than release 16.6
5 E; n0 Q& X4 g+ K1671268 ALLEGRO_EDITOR UI_GENERAL Visibility Window: There is a noticeable lag when enabling etch, via, and pin on a specific layer one by one' _) E$ `# Z1 C
1690691 ALLEGRO_EDITOR UI_GENERAL Reports not generating if the 'allegro_html_qt' environment variable is disabled
. p p# G7 J+ @( j7 x8 {1709903 ALLEGRO_EDITOR UI_GENERAL Toggling layer visibility does not change the display until the mouse pointer is moved
: d; N# f# C; ~: I) J1647596 APD EXPORT_DATA Allegro Package Designer crashes when trying to export board-level components
1 z* i \+ L4 l4 u9 R" {% q) C1688035 APD OTHER Significant difference seen in the percentage of metal between the Metal Usage reports of positive and negative layers
, {- k1 `, p5 Y# V$ H9 w. Y! M7 T# ?1690777 CONCEPT_HDL CHECKPLUS Rules Checker returns an error when the value of the PACK_TYPE property is in lowercase
9 M% ?4 i2 n. e4 d1695987 CONCEPT_HDL CORE $PN placement in DE-HDL during part development is not following mouse placement+ \2 ^9 n8 m; z" ^
1700873 CONCEPT_HDL CORE With duplicate part table files, running the Assign Power Pins command crashes DE-HDL without any message
; n" p2 g: } S6 O1702703 CONCEPT_HDL CORE Location of $PN in DE-HDL Symbol Editor is not as precise as it was in 17.2 Hotfix 0112 f9 k* N4 X8 ^ Y
1705999 CONCEPT_HDL CORE Signal naming is not working correctly in SPB 17.2/ E" B W/ W1 R3 J) D! {
1677489 CONCEPT_HDL CREFER CRefer points to incorrect page numbers when there are page mismatches in the logical and physical page numbers) X8 b& I2 c! J6 N0 w& ~
1698259 CONSTRAINT_MGR CONCEPT_HDL Unstable $LOCATION property in release 17.2-2016) e2 ~. a! F9 I
1702537 CONSTRAINT_MGR CONCEPT_HDL ECSet mapping errors reported after removing the signal models on an upreved design: f( `' _2 r- i# e# z2 P
1703981 CONSTRAINT_MGR TECHFILE Importing a technology file (.tcf) results in packaging errors
9 I# r6 R; R* G O5 z* d8 y: U; v1673115 ECW INTEGRATION Import from external data sources (Integrations) truncates input values to 128 characters# u) g4 z& W. m7 l" R8 s# M+ V- ]
1699395 FSP FPGA_SUPPORT Selecting a QSF part name in the FPGA Properties window crashes FSP
0 {8 K1 @2 Z* f! `+ \( X: _1704353 INSTALLATION DOWNLOAD_MGR Selecting 'View' in Download Manager results in error, 'Object Reference not set to an instance of an object'
$ P% T. ^$ w- c2 N1705265 INSTALLATION DOWNLOAD_MGR Problem installing OrCAD Library Builder from Download Manager
7 G( _# z4 G6 j9 q$ U3 P1646635 PDN_ANALYSIS PCB_PI PCB Editor uses 'powerdc.exe' to launch PowerDC instead of the 'powerdc' script2 @4 f! e" F. D$ m1 `% ?, O
' h W$ m: ~- C* ?
1 f' b5 L, X" g4 B1 r' O
Fixed CCRs: SPB 17.2 HF0137 v& }' p- `7 B# c, m) `! v
02-17-2017
) K+ W. V* H- j2 Z========================================================================================================================================================: S% a; g! F" Z: y
CCRID Product ProductLevel2 Title
! @" j$ ~3 I$ @, ~# I3 n========================================================================================================================================================! H4 \/ Z: z1 a1 j+ w
1567741 ADW COMPONENT_BRO The PPL_list never gets read when using a saveconf.ctr located in the global site.cpm- ^5 K1 }+ i/ p
1697109 ALLEGRO_EDITOR ARTWORK Artwork not showing padstacks for the soldermask layer: ? O1 }) E# M8 L
1682297 ALLEGRO_EDITOR DATABASE Derived padstack and associated padshapes not updated when design is upreved for compatibility with the current version
" O( {$ C* V5 v1 `. {1697309 ALLEGRO_EDITOR DATABASE PCB Editor 17.2 uprev changes NC pins from non-plated to plated
& X. G; P; p0 C8 r3 e' W) ^1698624 ALLEGRO_EDITOR DATABASE Opening 16.6 board in 17.2 converts non-plated holes to plated
2 B# K ]* z( `: Z. k8 | i1697092 ALLEGRO_EDITOR OTHER axlDBViaStack crashes PCB Editor session and corrupts the board
3 e- P4 V1 a8 y" z: { j1687819 ALLEGRO_EDITOR UI_GENERAL Change in Region and Language settings of Windows impacts decimal character in Padstack Editor4 W6 O7 r" i, X1 X3 g6 t
1696637 ALLEGRO_EDITOR UI_GENERAL Padstack Editor uses Region and Language settings for the decimal symbol
" Q6 b _4 l+ |& A& l1699326 ALLEGRO_EDITOR UI_GENERAL Padstack Editor follows the geographical area rules set in the Control Panel while PCB Editor does not( G/ r; _' ^3 w4 {4 W
1616138 ALTM_TRANSLATOR PCB_EDITOR Board file imported from third-party tool to PCB Editor has the shapes but not the components2 e- s! y4 ]& n/ j
1666020 ALTM_TRANSLATOR PCB_EDITOR Board converted from a third-party tool to PCB Editor has missing components( V2 b1 L( b$ b
1690448 CAPTURE CORRUPT_DESIG Corrupt design: nets in this design are not displayed when running Edit - Browse - Nets
: U% C4 a A q- O1690455 CAPTURE CORRUPT_DESIG Corrupt design: all the nets in this design are not displayed when running Edit - Browse - Nets
" N% w3 n* G" [9 U; l$ w' E1684180 CONCEPT_HDL CORE Message should indicate that the user needs to reload the design after setting SET STICKY_OFF- |( M6 @" H4 S! b/ `
1695987 CONCEPT_HDL CORE $PN placement in DE-HDL during part development is not following mouse placement$ c% X1 o4 r$ G0 X# I
1688287 CONSTRAINT_MGR DATABASE PCB Editor crashing while adding a net to a net group.9 P* B: U8 {! Z e5 E
1675013 ORBITIO ALLEGRO_SIP_I Failed to import brd file
: c, j+ V2 }. _# Z. L# v& B: j' @1698968 SIP_LAYOUT 3D_VIEWER 3D viewer shows keepin and not design outline.$ m, g8 s3 m% Q9 u* f+ f
1699884 SIP_LAYOUT ASSY_RULE_CHE SiP Layout crashes on using Assembly Rules Checker
; Y; J) f# Y* U* b$ L, Q8 u1 }$ T1689969 SIP_LAYOUT DIE_EDITOR SiP Layout crashes when moving dies using relative coordinates/ K+ }; J ]8 J4 B
1696239 SIP_LAYOUT DIE_EDITOR When using the Die-stack Editor to move and stretch wires, SiP Layout crashes
! _$ q( x5 l2 g6 X+ F3 P8 H1695372 SIP_LAYOUT REPORTS Running the Metal Usage reports fails on the Primary side., A) P. p& i1 s2 N6 r+ r
+ }6 u' z0 ^- r: X F: d+ G3 x9 E1 u; J: ^% K# ~
Fixed CCRs: SPB 17.2 HF0126 ^+ n4 d+ A9 Q5 Z# X
02-3-2017) c, S9 _& j- x* G! k0 Z( {5 h
===================================================================================================================================; d2 t! A) a4 B- K
CCRID PRODUCT PRODUCTLEVEL2 TITLE
1 u$ H/ @$ v, j4 J2 P6 C7 _===================================================================================================================================
+ K& M H0 H" f8 C. y; p% e1659641 ADW FLOW_MGR Documentation Editor does not invoke when a .brd file is opened from EDM Flow Manager
; q; y4 i" _7 ?5 N! r1 E2 b7 F1661632 CONCEPT_HDL OTHER Page skipped in DE-HDL when navigating using the Page Up and Page Down keys
4 C+ ]+ x8 l# m" n1668325 ALLEGRO_EDITOR SHAPE Updating shapes to smooth creates erratic voids. j. ]$ X8 D7 v- R4 I. f* i" y
1670082 CONSTRAINT_MGR ANALYSIS Inconsistency in Constraint Analysis Modes - Electrical in OrCAD PCB Designer Professional 17.2! n( t& C) B% ?5 l+ [
1674231 ECW METRICS Re-upload for local metric packets that failed on first attempt is not working when Pulse server name contains dots( w; {9 [- S1 v6 M( f& b
1674338 APD SHAPE Shape is not clearing slivers that are smaller than the 'Minimum aperture for gap width' of '18 um'5 A6 s; a! r! B1 W6 O! R) t; C
1675677 ADW DBEDITOR DBeditor Issue-Searching by using the Properties method
2 t$ s7 Z% W H# r* V5 j1677489 CONCEPT_HDL CREFER CRefer points to incorrect page numbers when there are page mismatches in the logical and physical page numbers! d1 @8 T6 S$ ?" \! S2 g; g
1679351 ALLEGRO_EDITOR REPORTS Missing Fillets Report is not showing missing fillets on the bottom layer
8 c; f7 R0 [8 a1 q' F, h" u3 Z1681002 ALLEGRO_EDITOR OTHER 17.2 STEP output fails to produce an output similar to 16.68 E1 @" y1 x" ?0 d/ ~+ m' W- h2 d
1682287 ALLEGRO_EDITOR EDIT_ETCH Auto-interactive Delay tune (AiDT) rips lines that have been routed1 Y- _7 G/ D; Z( k( C% K& k
1682900 ALLEGRO_EDITOR PLACEMENT Moving a symbol by snapping to segment vertex with 17.2 Hotfix 009 crashes PCB Editor
! J& }- y" }/ J: ~7 g1684117 CONCEPT_HDL CONSTRAINT_MGR Property deleted from Constraint Manager is not getting updated in the DE-HDL canvas% p( ]. U% x# x. _/ }: ~: ?
1686803 ALLEGRO_EDITOR INTERFACES PCB Editor crashes if the 'ipc2581_group_drills' variable is set.6 q. {; N3 K# n
1687816 ALLEGRO_EDITOR PLOTTING Export PDF Vector text option does not work- S. J7 [0 M: V# r" f! y4 ]& }
1688287 CONSTRAINT_MGR DATABASE PCB Editor crashing while adding a net to a net group.
# q! e6 [* j, m* H1689881 ALLEGRO_EDITOR DFA Record and replay script for loading DFA spreadsheet not working
" ~ X( e3 q- e9 P1690958 ALLEGRO_EDITOR SKILL SKILL command axlDBDelLock is not working as explained in the documentation
7 K# J3 @8 \9 ]6 Y0 G6 t1692166 APD DATABASE DB Doctor returns 'ERROR(SPMHDB-252): A corrupt database pointer was detected' for a specific design, X) y2 M, l) H) F9 h) }
1693431 ALLEGRO_EDITOR SKILL Running axlXSectionModify and axlXSectionSet results in warnings and corrupts multi-zone cross-section
: e3 B" Y' h, n+ i# Q/ `1693719 ALLEGRO_EDITOR MANUFACT Incorrect suppressed holes information in the drill file created0 U) f: B* a# c
1693846 ALLEGRO_EDITOR MANUFACT PCB Editor crashes when running the gloss command( V3 q3 y- E% G: }+ o
1694151 CONCEPT_HDL CORE Rename Signal for unnamed net added the sig_name at the incorrect position with small text size.
. w5 Z6 F) Q# Z7 |' f! `6 a1694867 ALLEGRO_EDITOR SHAPE Void is deleted by the shape merge command. L* b3 S" @; W: i; {" T
1695131 ALLEGRO_EDITOR SKILL PCB Editor crashes when using the axlSpreadsheetDefineCell SKILL function- Y5 t0 A9 x' ^; ]
; e7 n; g2 G- t' P) u e% Q
) U& H# }( W' _0 [- Z6 f! `Fixed CCRs: SPB 17.2 HF011
0 i+ L' g( ?, W' M3 f. q% [! R01-20-2017
9 y0 ^& e: X7 ?===================================================================================================================================" c4 I" k4 Z! Y( \0 [& b+ G
CCRID PRODUCT PRODUCTLEVEL2 TITLE
. k9 Z5 {" C- W8 V6 w===================================================================================================================================! @! n8 z- ~* D& B7 ~) Y
1618986 CONCEPT_HDL CORE Information required about the DONT_FORCE_ORIGIN_ONGRID directive( s1 R+ V7 P4 B. A5 r
1629696 PSPICE PROBE After successfully exporting traces to csv, PSpice crashes on a subsequent attempt to export traces
+ m2 c- g. L0 ]9 B1667213 CAPTURE NETLIST_ALLEGRO Tools - Create Netlist stops responding on Windows10
6 n, S7 X4 ?: T9 U4 w& Z1667599 APD OTHER Wire Bond operations taking longer than expected to complete
, K) ^/ ?7 _" }1667678 MODEL_EDITOR PARSE Signal model assignment creates ESpice models that do not pass Model Integrity checks! B5 b y6 l; q) S) C, S. F! B- W
1670120 ALLEGRO_EDITOR UI_GENERAL In 17.2, the Static Phase meter shows up in the middle of the screen instead of the lower right corner
P" r e! H$ Y3 h0 D) R1670927 ALLEGRO_EDITOR DRAFTING Using zcopy to create a Route Keepin results in database errors3 g. ~7 T: q3 w, S5 x
1675359 ALLEGRO_EDITOR ARTWORK Subclass ETCH/WIRE is added to artwork definition though the visibility of 'ALL Layers' is turned off& o! {5 Z- k( S/ @ a$ V7 E6 h: Z
1675619 ALLEGRO_EDITOR MANUFACT Differences observed in IPC-D-356A between releases 16.6 and 17.26 M" ?+ b+ g. ?5 X5 r5 k- V0 P
1676161 ADW FLOW_MGR Opening a project in SPB 17.2 flags the 'Operation load JNI code failed' error
% ~+ I# V/ ~1 _" T1677405 CONCEPT_HDL OTHER When moving a wire with a dot, the dot is not removed directly* f7 J! g X( C+ S
1678061 PSPICE SLPS Simulating an SLPS co-simulation with a Fixed-step solver with a value smaller than 1E-4 results in a crash% d; ~ h: o* Y4 L
1679347 PSPICE SLPS SLPS crashes when co-simulating without opening OrCAD Capture or PSpice
. a% x# e N9 U# B, V) v4 L3 ~1 A( O1680113 ALLEGRO_EDITOR SHAPE Irregular void created on dynamic shapes
+ s9 S7 H5 R/ Q! q) Z2 A1680802 ALLEGRO_EDITOR DATABASE A 16.3 database locked with disabled export of design data should be view only in 16.6! {' S5 B% `" s4 a' |; l! j
1681129 ALLEGRO_EDITOR DATABASE Match Groups in the DE-HDL design are not getting transferred to the board file
- t( ^3 j/ i# Z$ L& P1681514 ALLEGRO_EDITOR UI_GENERAL Opening the Dynamic Shapes State report hangs PCB Editor in 17.2 Hotfix 009
/ w7 f8 d* q2 w! S6 X1681727 CAPTURE NETGROUPS In 17.2, Capture crashes when closing a design that has assigned Netgroups
) N& y8 f2 U. M, u# [1 _1682297 ALLEGRO_EDITOR DATABASE Derived padstack and associated padshapes not updated when design is upreved for compatibility with the current version
/ Q# c4 \( o6 V1 ^1 [4 G4 f3 S1682447 CONSTRAINT_MGR CONCEPT_HDL Extraction issue on differential pairs in the given design
8 _2 m0 e& N8 o" O+ Y8 A1 O1682454 CONSTRAINT_MGR CONCEPT_HDL Design with NO_XNET_CONNECTION property on parts is exported to PCB Editor; many other components get the property9 \3 d0 }9 D" S9 t+ R
1682469 CONSTRAINT_MGR CONCEPT_HDL Creating a CSet from an existing CSet leads to invalid CSet names in Constraint Manager connected to DE-HDL |: C, w: N% P4 S' E0 \
1683919 ECW TDO-SHAREPOINT Site Minder integration for login from TDA not working after SSL certificate update
! f: M4 n$ o. ~7 F$ A1684111 ALLEGRO_EDITOR SHAPE Dynamic Shape not voiding overlapped static shape' u8 E& A$ Q. i/ U h. L" f; Y
1684508 ALLEGRO_EDITOR AUTOVOID Allegro PCB Editor stops responding when deleting a via8 P. O3 U- k/ T3 k) s. r* z% Z8 r! y3 Y
1685540 ALLEGRO_EDITOR OTHER If text is attached to an object, the object is also printed in the PDF! H: c1 q& X: e. d. c. E9 @3 o5 c
1685810 ALLEGRO_EDITOR PAD_EDITOR In 17.2, Padstack Editor does not save adjacent layer information for BOTTOM pads
+ d2 ?9 F4 a/ _/ @3 o1685986 ALLEGRO_EDITOR PADS_IN PADS Translator-generated output shows incorrect unit for the soldermask oversize option
0 M7 ~' j- `4 F: I% c4 b6 S, S5 H1686127 ALLEGRO_EDITOR SHAPE The void of shape missed in artwork.
) u: P3 h- l) P% H" \. G; Y% ~1686791 ALLEGRO_EDITOR OTHER Searchable property unavailable on bottom layer pins in the generated PDF% R9 ~. T) O% i3 t2 _% D
; E+ ]- p1 Q& w* W& a4 C7 B8 F7 W. g9 }9 d( B
Fixed CCRs: SPB 17.2 HF010, H0 V# Q6 {1 o
01-6-2017
$ z4 e, \ p* Z: p' m1 {& O===================================================================================================================================" A) Q, ^6 _# q6 [' q% V2 k
CCRID PRODUCT PRODUCTLEVEL2 TITLE, C2 D0 V. t3 j0 `2 _8 r
===================================================================================================================================) K J- Z' E; @8 e8 k; `
1524700 F2B DESIGNVARI Variant file cannot be loaded
5 W0 r- o* Q, Y+ V1597787 CONCEPT_HDL MARKERS Save As in Marker dialog causes DE-HDL to crash4 `- V9 R# t8 v7 o3 l& ?5 N
1599843 CONCEPT_HDL INTERFACE_DESIGN Moving NG causes extra elements added to it to move
" p( l- y5 Z3 n6 h1620017 F2B PACKAGERXL Packager Fails with ERROR(SPCOPK-1053) when $PART_NUMBER property for components has a value
6 S5 n( I& {. O+ s( f. J, ^1632977 CONCEPT_HDL INTERFACE_DESIGN Connectivity error when moving NG members% G* T5 ]/ i, Q2 M- e
1635941 ALLEGRO_EDITOR INTERFACES Shape created by IPC 2581 for negative film is not same as the shape on board7 J2 @7 U6 B; x" S& A% ^# c6 ~
1656357 CONCEPT_HDL CORE Pasting a signal name across pages causes the name to overlap with the wire segment
' n( V: R1 \! r! a& l) T! k" v1657346 CONCEPT_HDL PDF Wire Pattern set to two-dot chain line in a schematic appears as a solid line in the PDF output
+ p, Y" ^# w. h* ?9 A! ]( r6 h/ M( `7 D1658048 ALLEGRO_EDITOR COLOR color_lastgroup is not working in SPB 17.2
* \; ]4 r( h* s" f9 ~$ n1658874 CONCEPT_HDL CORE 'Insert (n) Pages' command does not work when the CONFIRM_WRITE directive is ON6 I" Z5 v. u. H6 s
1659030 RF_PCB LIBRARY Offset is not calculated from the center if using negative values for input pins when placing MSOP symbols; E2 R! ^! D* y
1659097 CONCEPT_HDL CORE Mouse stroke fails to be enabled on startup with left mouse button (LMB)
/ C* _8 U* r) h: a* E' v1659532 CONCEPT_HDL CORE About Import Design command with the CONFIRM_WRITE directive; `0 n6 E$ C8 M( C
1659929 CONSTRAINT_MGR UI_FORMS Using wildcards in filename for Import Constraints does not work in 17.2
: }: L9 U0 D$ ~: e9 I7 R- ^8 G0 e1 {1660200 ALLEGRO_EDITOR UI_GENERAL Move by Sym Pin # edit box is obfuscated
1 m0 X8 x0 f: `( C5 P# K1662821 ALLEGRO_EDITOR OTHER Cross section chart does not show stack vias in 17.2
2 t# F6 s/ Z% x1663641 CONCEPT_HDL COPY_PROJECT File - Copy Project in Project Manager creates two designs if there are dashes in the design name
' x5 s9 j0 v4 X* @1665652 ALLEGRO_EDITOR SHAPE Critical fillet and shape issues in 17.21 P) M( [5 J, B$ c
1665918 CONCEPT_HDL CHECKPLUS Error (100) Program Internal Error 'Create_flat_node' with checkplus run
; s# H) t& W5 T+ c# p- C3 f: q1667056 ASI_PI GUI Power Feasibility Editor does not list capacitors connected to selected nets/parts' X6 r0 m: f# [8 D" G( N1 m" j
1668137 ALLEGRO_EDITOR SCRIPTS PCB Editor crashing when running Script Replay
. ^* a* z7 \$ A0 Y3 X" W* B1669651 CONCEPT_HDL CREFER CreferHDL values are invisible& y9 G8 U& O" ~" Q; J; N
1669707 CONCEPT_HDL CORE Pin numbers not visible on the canvas after replacing a part with the same symbol but a different part property
% i9 l, A9 m* r; N9 J3 f$ n4 q1670339 ALLEGRO_EDITOR OTHER Small shapes defined on the mechanical symbol Board Geometry - Outline are not converted to the Cutout subclass.
2 u+ L5 w, ^" A' g# i3 L1670564 ALLEGRO_EDITOR MANUFACT Exported Gerber file cannot be imported in brd4 f8 y5 l0 F+ o; q: Y1 K
1670687 ALLEGRO_EDITOR NC nclegend.log reports missing columns which are present in the NC Legend
) h9 i4 b' n. H! `, x9 d. J6 r1670811 PSPICE AA_MC AA MC Plot settings options6 ~" I9 s: r: j! }0 r0 K* \
1671428 ALLEGRO_EDITOR UI_FORMS Display origin checkbox position changes in Step Mapping dialog0 f9 n. y {6 r9 b( B( }% Y
1671728 CONCEPT_HDL CORE Option requested to reload preferred_projects.txt without re-opening DE-HDL
: j& g0 H U# \+ R1671901 ALLEGRO_EDITOR UI_GENERAL Toolbar and menus are locked or greyed out
q. C$ {( l8 x! P) x a& f$ B1672477 ALLEGRO_EDITOR DRC_CONSTR DRC generated by Dynamic fillets
1 j' D! @* \% \. H1673499 ALLEGRO_EDITOR DATABASE Drill table title issues of backdrill designs in 17.2+ c; Q. r) |' }) Y) d
1673681 ALLEGRO_EDITOR UI_GENERAL F1 for Help not working in PCB Editor 17.2
5 L Z0 v0 @- V! m7 g1675499 ALLEGRO_EDITOR DATABASE Running the Gloss command causes PCB Editor to crash...- @, y* }2 Q1 t4 f/ a, @
1676480 ALLEGRO_EDITOR MANUFACT Creating Variant Assy_Bot Drawing showing Variant Assy Top Drawing/ x Q& H3 q# _, x: p) g
1677431 ALLEGRO_EDITOR DATABASE Get ERROR(SPMHA1-141): Invalid sector row. Contact cadence customer support when opening DRA File
6 C% [8 h e# O4 M1677651 CONSTRAINT_MGR CONCEPT_HDL DE-HDL crash on design after successful packaging
4 u, D6 C$ i9 M8 k& N/ g& I3 J1677672 CONCEPT_HDL CORE Whitespaces in URL links are not resolved correctly on Linux with Firefox/ ~# ]( {( Q6 m
1680837 ALLEGRO_EDITOR SHAPE Updating the shape makes the shape disconnect from Thru pins of same net
k% o$ h6 N0 ^0 `; z# ]1681059 ALLEGRO_EDITOR SHAPE Shape Voiding using DV_SQUARECORNERS environmental variable does not always produce voids with square corners.
4 x9 {3 a. d6 U; R' Z0 @/ P3 V1682312 SIG_INTEGRITY LICENSING Allegro Sigrity SI/PI Product Choices window is blank after installing 17.2-s009 hotfix
c" J; q( o- v- H ?( u0 `
m' B/ U8 P$ _& ^6 t9 o% _! s! S" u: {0 x: d1 K
Fixed CCRs: SPB 17.2 HF009
6 v4 X( Y$ L* a% @ a, I, h9 _( M12-8-2016 ! F, _9 n9 l: ]1 D4 g! b
===================================================================================================================================
6 t9 ` R! q7 w5 d: DCCRID PRODUCT PRODUCTLEVEL2 TITLE% \5 A7 d: X/ {% b5 b
===================================================================================================================================# P/ M4 X6 V6 V, u
1212577 PSPICE MODELEDITOR IBIS translation fails without any information in log file4 U5 r0 l) e. T, m- ]& @
1311687 PSPICE MODELEDITOR Timeout error while translating IBIS model
) M, e% n3 L0 k. W1327174 PSPICE MODELEDITOR Log file should list error details during IBIS Translation8 j+ M( M+ F6 j1 Y( {7 j
1499665 ALLEGRO_EDITOR INTERACTIV Offset Move depends on move setting.
) Z5 @, p/ B+ M# Y& W& x1516093 ALLEGRO_EDITOR PADS_IN Pads library translator does not translate slot orientation
5 c9 l5 g; o4 J" S1565795 ALLEGRO_EDITOR UI_GENERAL Search does not work in the Defined Variables window [7 ]- V i1 ^$ ?
1568817 ALLEGRO_EDITOR UI_GENERAL Padstack editor not accepting comma as decimal separator with system locale set as LANG ru_RU.UTF-8
0 A, H4 L6 U% [8 c% ]3 }8 k. `; f) F. D1569272 ALLEGRO_EDITOR PLACEMENT Get the error message 'E- (SPMHDB-394): Placement cannot be completed ... 'after creating Place Replicate circuit$ t! T, J2 y& s& |
1577379 CONCEPT_HDL CORE Packager-XL gives different results when run from DE-HDL and ADW Flow Manager
& t) K. n7 Y- H8 R' e# r7 u2 h+ b1578523 ALLEGRO_EDITOR PAD_EDITOR Library Padstack Browser does not refresh preview
# J& s! ]2 b9 k1578533 ALLEGRO_EDITOR PAD_EDITOR New Padstack Editor does not automatically update the geometry
* ^! N! A4 q* a5 m$ g1581129 CONSTRAINT_MGR UI_FORMS Unable to dock the Electrical worksheet in Constraint Manager
+ B6 ^, G t6 N% H1582103 ALLEGRO_EDITOR PADS_IN PADS Library Import creates additional filled shape not present in source data: s/ S @" J# u2 j4 {
1591027 ADW LIBDISTRIBUTION Library Distribution redistributes previously distributed models0 q4 g6 l2 B, b' O
1592026 CIS VIEW_DATABASE_PA View database part does not work from schematic pages of an externally referenced design- F( a& \: m- J4 f6 z9 I
1593389 CAPTURE GEN_BOM Include files in Tools - BOM not working
7 y. ]9 K+ f5 R1593404 SIP_LAYOUT EDIT_ETCH Slide command moves via toward the object5 [( q$ c; u) |9 F0 m+ ]
1595872 CIS PART_MANAGER Capture CIS Part Manager PCB Footprint update case-sensitivity issue
4 r& ~2 k: X6 f0 C+ b+ |1596955 ALLEGRO_EDITOR EDIT_ETCH Scribble mode is not working as per expectation.
/ X; Q( v( C- h$ |% j6 c8 q. n0 K2 Q! n1600936 ALLEGRO_EDITOR INTERACTIV Pin DataTips differ between 16.6 and 17.2
: l6 Y6 L0 \, n! k4 `% k+ ^% x1605961 ALLEGRO_EDITOR COLOR Wildcards not working in the Filter Nets field of the Color Dialog window
" s# f3 k- R0 h1606392 ALLEGRO_EDITOR PLACEMENT Filmmask not shown when component is attached to cursor
. A/ B# E& m$ |1607016 ADW TDA TDO crashes after LRM update during check-in hierarchy2 W& v/ @/ L; [3 P" I+ S6 n
1608059 CONCEPT_HDL CREFER Removing crefs from top-level design also removes .csb files from lower-level blocks
) k3 M6 {' e% m/ Y% h* `1608278 CAPTURE OTHER Crystal Reports: User is prompted for ODBC password to create a BOM report3 O) A( H* \8 q
1610377 CAPTURE PROPERTY_EDITOR Discrepancies between the NET_SPACING_TYPE property (or any other property) text and the actual property9 s9 R$ A" [, k# [/ F4 ]
1610456 ALLEGRO_EDITOR DATABASE Strip design and selecting user defined subclasses results in database corruption.
7 e5 _* P) N9 K- B% c5 y1612793 CONCEPT_HDL OTHER Pattern-based auto-distribution of split symbols not working if there are spaces before commas
P2 `( F: H: [- f9 b1613442 CONCEPT_HDL CORE Signal names are not horizontally centered when the wires are added using different methods0 m x8 z( U7 K) X8 p3 q
1613559 ASDA IMPORT_DEHDL_SHE custom variables from the BOM Tables are not getting imported
2 Q9 }3 H, s& p8 v' Z' \7 T! |1614093 CONCEPT_HDL CORE Import Design window has artificial 64 char limit for path - prevents access to some locations
! x9 I& q" n. z* X1 ]# R1614372 CONCEPT_HDL EDIF300 OFFPAGE symbol is exported as PageBorder in EDIF300 schematic
' @0 D- V& \6 x& W1615075 APD LOGIC Netlist-In wizard fails to import the net names, but gives a successful completion Info message2 d O! J; z/ G4 p8 ~) }. z% s# @
1616131 ALLEGRO_EDITOR PLACEMENT While placing a module, the Mirror command in the right-click pop-up menu is not working
8 t# N/ f$ }2 U; y2 Q0 M; ?: k1617377 ALLEGRO_EDITOR UI_GENERAL Visibility pane does not retain the correct layer view
& G( o: l- J$ V) g: W2 k1 P- }1617404 ALLEGRO_EDITOR UI_GENERAL axlUIMenuChange does not work as expected in 17.2
' O1 F6 V# ]( U; i ?2 B" S! a1619412 ALLEGRO_EDITOR INTERACTIV Script to create new padstacks from existing padstack is putting in wrong values for a regular pad
0 m4 s/ d2 f3 n. O* G1621842 ALLEGRO_EDITOR PLACEMENT mechanical symbol without placebound will not place in QuickPlace
+ K) C6 _: F8 q0 s3 G' E; |- M1621874 ASDA PRINT Print - Save as PDF uses the default printer options only6 j" Y6 n& N8 h1 _4 q* Y
1621887 ALLEGRO_EDITOR INTERACTIV Getting a 'Could not satisfy the snap condition' message when using the Snap pick to option! p- j Q9 I3 D" c) {1 i* t
1622680 ALLEGRO_EDITOR PADS_IN Import PADS fails with the 'ERROR: *NET* section found. Translation of netlist is not allowed.' message! [* |" ?8 u f2 t, U
1623832 ADW COMPONENT_BROWSE Incorrect part placement on schematic in Design Entry HDL 16.6-S073
- g/ N3 }0 v) y1 _% j/ j- X2 v/ b% g4 y1624813 CAPTURE GENERAL The Value property is always left aligned when placing a symbol on the schematic, \$ e8 F$ E: [! @
1624953 ALLEGRO_EDITOR UI_GENERAL Custom views in 17.2 do not return to original _0 E/ M$ F* g( a
1625000 ASDA CANVAS_EDIT File - Save Project does not provide any indication of saving or progress bar; y5 p0 N$ | b. z$ A, [; D
1625163 CONSTRAINT_MGR OTHER There is no status for the analyze command in the Constraint Manager in 17.2' V5 P/ Q3 D8 p8 O ^& \, t* s
1626647 PSPICE ENVIRONMENT Capture crashes when loading a design with two hyphens in sim profile name* l, [, p! c% d% v$ x3 y+ E
1628357 CONSTRAINT_MGR OTHER Constraint Manager shows differences if exporting and importing constraints on the same board.. C+ p3 p" c. n0 U! O
1628409 ALLEGRO_EDITOR PAD_EDITOR Pad Stack Editor does not remember last used directory" a8 I% `( t% ]5 f& {
1631443 CONCEPT_HDL ERCDX ERC reports warning due to lower-case value of some properties in chips.prt- d, o5 V: P4 \5 y
1632195 SCM OTHER 'No known page border found' error in cref.log
: E8 A% G; }7 V u1632365 CONSTRAINT_MGR OTHER Select command is disabled in the right-click pop-up menu from Constraint Manager in SPB 17.2
* f/ c. y1 |- x. B5 @9 ?+ u, F1632462 ALLEGRO_EDITOR 3D_CANVAS 3D View (new) and PCB Editor crash when checking collisions
1 C& s1 u4 e. W- G! o7 ]& O1632590 ALLEGRO_EDITOR 3D_CANVAS PCB Editor crashes when 3D View is open and more 16.6 boards are opened
3 ~9 M; ]" U( _* A1633433 CONSTRAINT_MGR UI_FORMS Expand - Collapse feature for multiple objects not working correctly
8 { I, C1 {- J9 I, P5 I1633454 ADW TDA TDO crashes if DAO throws an exception
% G! J* v# A+ U1633526 PSPICE AA_PPLOT Spaces in Simulation Profile cause error in Parametric Plotter) L7 P) G( l- X! p
1633608 ALLEGRO_EDITOR COLOR 'Retain objects custom color' should not enabled as default.
5 c3 m8 X2 I' _; V. _* z1636216 ALLEGRO_EDITOR 3D_CANVAS Interactive 3D canvas (Unsupported prototype) is not mapping step model when assigned to device6 R3 f' E* F) @% N1 K# e" \
1636899 ALLEGRO_EDITOR 3D_CANVAS The new 3D Viewer is not taking the Package Height set on the PLACE_BOUND layer into account when displaying it.$ C9 w Q! b6 J( `! X
1638185 CAPTURE DATABASE Opening CIS database locks all part libraries none of which are open
9 } p9 u# Q ~; l- X$ A1639409 ASDA CANVAS_EDIT Handling of MAKE_BASE property from DE-HDL designs imported into SDA' j" |" j+ Y+ M& T5 {
1639541 CONSTRAINT_MGR OTHER PCB Editor 17.2 crashes when making changes in Constraint Manager9 V* f8 [% N: M7 s" ^ N
1639613 APD STREAM_IF The stream out command has created sharp angles in the GDSII output file" ?* `+ `9 j9 d+ b3 o$ d# R
1640061 ASDA HIERARCHY Incorrect message received when invalid characters are specified for subdesign suffix
+ o& x7 X) `5 H( \! A# X& A l! n( z1641118 F2B DESIGNVARI Some DNI parts are not identified in the variant view due to the BLOCK" J6 r% F1 P( l, m3 [
1641410 ASDA CONSTRAINT_MANAG No errors or issues reported when incorrect topology is applied to a net or an Xnet
, E5 v4 R. r: i, o% u1642891 CONSTRAINT_MGR CONCEPT_HDL DE-HDL crashes randomly while working on Constraint Manager4 O; Z' e B6 t' O8 P8 w+ C
1643003 CAPTURE PROJECT_MANAGER Start page shows latest as S004 after installing S005
2 w. E* ?; G$ ~1643532 ALLEGRO_EDITOR OTHER Strip design command fails to delete symbol text in the attached design$ M. ?4 ^. c. c! s4 ?
1645529 ASDA CONSTRAINT_MANAG Unable to delete the diff pair from the nets
, O8 P* D% _# Z2 \# I1645639 CONSTRAINT_MGR CONCEPT_HDL DE-HDL crashes when the XNET_PINS property value has a trailing comma character
6 {+ X0 b6 H( G; Q7 N- p1646354 CONSTRAINT_MGR CONCEPT_HDL Cannot select Design Instance/Block Filter from the View menu in Constraint Manager
$ o" T! U' }/ m" ~1646612 PCB_LIBRARIAN CORE Generate Symbol option crashes Part Developer
5 Q2 I1 [5 h- c1646932 ALLEGRO_EDITOR MANUFACT Manufacture - Auto Rename Refdes keeps defaulting to Use Default Grid even if another is chosen2 z3 X1 s7 R/ b5 v. [& b9 p
1647190 APD REPORTS 'Sorted by Bond Finger' report shows incorrect wire bond connection- D( t0 [% R4 A# f" l5 r2 }' Y
1647673 ASDA EXPORT_PCB Two Physical folders are seen after installation of QIR
- ? l' ]) B+ f, R! f1647729 ALLEGRO_EDITOR SKILL axlFillet returns t when fillet is not added.. S( B& x! g; u U K
1647779 CONSTRAINT_MGR OTHER 'Software Version' in the cmDiffUtility viewer does not show the correct version
9 A/ x7 `5 I' @) G/ V( O1 m1647843 ALLEGRO_EDITOR ARTWORK Misleading information in command window when artwork import fails
2 z# K! w5 s, J+ _3 { T1648575 CAPTURE OTHER Suppress warning setting must be written in capture.ini file/ E3 D1 G, l7 s/ S+ ]* g
1649060 CONSTRAINT_MGR CONCEPT_HDL Rename dcfx to dcf process results in error in log file and dcf not updated
+ r8 r) l6 N. @! g7 y1 _1650106 ALLEGRO_EDITOR 3D_CANVAS 3D canvas rotates mirrored components in unmirrored angle8 k. }' |% q8 j
1650238 SIP_LAYOUT WIREBOND When performing 'Adjust Min DRC', the reference bond finger should not move.: y+ l. J# z& n
1650734 APD SHAPE Shape on L1 does not flood properly
, h/ f: b3 n" b+ k# a9 n- d1650793 CONSTRAINT_MGR CONCEPT_HDL Conflict of XNET_PINS definition between the chips and the SIGNAL_MODEL is not handled correctly @$ y& q! ^( @) M+ Z' ^
1650801 ALLEGRO_EDITOR SCHEM_FTB Running Export Physical with Update PCB enabled in Project Manager crashes netrev.exe
3 a. o7 T5 s( Q# p( |1651011 ALLEGRO_EDITOR 3D_CANVAS Interactive 3D viewer shows mechanical symbol mirrored
! s. y( C2 x( T2 K6 `! S6 V# u1651063 ALLEGRO_EDITOR CROSS_SECTION Cross-section preview is incorrect0 W; V% @2 x3 b g3 ]
1651066 ALLEGRO_EDITOR DATABASE Pins not connecting even after running the Tools - Derive Connectivity command
4 W) u, H* w+ f& E+ I) F+ \0 p1651700 ALLEGRO_EDITOR SKILL Running axlXSectionModify() on a layer removes the value of the material
4 W& h8 u& U6 G- F# t* _; c1651925 ALLEGRO_EDITOR ARTWORK Searching for a macro in the artwork data file: Count for the macro does not match the actual count in the output+ [0 b, a5 _# l$ b7 Q
1652230 CONCEPT_HDL CORE The master.tag and vlog004u.sir files are not created in the entity directory on saving symbols
% U! j) o2 I. b: Y1653080 CONCEPT_HDL ERCDX Difference in results from SPB16.6 in 'erc.rpt' when logic_data is renamed as worklib in SPB17.2 on RHEL6.57 a+ P# W, C# a- f/ d- D
1653422 ADW LIBIMPORT Classifications not linked to a Part Number or Cell Model are removed during Library Import
/ Y$ Y: T$ [5 \) t1653526 ALLEGRO_EDITOR DATABASE Via padstack keepout is not displayed on the canvas when pads suppression is enabled.& C6 v" C9 B, I
1653951 ALLEGRO_EDITOR CROSS_SECTION Cross Section Editor changes lost despite selecting No to the 'All changes will be lost ...' message
2 a+ w# ^8 G, G% Y6 [" o, p9 n: r1656224 ADW FLOW_MGR Copy Project wizard no longer allows dashes in the 'Name of new project folder' field( ?9 Z/ C# \0 m/ ]$ V( M9 l
1656581 ALLEGRO_EDITOR OTHER PDF generated for layer with shape shows undesired voids if film is mirrored and Filled Shape is not selected
. B6 ]0 t G. Z7 h) K" z1656608 APD REPORTS Incorrect calculation in the metal usage report
) u" A$ p) v; i- a1656726 CONCEPT_HDL CORE Interface command always disabled in the Wire menu- K3 _+ w" y. F
1656841 CONSTRAINT_MGR UI_FORMS Incorrect layer information is displayed in the Edit Via List dialog when a filter is applied
; W) E1 w+ f: h8 y$ _6 J+ z- t1657220 ALLEGRO_EDITOR SKILL axlXSectionGet() returns Primary list of layers and not All stackups8 f" A1 ?% `' ?" M6 i6 }' G+ Q* k
1657257 SIP_LAYOUT EXTRACT When using extracta, custom layer names not getting retained
/ k# ~ y5 `+ {! ^& `1658440 ALLEGRO_EDITOR PAD_EDITOR The location of a drill in the .pad file is different from the .dra file2 U3 p$ o1 b3 H9 K* ]4 ^& p
1658445 CONSTRAINT_MGR CONCEPT_HDL When DCF file is converted to ASCII, no further updates are allowed.' j; s" m. |! B/ T- W) X
1659473 SIP_LAYOUT WIREBOND When moving wirebonds they are jumping instead of sliding4 q. A; R- v! a9 ^ Q: E" W' z4 [
1659498 ALLEGRO_EDITOR INTERACTIV Unable to turn off line on Etch Wire for Jumpers1 `2 `1 c* F; E) T8 j# |
1659644 CONCEPT_HDL OTHER Predefined nets are not listed if 16.6 design is being opened in 17.2
' |( O+ q2 A$ C$ l1 a W1660475 CONSTRAINT_MGR UI_FORMS The CTRL+V shortcut is not working in the Export Constraints window in Constraint Manager 17.24 v+ }/ j! T3 |; k4 D
1660492 ALLEGRO_EDITOR UI_GENERAL PCB Editor crashes when using multiple desktops on Windows 10
0 W4 e5 w+ b- a$ j: i6 z/ }6 K1661133 CONSTRAINT_MGR ANALYSIS PCB Editor crashes if comma is used in the Value field for Analysis Mode* A; S! m5 ]( l. x3 E
1661307 CONSTRAINT_MGR CONCEPT_HDL Prevent creation of diff pairs on VOLTAGE nets7 f/ E( ~; p9 t# V+ Z) l
1661357 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes when using Route - Connect
9 K9 |3 O6 L5 V! e1661874 ASDA DESIGN_CORRUPTIO Unable to delete the ZERO part from the schematic page1 o# E x4 u m" ~
1662799 ADW SRM Mechanical symbols are not being displayed in the Mechanical tab of Symbol Rollback Manager
: @: M7 M1 K' p6 |/ A8 N6 [1664797 SIG_INTEGRITY GUI Unnecessary coupled interconnect models were generated during View Waveform.* y5 Y1 I5 o! q3 K8 m
1664858 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes during Auto Interactive trunk route.
1 b1 m( N" p5 ~6 A, K1664911 ALLEGRO_EDITOR OTHER PCB Editor freezes after DRC Update is performed/ F3 {/ A! | O
1666329 CONSTRAINT_MGR OTHER SCM Import Physical process crashes cmfeedback0 F, T: J- \! ?: r7 H3 ], O* d
1666551 ALLEGRO_EDITOR ARTWORK Import Artwork, Mirror option separates imported artwork to different XY locations
% Q1 G# n+ B" \* Y' ]+ H1 s1666723 ECW TDO-SHAREPOINT TDO login is not working with Site Minder because of incorrect characters in the Site Minder login form HTML+ f: `8 y" X; F
1667068 ALLEGRO_EDITOR SHAPE Update shape removing the shape voiding2 | t9 I, d3 m# [" u, O }
1669828 F2B DESIGNVARI Variant Editor crashes on Windows 10 T540 P laptops but works fine on Windows 10 desktops5 U8 _6 R. H6 d. [
1670221 ALLEGRO_EDITOR DATABASE Non-recoverable corruption error is reported when saving the board after adding a layer
$ I9 s# q5 w! i. f! V; D7 i1672134 ALLEGRO_EDITOR ZONES TDP needs FIXED component override" W+ o/ b5 {) Q O# o7 `" C
5 e9 L$ N- u, e& g, Q
/ r8 J1 V/ u" h5 LFixed CCRs: SPB 17.2 HF008
+ P B& P$ Q0 H* E( R' j0 a# C7 M5 J+ X+ ^10-29-2016
' s" K( o2 x" N" Q k4 \3 L- B, I===================================================================================================================================
. O7 e" ~0 D7 |9 ^7 {CCRID PRODUCT PRODUCTLEVEL2 TITLE
6 c; w0 T: b/ I===================================================================================================================================: r: o8 M6 {5 }
1644406 ALLEGRO_EDITOR SHAPE Alternate symbol placement results in illegal parent identifier error' @0 i+ N2 ~! u8 l
1647098 SIP_LAYOUT OTHER SiP crashes on symbol copy and rotate4 s8 i& U. b; i" @
1647154 APD OTHER Disconnected Clines not working
6 F& }5 \5 Z* F# t1 F) g) H6 s3 }1648817 GRE IFP_INTERACTIVE Allegro PCB Editor stops responding on adding netgroups to a nested netgroup8 W6 C; Y( p+ s( A o, `% }: I- w
1649829 CONCEPT_HDL CORE A delay is observed before the sub menus of the File and Tools menus appear
]7 }/ |% I) V; c$ o* W1652930 ALLEGRO_EDITOR OTHER Command-line version of switchversion not working) k. j" [/ `8 k; p7 u, C2 ^$ `
1653109 ASDA DESIGN_CORRUPTIO SDA not pulling latest library information for part
; [. A! n5 u! y/ l1655377 FLOWS PROJMGR Project Manager crashes on Windows 103 e& y; r; r' t% o O. @
# Z. @3 t* z4 J( T5 q
; O$ q; ^3 S3 e. j E" Y# U% l# @Fixed CCRs: SPB 17.2 HF007
8 `& i* R, B1 o% y; j10-20-2016
# n, H7 {0 F6 R; O! c) r===================================================================================================================================
' T3 [0 v, x. M3 a& s. l" b3 CCCRID PRODUCT PRODUCTLEVEL2 TITLE
& k4 x6 V& a4 q% X6 d===================================================================================================================================
/ k% v" Y" ?( \+ z5 M1582276 CONCEPT_HDL CORE Need the ability to delete an image placed on the DE-HDL canvas2 A4 r ?. y8 T2 r
1594101 CONCEPT_HDL CORE No error or warning issued on specifying an incorrect unit for voltage/ C: z! C- n) {5 r0 B
1611293 ALLEGRO_EDITOR UI_GENERAL If the Command window is floating, it cuts off text from the bottom half of the last line.
2 n/ S n1 H, X$ d1 Y6 v% b* S1611652 ALLEGRO_EDITOR UI_GENERAL New artwork film not appearing in the drop-down list for Visibility Tab
) ~2 d; U3 g' b U2 F& a/ J1618205 ALLEGRO_EDITOR UI_GENERAL New Artwork film added is not updated in Visibility - View0 ^, q6 o9 j9 x
1631114 CONSTRAINT_MGR OTHER SKILL functions axlCnsPurgeAll and axlCNSDelete delete spacing constraint sets but not deleting names
. u8 \: ^$ t3 p) @1633726 ALLEGRO_EDITOR UI_GENERAL Visibility tab not dynamically updating the view list when artwork film changes
8 T+ c6 w% q0 G: N& N1636404 CONSTRAINT_MGR CONCEPT_HDL In 17.2 QIR1, DE-HDL Constraint Manager allows users to enter invalid voltage units' w; o$ ~6 W1 p# |1 g! w
1636864 ALLEGRO_EDITOR UI_GENERAL Domain Selection for Visibility does not work with Hotfix 004 unless you save and reopen the board file
$ m! K% v+ {& b- B1638251 ALLEGRO_EDITOR DATABASE Unplated hole changed to plated hole after uprev from 16.6 to 17.2 version: V0 K0 z! w$ m& _% A- F
1639483 ALLEGRO_EDITOR EDIT_ETCH Manually routing discrete components with incorrect constraints causes PCB Editor to crash
* n: P( \) O' ]" W2 U1641435 SIP_LAYOUT IMPORT_DATA Need SiP Stream mapping layer count to match Virtuoso stream layer mapping count
* H# O$ Y$ n" r6 n: \! c( f1641483 SIP_LAYOUT WIREBOND SiP Layout - Modify the wirebond report generation for Start and End height when using a DISCRETE class footprint2 {) a) _$ s! K5 n( P
1644131 F2B PACKAGERXL Option needed to package a DE-HDL design with ptf errors into a board file
. l7 F" M) D w: ]) b; @$ W1644807 CONSTRAINT_MGR ANALYSIS Unable to set electrical constraints modes with the OrCAD PCB Designer Professional licenses4 @, f8 g' t# {' j
1646228 ALLEGRO_EDITOR UI_GENERAL Running the axlUIMenuInsert command to add a submenu after running the axlUIMenuFind command crashes the tool3 f/ j& }' f/ U
1647402 PSPICE PROBE Unable to print on Windows 10 as no plots are displayed in the Probe window: }1 d1 Y I; F& r$ @7 T" H |
1648183 ALLEGRO_EDITOR INTERFACES Allegro STEP Export: Using the 'step_3D_copper' variable, pads not exported in the same plane as traces and shapes; Y/ v. Q3 K! {
1649222 APD ASSY_RULE_CHECK Allegro Package Designer stops responding on running the Acute Angle Metal DRC" g2 ?2 K1 I5 [' m
* X* T0 n- i. W2 i5 x" ?
, J) P0 e" p+ G; F$ h! |/ J! N
Fixed CCRs: SPB 17.2 HF0062 J n* q3 t. r$ D# s
10-7-2016
; y, G9 k i6 n) b7 k9 V===================================================================================================================================# W8 `3 w- b# s8 M( s1 m- G
CCRID PRODUCT PRODUCTLEVEL2 TITLE. ^# C: i, S2 j4 b* l3 n0 P
===================================================================================================================================
6 j7 k# X+ s; k: X0 R, v, G: i1585203 ADW DBEDITOR Optimize check-in of footprints with multiple padstacks2 Z. M0 T* @' F* ?# Z8 E
1607954 ALLEGRO_EDITOR SHAPE Dynamic Shape not updating correctly6 K" E5 v: V9 O* \# c
1618173 ADW SRM SRM does not automatically run when a .brd file is opened from EDM Flow Manager in 17.2 Hotfix 003- j) W$ d+ Y1 M1 x9 d
1618832 ADW SRM SRM marks parts as updated even when they are not updated
$ l2 U( c+ U# b2 [9 d6 ^* k# z6 G1623823 SIP_LAYOUT WIREBOND NO_WIREBOND property is ignored by Add/Edit Non-Standard
- ^% ~# M* w0 Q% k1 b, M0 m9 u1626001 ALLEGRO_EDITOR SHAPE Shape to route keepout DRCs reported for dynamic shapes in the attached design
2 P$ P# C/ i9 j1626546 SIG_INTEGRITY FIELD_SOLVERS Extra RL elements in via spice circuit model generated by Via Model Generator
7 B$ M* h( H) E: r9 ]! p1631792 SCM OTHER The NC net has re-attached itself to another net, RIGHT_LEFT_N, in the design9 w! Q0 g7 t% b* f. m
1632223 ADW LRM Checking in a hierarchy causes a crash
5 A# Y" F1 ~: {* E1632844 F2B DESIGNVARI Part is simultaneously defined as Pref and DNI in Variant Editor with no error$ r4 q0 U, ?6 c$ R
1633647 ALLEGRO_EDITOR MANUFACT Variant issue: Create Assembly Drawing command not creating filled shapes for keying pegs in attached design6 C5 }' @- Y5 |$ M% V% Z
1633707 ALLEGRO_EDITOR DATABASE Cannot remove Route_Keepout associated with a pin
; T1 T/ ~. e. p+ R( o8 f* a1634392 PCB_LIBRARIAN OTHER Launching Library Explorer without -proj option crashes the tool
3 }7 a) |, K3 \( A' ]! \1635049 CONSTRAINT_MGR CONCEPT_HDL DE-HDL crashes when trying to create layer set from Constraint Manager
1 v7 a2 p$ t# C5 G x2 d! ~1635593 ORBITIO ALLEGRO_SIP_IF Importing .sip file reports undefined argument error while processing shapes
5 \3 |& P) X, I$ F1 o1635858 ALLEGRO_EDITOR ARTWORK Get 'WARNING: Null REGULAR-PAD specified for padstack' messages in log file when generating artwork for all layers( z2 w# Z4 V+ {0 b/ R$ t8 P. b. h
1636097 ALLEGRO_EDITOR ZONES Technology Dependent Packaging footprints not updating in the design7 f. z& C4 n5 U, ^8 C# G D8 G! ^
1636185 ALLEGRO_EDITOR ZONES Import Placement not placing TDP footprints in zone6 Z# {% P( R) ] |5 ^
1636867 CONSTRAINT_MGR OTHER Millimeters shown as mils in the Analysis Modes dialog box& F) r) C% w3 b* p0 i- u! W8 p
1638094 SIP_LAYOUT OTHER Cross Section Editor not seeing updated information
* B4 H }/ K- W" B( q5 P. O1639845 ALLEGRO_EDITOR INTERFACES Step file not generated when board is exported to a folder with special characters in name) f/ U1 u3 O' r& \4 y7 K
1640611 APD SKILL Launching XtractIM from SiP Layout with the attached design crashes both SiP Layout and XtractIM! e( { `' S8 u' T" f9 S/ {, G! n
1641339 ALLEGRO_EDITOR INTERFACES DXF_IN does not show all the subclasses available in the design! d' O# T* h$ r) R" N6 R
1641879 XTRACTIM GUI XtractIM crashes on extracting a SiP design if 'SI Ignore' is selected for a die stack layer in Cross Section Editor: s. U/ |2 ^" u! m4 p/ @) |" |
1642012 CONCEPT_HDL CONSTRAINT_MGR Schematic-defined net groups without any members cannot be deleted in Constraint Manager: M. r( k% ^4 s; z
1642015 CONCEPT_HDL CORE Pin exists on block but no corresponding port exists in the underlying schematic+ x" U) e& B @6 V7 j8 c
1642597 ALLEGRO_EDITOR OTHER Importing .tdp file: Footprints not included in the .tdp file are updated in the design7 e+ t* b" n: n# p2 L
1643557 SIP_LAYOUT DIE_GENERATOR Die Text files will not update the design
' K6 z/ R6 X1 e: k1646086 ASDA IMPORT_BLOCK Importing a DE-HDL design into SDA results in error 'IMPSHT-42 Alias cannot be created'
% a" [7 p1 C# M; v1647580 ASDA IMPORT_PCB SDA-File Import from PCB Editor has duplicated RefDes on schematic.
& w9 |9 l9 r6 U: ?( s" G! t
J( P6 z7 F5 U. @* F
; k8 W: I. e7 E5 c: b, l3 @Fixed CCRs: SPB 17.2 HF005' U% M- L5 L8 R/ Q" [9 X
09-10-20165 q5 V3 A! ?3 v" O
===================================================================================================================================
5 Q- a2 N0 @0 k* [% ]& {CCRID PRODUCT PRODUCTLEVEL2 TITLE7 C0 m, g! E4 u! W5 U9 y- f4 o
===================================================================================================================================
6 E! O* Z1 H: m! R: ^ W1496199 ALLEGRO_EDITOR SHAPE Overlapping route keepouts result in a broken shape/ N; g9 J8 r" ~8 j+ j% R
1519972 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase DRC at incorrect location
+ Z' \9 k% e% E, r1521940 ALLEGRO_EDITOR DRC_CONSTR PCB Editor not recognizing the correct pin pairs of the differential pair
2 |$ z: s! k; I2 u1536713 ALLEGRO_EDITOR INTERFACES File - Viewlog still checks for brd2odb.log file5 ?6 |9 ?8 O$ e8 H: e1 ?
1568912 RF_PCB BE_IFF_IMPORT Route keepouts can only be imported once9 F8 L* b; b t# Z4 p
1586846 RF_PCB PLACEMENT Get an error while manually placing RFCOMPIB part
; i; A: P- t. |6 X+ ]4 D1588769 ALLEGRO_EDITOR UI_GENERAL ALT+key shortcuts are not available in 17.2. O* n0 R0 n' q7 E/ I0 z
1589396 ALLEGRO_EDITOR UI_GENERAL Need option in 17.2 to change the placement of the Find, Visibility, and Options tabs
) D' u8 r5 c& v/ l1593258 ALLEGRO_EDITOR OTHER Adding German letters to database diary deletes all the entries! @# C' }# n ?+ J0 M9 B
1597413 SIG_EXPLORER SIMULATION SigXplorer crashes when simulating with a via that was added to the canvas
& r' g# s) v* O% s" q1599680 ALLEGRO_MFG_OP ALLEGRO_INTEG Documentation Editor crashes on opening a specific database
( s d0 s- q( A+ s1606682 ECW ADMINISTRATION ECWBackup and ECWRestore fail when data is 1GB or more
6 h6 V, U( F {2 `8 u1607250 ALLEGRO_EDITOR DATABASE A board file created in release 16.5 crashes when opened in 16.6 Hotfix 69
3 W* i3 B8 e: G' O0 J7 l1607565 ALLEGRO_EDITOR SYMBOL Default values are not consistently converted when adding pins after changing units.4 N# w% ?: |8 K% a
1607956 ALLEGRO_EDITOR OTHER Unable to generate the model index file from the command line using mkdeviceindex/ }* [/ x% N/ I
1609794 ALLEGRO_EDITOR UI_GENERAL PCB Editor: Shortcut keys to menus are not available in 17.2
1 P/ ]& c, W0 ]1 E0 B# J; Q, q1609817 CONSTRAINT_MGR CONCEPT_HDL DE-HDL crashes on opening project
' K% K4 t$ ?6 M- x. X1611446 ALLEGRO_EDITOR SHAPE Inconsistent break in shape when creating voids in a design in 16.6 Hotfix 69* I: h3 n2 `% z
1613512 ORBITIO ALLEGRO_SIP_IF Unable to read the OrbitIO database file (.oio) in SiP Layout
8 G P7 z. H. G) ^1619610 ORBITIO ALLEGRO_SIP_IF Some mechanical pins appear rotated by 90 degrees when imported
/ W* v% M l/ Y2 i- o$ h1620814 ALLEGRO_EDITOR PARTITION Etch and Via are not imported with the partition1 d' X0 |$ Q( Z) z( F
1621390 GRE CORE Design Crashes during the Spatial Planning phase
/ W# e7 f! i9 C1623112 ALLEGRO_EDITOR OTHER SPB17.2 switch release is unable to identify 16.6 release when 16.6 is installed in All-Users mode: T3 T& W y1 d1 d
1623113 ASI_SI GUI Aggressor waveforms are not displayed in waveform viewer after crosstalk simulation+ M4 f2 b4 ], r# L
1623231 CONCEPT_HDL CORE Unable to make the Attributes form part of the standard display in DE-HDL/ } a) K" V( K [; D$ q
1623666 APD OTHER Incorrect vector pin syntax appears in the chips file written using 'RF Module - Export chips & connectivity'. L$ I5 R8 A/ ^( i/ u9 r
1623888 CONSTRAINT_MGR CONCEPT_HDL Ambiguous and inaccurate mapping errors reported when an ECSet is applied to a differential pair object* n9 [- a& `# l2 N, V9 g) i% {
1623904 ALLEGRO_EDITOR SCHEM_FTB Logic import fails, but no error mentioned in the netrev.lst file
7 u {" w! b* t; g) I3 C9 h4 ]0 o* e1623935 ALLEGRO_EDITOR SKILL On running the SKILL function, axlSectionModify, Shield and Etch Factor are not updated d. p$ j1 h4 ]- \! Q+ b: V
1625610 ALLEGRO_EDITOR SHAPE Modifying a shape boundary leads to other shapes losing their voids7 b. S+ q7 E3 _7 s! [) d7 M
1626716 ALLEGRO_EDITOR UI_FORMS Z-Copy menu is not available with OrCAD PCB designer Professional license2 {: E2 d9 C* B
1628403 ADW TDO-SHAREPOINT Objects remain checked out after multiple failed 'check-in hierarchy' attempts
5 F1 |, n" E# O# C) L3 R) v$ g1630458 ORBITIO ALLEGRO_SIP_IF Import OrbitIO Database file (.oio) in SiP: Bill of Materials report does not include standard dies9 g* c" @6 [$ j( U6 S
1632504 CONCEPT_HDL CORE DE-HDL core dumps during Save Hierarchy on Linux
; A+ r4 _! @6 }9 f! w$ n1633581 ALLEGRO_EDITOR PLACEMENT On mirroring a part, the cursor moves to the origin of the board2 L% o0 W1 M [: U
1633601 ALLEGRO_EDITOR PLACEMENT Place - Via Arrays - Boundary command: Via arrangement pattern deteriorated in Hotfix 004
. u6 Y0 L; a" T6 P/ H% j+ ]% l0 W' \9 }! r I
/ B$ m6 }# Y, h; j7 HFixed CCRs: SPB 17.2 HF0041 W! j6 p! ^+ a, n; s
08-14-2016
( V# F9 Z: D$ A- h===================================================================================================================================2 K: z( T/ x/ K. D! f. t/ u$ N
CCRID PRODUCT PRODUCTLEVEL2 TITLE
3 v; C3 w2 ?* Y===================================================================================================================================
R% h ] b# P908816 CAPTURE SCHEMATIC_EDITOR Few graphical operations are active even when a page has been locked& _1 y+ `1 I; N2 G, V$ h' T
1213923 ADW LIBIMPORT Cannot delete parts in the Library Import project (XML)5 G; v# W/ w7 j, J9 M) Q. @
1250476 PCB_LIBRARIAN LIBUTIL con2con does not check for PACK_TYPE value set to question mark+ P' u! N8 I; m; O% _; ]+ n3 R8 J
1306441 APD OTHER The Minimum Shape Area option in Layer Compare uses an unspecified value2 ]+ e* w; r! P# O5 L
1322242 ALLEGRO_EDITOR INTERFACE_DESIGN Using Add Connect with the Replace Etch option causes PCB Editor to slow down for certain constraint nets4 w9 `+ j9 L2 i3 w- J
1326716 ADW DOCUMENTATION Dataexchange documentation correction needed
7 b' \8 _) m) ]3 }1356948 APD DEGASSING When using the Degassing tool on shapes the size of the file becomes very large
2 J1 \( C9 _9 x5 M/ ~: _/ Q1376510 ADW DBEDITOR DX output ERROR after Property Display Ordering of Part Classification.
2 h( e P$ q" b1408218 ALLEGRO_EDITOR MANUFACT Specifying the Offset value results in unexpected value of the NC Route coordinates in the .rou file
* x1 M+ a- N! X$ z% O% ^' z1410485 CAPTURE SCHEMATIC_EDITOR The 'Autowire - Connect to Bus' menu command and the 'W' keyboard shortcut are enabled on a locked design
3 y$ r% N( d2 J+ c! r1413248 CONCEPT_HDL CORE Import from another TDO project makes the block read-only; Z8 m9 `, X3 u
1413287 ADW LIBIMPORT Library Import converts all Attributes to uppercase when reading CSV
6 K, ]) K8 W' z2 ~' }2 V% c6 `1417429 ALLEGRO_EDITOR INTERACTIV Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle0 P+ M' b. R' k3 Z0 V: P* I
1417442 ALLEGRO_EDITOR INTERACTIV Spin via stack and only part of the stack spins2 B% l; [3 H3 _5 K3 }- Y
1430251 ALLEGRO_EDITOR PLACEMENT Quickplace placing symbols outside of a polygon shaped room i5 b; t' n+ Z( o
1440509 ALLEGRO_EDITOR PLOTTING Ratsnest does not follow the RefDes position when plotting the BOTTOM layer with the Mirror option
1 W) @- f! _% A. o, c4 } C1441086 PCB_LIBRARIAN OTHER Changes made to a package with sizable pins generated from the 'sym1' view are not saved
! _5 {' a6 \) I' S1443339 PCB_LIBRARIAN PTF_EDITOR ALT_SYMBOLS syntax in PTF file not checked b+ C. k/ T1 q8 Q' z1 h, o+ f
1444144 ALLEGRO_EDITOR DRC_CONSTR The 'add taper' command generates line to line spacing DRC
n; _! e- r w0 t" q+ e, w1451766 CONCEPT_HDL COMP_BROWSER License error message should indicate which license is required3 @7 d' a, ]9 L* I G
1451977 CONCEPT_HDL PDF Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set/ h" h& t" m- t
1457138 CONCEPT_HDL CONSTRAINT_MGR devices.dml: difference in content generated by _automodel add command and Constraint Manager launch
" x; ~; S+ {6 ` R1 s1 _: M1458439 F2B PACKAGERXL The Packager pstprop.dat file reports false conflicts in net properties3 O. Q3 P. \; x5 p+ l% \7 k
1464865 CONSTRAINT_MGR ANALYSIS For identical nets, topology in DE-HDL CM is different from the topology in PCB Editor CM% C% u3 _* u; _1 d; x
1464948 PCB_LIBRARIAN VERIFICATION The errors/warnings do not match between the various tools
/ l9 |! \ _( J/ s1467826 CONCEPT_HDL PDF PublishPDF from console window creates a long PDF filename
" c$ w( \4 d9 J M \( b5 ^1470106 ALLEGRO_EDITOR MANUFACT silkscreen program cuts auto-silkscreen lines excessively
6 s# s4 N8 N$ e ]: Z F3 s2 Z. z1471287 CONCEPT_HDL CONSTRAINT_MGR Pages imported from other designs with different units should inherit the source constraint units
: u2 }0 C. O3 ~! ] `) s4 C1472046 ALLEGRO_EDITOR OTHER Gloss routine, 'Via Eliminate' - 'Eliminate Unused Stacked Vias' is not removing unused microvias from the stack) A- x) y( G" {% o. E
1472414 ALLEGRO_EDITOR SCHEM_FTB netrev changes pin-shape spacing rule in constraint region
* f0 I; r6 _# Q" }& V1472444 ADW ADWSERVER Multiple errors in adwserver.out after SPB054/ADW478 l: N- T% G6 G& z
1473056 ALLEGRO_EDITOR ARTWORK Gerber export has additional phantom data not on design# l& K' r w8 |, p
1473900 CONCEPT_HDL CORE DE-HDL stops responding when a hierarchical block with variants defined inside the reuse block is enabled U9 d( V7 |! P* u; w1 K3 R$ z* I
1474020 ADW DBEDITOR Unable to modify schematic classification when a part is checked out previously by another librarian: g- r) z3 v' P
1474066 ADW DBEDITOR Bulk edit performance lags when parts included have a large number of properties* q* T( V# }8 B( b) Y
1474764 ALLEGRO_EDITOR PLACEMENT In Hotfix 56, the 'place replicate create' command does not produce desired results if a fanout is marked# P+ G) T9 i7 F" }& d
1474894 ALLEGRO_EDITOR PLACEMENT Place replicate fails to include vias when the module is applied to other circuits.' w* {* j6 q6 ?1 ~' r1 i
1475650 ALLEGRO_EDITOR OTHER Using Outlines - Room Outline gives WARNING (axlRemoveNet): No match for subclass name - 'BOARD GEOMETRY/__EPB_SCRATCH_'
. @( }; H) [6 \" N1476528 ORBITIO ALLEGRO_SIP_IF While translating a .mcm to OrbitIO, the error 'allegro2orbit.exe has stopped working' is thrown& q( m: {, l# y; K: [) K
1476920 CONCEPT_HDL OTHER Genview consistently fails in some indeterminant manner., {- O) h* l% Q! J- {$ Z/ h
1477369 CONCEPT_HDL INTERFACE_DESIGN A significant number of problems are reported when running genview with port groups
/ Q A% [, K+ `0 E5 Z, K1478111 F2B DESIGNVARI Hierarchical block variant not shown in testcase with S57 although it was working with 2015 release
) k) y4 X6 g- h6 c [1478200 GRE IFP_INTERACTIVE PCB Editor displays the 'Low on Available Memory' error when updating shapes and then crashes
# T; P$ k6 Y' I* h1478680 CONCEPT_HDL CORE Unable to move components in a schematic using the arrow keys( a3 U9 Q- q% J& F' |% d3 z
1479135 F2B PACKAGERXL Hierarchical design reports conflicts when signal names change through the hierarchy
) Y% r: i4 X3 \1479153 CONCEPT_HDL CORE File - Save Hierarchy flags an error and does not update subdesign xcon
5 s+ D2 n1 r4 d" l& \" o1479227 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy
) i$ K4 F1 X# J, s1479454 CONCEPT_HDL OTHER DE-HDL issue: locked DIFF_PAIR property is editable, r2 t* ^) w; r$ R O
1479569 PCB_LIBRARIAN OTHER hlibftb fails with error SPCOPK-1053
/ z& A$ C" ]* h8 y A0 |8 P3 Y) A8 }1479785 ORBITIO ALLEGRO_SIP_IF BRD file is not loaded in OrbitIO, I4 b/ j- u9 R2 H1 U
1480005 ADW DBEDITOR The DBEditor or DBAdmin GUIs do not allow the same characters in Property as LibImport CSV Files
) Z8 m4 c) v2 |; }; i0 ~9 i3 {1480367 SIG_INTEGRITY OTHER Differential pair extraction SKILL error
. n; N; ]. M% F$ n1480499 ALLEGRO_EDITOR PARTITION Cannot delete partition
# O9 n0 `+ b& T0 t, I6 j/ K1 n1482544 ADW DBADMIN Hierarchical Preferred Parts List (PPL) is not functioning correctly
& g3 ]# D X( R$ \) f1483136 ADW COMPONENT_BROWSE Error flagged when searching a property value with parenthesis or comma in Component Browser in the ADW mode' K6 j/ m+ l3 x( n* f; w
1483617 ALLEGRO_EDITOR DATABASE Delete islands command crashes database with filled rectangles( N0 _ V: g: Q1 `7 c5 g* [
1484100 SIP_LAYOUT INTERACTIVE SiP crashes when copying and rotating a symbol
l! G$ _: b2 n3 w7 x2 W6 M5 o& q1484781 CONCEPT_HDL CORE Three different Hierarchical Viewer issues
3 v- ?2 B: T+ v* O/ O+ r1485059 PCB_LIBRARIAN CORE Part Developer pin attributes are randomly marked as read-only% {; Q4 Y% u; n/ V$ b4 X7 c
1485931 ALLEGRO_EDITOR INTERFACES Errors generated when importing IDF in an existing board file$ }9 Q% r6 `( i" ^$ O
1485960 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule is crashing the project
, n# t# J' d2 ?6 G }. Z1486086 ALLEGRO_EDITOR ARTWORK Cannot generate artwork.- N, D, S4 s, w& m4 ?6 a3 C
1486378 ALLEGRO_EDITOR PARTITION Unable to delete orphan partition as it is not listed in workflow manager.% M4 F9 ~8 a0 |
1487085 CONCEPT_HDL CONSTRAINT_MGR Import Physical with the Constraints only option reports problems
4 N8 W, y9 C* J7 P1487125 ADW COMPONENT_BROWSE Results not displayed in Component Browser for parts with no associated manufacturer parts
/ V$ _) s5 `. J( n1487265 CONCEPT_HDL CORE Replace command in Windows mode shows incorrect behavior
1 Y# ^9 _/ X& g7 _9 q1487496 ADW DATAEXCHANGE DX changes checkout ownership when override action is set to remove existing relationships
. Q+ R+ |, E; t2 C& Z5 q0 o1487656 ADW LIBIMPORT Pre-analyzing a project reports false warnings- T& [& g7 b6 d( F3 d- d' U
1487733 CONSTRAINT_MGR OTHER Export Physical takes more than two hours to update PCB Editor board
9 ?: ~- P/ r, v' Z9 j1488753 CONCEPT_HDL CORE Import sheets in a design with no change in models: CM_VALIDATION_ON_SAVE variable is triggered1 e6 z; m* D9 D3 Y4 p/ ? |6 T) }
1488758 CONCEPT_HDL CONSTRAINT_MGR Disable Constraint Manager launch if CM_VALIDATION_ON_SAVE is set and the database goes out of sync- P, I3 \: f% j2 i4 ?5 a
1490299 SCM OTHER Allegro System Architect does not update revision properly9 O* p" p$ b; v3 a5 a
1490744 ALLEGRO_EDITOR SKILL axlChangeLine2Cline changes line to cline and places it on the TOP layer* R, b$ F {5 [- t3 _
1490924 F2B PACKAGERXL Save Design/Export Physical is resetting Via constraints/ ?+ V/ [+ j {/ u! R
1491351 ALLEGRO_EDITOR OTHER Create Detail for bond fingers on a custom layer not working1 T& w, v, s+ G3 ~! l
1492013 CONCEPT_HDL CORE Stale PNN properties not cleared from schematic on packaging design (backannotation) s5 C" t; y) b2 l4 V
1492595 ALLEGRO_EDITOR MANUFACT Dimension character substitution help is wrong. P2 E& K. O$ }* t- ?( h
1492703 CONCEPT_HDL OTHER 'Global Property Display' not working for symbol edit1 [5 v* l2 u; v* h! n% J5 l0 p7 ~
1492777 ORBITIO ALLEGRO_SIP_IF OrbitIO crashes on importing MCM0 B5 Z" J8 A2 T* b: u
1492901 CONCEPT_HDL CORE Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL
% K" W- L( E9 D+ ?5 T3 z: o# K1494194 CONCEPT_HDL CORE Random display of the 'PHYS_NET_NAME' property in hierarchical designs+ e* P5 `' a7 @4 S5 Q* R: m
1497597 ALLEGRO_EDITOR DATABASE Show Element on pin shows wrong drill size
& V4 _4 j" r/ Z; i# j% e6 @. {1497956 CONCEPT_HDL CORE ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root9 [, ]- E6 y$ ?- t/ G8 M
1498234 ALLEGRO_EDITOR ARTWORK PCB Editor fails to create artwork and no error is listed in the log file
% `: a: ~3 W, Z1 y; Z C1499363 CONCEPT_HDL CORE Custom attributes under variant management stopped working in Hotfix60* q+ K. k4 n: d9 o
1500422 ALLEGRO_EDITOR SKILL SKILL function, axlTriggerSet, results in PCB Editor crashing at launch* E% k" _5 \# T" X1 H# R5 k; y
1500725 CONSTRAINT_MGR CONCEPT_HDL Unable to clear pstprop.dat file conflicts
% u. W* m% F! I3 p. f; q3 l$ ^1501093 SIP_LAYOUT OTHER Package design variant shows wirebonds connected to a die which is not part of the variant
`" Y; f6 n( n1 ?) e1501165 F2B DESIGNVARI TDO does not manage overlay files and variant_roz1040660_1.ba cannot be created unless variant_merged.dat is checked out# d6 E) U$ N$ r' e W% D) N( r6 d2 |7 h& K
1501294 ADW COMPONENT_BROWSE Some tabs missing after the migration to ADW ISR 053 with SPB ISR 060" n9 V! \) F/ D' R- M, t
1501974 F2B PACKAGERXL 'Feedback has found Illegal pin swap(s)' error although the pin was already swapped and fed back (B2F) to DE-HDL0 r# @+ \7 i$ L. I" t6 x, u
1502282 ADW CONF Configuration Manager: Clicking 'Set up or Manage Company & Site' gives an unclear message7 q; q4 }$ m4 E6 z! G
1502782 ALLEGRO_EDITOR SCHEM_FTB Allegro System Architect (SCM) - Export Physical stops unexpectedly without any errors or warnings( c* y! c% O9 j) C9 N8 V1 W8 `
1504093 ASI_SI GUI View Topology and Waveform buttons overlap when Signal Analysis window is resized5 T6 ]' d0 M+ s
1504767 CONSTRAINT_MGR SCHEM_FTB Constraint Manager generates errors if the 'sNoF2BFlow' property is added to the Constraint Manager Dictionary
/ J4 P* A0 v) s4 f1506110 ALLEGRO_EDITOR DRC_CONSTR No DRC shown when a text on etch layer is overlapped on mechanical pin
3 R* X1 b9 O5 b1 p! Q4 T1506654 CONCEPT_HDL INTERFACE_DESIGN On moving, Netgroups break
4 N7 z% X- a6 B; O! @1507497 ADW COMPONENT_BROWSE Switching rows in Component Browser does not change the graphics of the symbol
( S; M* m0 v9 E0 I1 R! e" ]1509184 ALLEGRO_EDITOR DATABASE BB vias in mirror have terminal pads suppressed by artwork
' y! T* }; k7 l6 e1510387 FSP EXTERNAL_PORTS Break in extending a net as a deep connection when it is targeted to multiple FPGAs connected in a daisy chain
8 R l% x c4 v* V0 H- _& M1510570 ADW DATABASE ERROR: Cannot check in block model because the part with instance id used in the model is not available in the database" m O* _0 _: M9 {* w8 m
1511180 ADW DBEDITOR Database Editor: Incorrect message about a schematic mode displays when associating a footprint to a part number
' y3 B) z. f3 w C1511397 SIP_LAYOUT TECHFILE Tech file exported from release 16.5 cannot be reused in SiP Layout in 16.5 or 16.6& w7 ^) a$ U! c7 s# |* {6 T
1511744 ALLEGRO_EDITOR OTHER Allegro PCB Editor removes property from component instance
, w+ Y9 P0 b$ j9 ^; H9 [- [1511761 SIG_INTEGRITY OTHER Allegro PCB Editor crashes on running the cns_show command.- L3 p. J+ t% d# b
1511947 ADW DSN_MIGRATION Command line arguments of the 'designmigration' command are not working
3 k" q. |! K1 B* Z& O1513085 CONCEPT_HDL CORE NC symbols in the schematic are being renamed to NC_1 in pstxnet.dat and are routed as one net in Allegro PCB Editor5 C; A/ ?9 z; m+ j1 L. [
1513092 ADW DBEDITOR Create Footprint Model name is not working properly if it already exists in the local flatlib: R3 b# k- M, n- D# j$ L3 ?6 q' Y
1513737 ADW CONF DesignerServer from a different network domain does not show distribution data
8 l0 n% \& U" N9 p0 e: x( R1514469 CONCEPT_HDL CORE Unable to get rid of an underscore from the PHYS_NET_NAME property# }, X3 y; r( y3 h% s# a, x. e1 B
1514942 SIP_LAYOUT CROSS_SECTION AIR no longer permitted in stackup in 17.0
, u: u: V& H1 m; C$ W. ^1515318 PCB_LIBRARIAN IMPORT_EXPORT Import Pin Table: 'CTRL + C' and 'CTRL + V' not working correctly: a1 t- H# E/ ^1 Z/ m
1517351 CONCEPT_HDL CORE Genview does not update an existing split symbol
* D9 V4 r" {. `) q, L$ s& U1517388 ALLEGRO_EDITOR SHAPE DRC error reported as PCB Editor fails to read the void for a via q c: t0 l+ }- \
1518032 CONCEPT_HDL SECTION Error SPCOCN-2009 displayed even when the user has not manually sectioned the design
' w# p7 z# r" p) J7 A& E U1518724 PCB_LIBRARIAN PTF_EDITOR PTF Editor is not saving changes
3 g4 R' A- j; T8 I: ?& s1519040 ALLEGRO_EDITOR DATABASE Match groups are lost when a board created in SCM is saved in Allegro PCB Designer.
) b( g; f) d6 z9 K0 [- E5 ]3 s1519518 CONCEPT_HDL OTHER Genview does not generate split symbols
2 ~7 P' m0 n% [8 c2 R1519623 CONCEPT_HDL CORE Differential pair added to a NetClass does not display 'NET_PHYSICAL_TYPE' on the canvas s' l K' { D: o! E
1519910 CONCEPT_HDL INTERFACE_DESIGN Hotfix 62: Information on manually-remapped port groups is not saved, but reset to default
/ ]1 q. N; h% O3 k8 V5 b1519946 CONCEPT_HDL CORE Renaming a net leads to loss of constraints associated with the net4 T5 }; d4 B8 ~$ b1 d5 R
1519987 ALLEGRO_EDITOR SCHEM_FTB In Hotfix 61, constraints are lost on importing a netlist
9 s9 k! l; i' E# D1520207 CONCEPT_HDL CORE Genview crashes after renaming ports
; t9 C6 J* a+ o% l4 g" h1520727 CONCEPT_HDL CORE In Project Manager, the 'Design Sync - Export Physical' command does not automatically update the schematic+ U9 u- g# L- m) }9 @+ w7 M
1521174 SIP_LAYOUT DIE_STACK_EDITOR Padstack shapes not converted correctly to die-stack layer using Die-stack Editor* ?! A* o Y* e' K$ w
1521871 CONSTRAINT_MGR CONCEPT_HDL Constraint Manager launched from DE-HDL allows space in the name of layer sets9 H* j9 K) j, T' r8 j) t% O* N
1522831 APD OTHER axlSpreadsheetSetColumnProp with 'AUTO_WIDTH' propName does not autofit the contents.$ g+ S" t& Q8 f/ ` T
1522900 ORBITIO ALLEGRO_SIP_IF Padstack shape distortion after translation to OrbitIO from SiP Layout design( Z5 a4 h. v8 ~) N
1523237 ALLEGRO_EDITOR SKILL SKILL function axlDBGetExtents() causing PCB Editor to crash' u G! s( F p
1523426 ALLEGRO_EDITOR DRC_CONSTR Dynamic shape not adjusted based on keepout; DRC generated9 y4 D5 B! l- N: m5 t# o
1524875 F2B PACKAGERXL Packaging using csnetlister fails, while manual packaging of individual blocks works fine
# b; D! ]9 t" H1 N0 ~1525432 CONSTRAINT_MGR OTHER User-defined property not being transferred from DE-HDL to PCB Editor4 A0 d' u+ \4 K H! o+ I. p
1525883 ADW DATABASE Invoking libimport on an existing DB should verify that the 'libimp_su' variable is set correctly
0 F9 E9 P4 D4 j& S1525948 F2B PACKAGERXL Reference designators assigned by the Packager tool are not correct
* M' m( ^8 }- E! O; [: M1526914 ADW LIBIMPORT Cannot import to new library database: o6 j# D+ f0 i- a1 g. B
1527321 ALLEGRO_EDITOR SCHEM_FTB Unable to create netlist with the 'Open Board in OrCAD PCB Editor' option in Hotfix 63' H. c) r4 B p& e5 e1 Q- d
1528075 CONCEPT_HDL OTHER Auto Generate: DML model assignment fails with error 'There is PHYS_DES_PREFIX property in PTF file.'
1 S$ ~# }! ]' S1528235 ADW DBEDITOR Running rule 'Validate Classification Property and Property Values' results in property mismatch error
& D* P+ Z$ k7 B; ?3 Q1528254 CONSTRAINT_MGR CONCEPT_HDL Import Logic with the 'Overwrite current constraints' option is deleting some attributes: m B" _; a# Z! M
1528398 ALLEGRO_EDITOR SCHEM_FTB Netlisting of pins with NC property results in error6 h9 R: V# I8 j5 Q* S+ @+ t
1528479 ADW LRM LRM crashes when opened on a lower-level block in a hierarchical design
1 ~0 Y8 _( M( G& {4 @1528894 ADW DBEDITOR Lack of PTF_SUBTYPE in the classification prevents the release of the part
+ }) _. u5 d$ s C( r! U2 c1529178 SIG_EXPLORER OTHER When an ECSet is created from a net, values are not transferred correctly for PinPairs
, k, G* ?4 K( X. [8 g% ]1 \( T" E$ G1529209 CONCEPT_HDL CORE When adding a component symbol version, the More option does not show all the versions1 n% R) ]4 a0 g
1529720 CONCEPT_HDL COPY_PROJECT Running ADW copy project does not update the 'master.tag' file
, r7 T& @& I0 r V1530445 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes when 'Add Connect' is used1 M6 |# B7 |1 l' s; d8 J( O
1530707 CONCEPT_HDL CORE Request to recover a 16.6 design after DE-HDL crashes4 t9 K; Q& {8 P
1531425 CONCEPT_HDL CORE DE-HDL crashing while trying to add a NetGroup
3 q- b. o% @' n. u1532865 CONCEPT_HDL CHECKPLUS Provide the ability for Rules Checker to report a GND symbol from the standard, and not our local library, in .mkr
, u0 ^! S! B* Q1533543 ADW DBEDITOR Component Browser free text search returns 2 parts when only 1 exists$ M/ n( C, P4 u
1536273 CONSTRAINT_MGR CONCEPT_HDL Model-defined differential pair is removed, and Constraint Manager Design Differences does not report an issue. b: f4 S9 k+ Y' T* |: C
1537055 CONCEPT_HDL CHECKPLUS Rules Checker - POWER_PINS value not obtained when schematic instance has the POWER_PINS and POWER_GROUP properties" k/ b6 Q5 L5 f/ e# m) y6 u
1537339 CONCEPT_HDL INTERFACE_DESIGN No warning is flagged when moving a Net Group over a net7 q- K( E; t* I5 s9 m# B. }8 d
1537521 FLOWS PROJMGR Do not allow project creation if there are spaces in directory or file names on the Linux platform: h7 A4 @ c5 v( z% |! b
1539077 ALLEGRO_EDITOR SYMBOL PCB Editor crashes when choosing 'Layout - Renumber Pins'7 X) \ a1 _0 j3 E4 T5 @
1539227 CONCEPT_HDL CORE Renaming a page from the hierarchy browser crashes the schematic editor.
^2 \" V* p) |: C; F% h1539997 ALLEGRO_EDITOR SKILL PCB Editor crashes when the axlStringRemoveSpaces() command is run
4 ]* D: p& a1 s1541532 SCM SCHGEN Generate Schematics crashes with 'Out of Memory' error( K0 W U- U0 j: N+ y5 C4 k' b
1541680 CONCEPT_HDL DOC A dot (.) or period in design name created 2 separate design folders in worklib
: e* _% I$ K9 L) C; }* u- z1542817 ALLEGRO_EDITOR DATABASE Import Netlist not getting completed on specific board3 c( L- @& V. d
1542949 ASDA EXPORT_PCB The Export to PCB Layout form: The file name specified in the 'Output Layout File' field is not accepted" m0 P6 s! H1 X$ V; `' e% D. z' c
1543537 ASDA NEW_PROJECT While creating new projects, the new folder name is not visible clearly in the explorer' i6 j2 B& P% \& V% d1 m* r
1544060 SCM SCHGEN Generate Schematics causes Allegro System Architect to crash! g* D. n- d- E# w
1544633 APD STREAM_IF The 'stream out' command causes Allegro Package Designer to crash
. P# |8 h5 i0 _' E/ ?1544698 ALLEGRO_EDITOR PLACEMENT 'place replicate' does not add clines and vias to fanouts if fanouts are marked
% ~3 p6 _& c/ G$ ?5 l) G( d1544856 ASDA CANVAS_EDIT Edit > Find places the process (UI) behind the SDA tool.
# @1 V% @" z+ M& V* P% D1545136 ALLEGRO_EDITOR PLACEMENT All fanouts are marked as part of one symbol instead of the symbols they attached with) Y, W6 |- s& R
1546062 ADW TDO-SHAREPOINT Failure to launch TDO Dashboard, need to update error message with more useful information$ s3 Y5 i" q3 y+ _* O$ g. z$ d
1549105 APD OTHER 'Stream out' fails with message: 'Request to terminate detected. Program aborted'
" h- Z7 _+ Z' z% @/ D1549658 ADW TDA An unmapped network folder in the Team Design Authoring option results in an error# ~1 o# _# r8 i0 G5 p( a
1550052 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes when copying symbols
* Y& c8 e6 W! X$ D: Z1551635 CAPTURE TCL_INTERFACE GetSelectedPMItems returns error for design cache objects$ D# J) ^$ Y1 e8 z5 P
1553027 ALLEGRO_EDITOR UI_GENERAL PCB Editor canvas stops responding for tasks such as resize and workspace switch
" S) L# j( [/ o# E+ A4 N! p1555246 ADW DBEDITOR Part Copy As does not copy AML and reliability model relations.
+ }" F: Y4 M k5 _1555254 ADW DBEDITOR Text in Free Text search box is removed if it loses focus
[/ e; B2 n9 V; [) [4 ?4 r) D1557542 ALLEGRO_EDITOR OTHER DXF export creates strange result for donut-shaped polygon4 L+ M: F% R5 d0 W
1573039 ALLEGRO_EDITOR INTERFACES IDX returns control to the general interface prematurely during an incremental IDX export) B% o( S/ Y% O
1580571 ADW DBEDITOR XML files continue to appear in flatlib even after the padstack/footprint models were released$ Q! N8 p5 ]2 q$ s; U: W
1580580 ADW LIBDISTRIBUTION The .lis file contains references to old models even after they were purged.
/ p6 J2 f4 X! w; L g1582064 ALLEGRO_EDITOR UI_GENERAL User-defined menus not working in PCB Editor 17.2
8 [: R; L/ V* U0 B( z! s" Y4 b1582628 ADW TDA When one user takes an update of physical object while the other user is still checking in the object, TDO crashes
1 \7 c# q, V+ Z- `7 Z1582856 PSPICE MODELEDITOR Getting 'ERROR: [S2C3471] Base part library does not exist when Export to Part Library', though olb is created5 i* f1 U" C; E# D4 e4 J7 ~
1584719 TDA CORE Caching errors are flagged for a board-ref project during block update0 R. ^( L. q- }3 {
1587045 CAPTURE IMPORT/EXPORT Unable to import PDF file
; e) p4 l7 A i1 a; S1587259 ALLEGRO_EDITOR UI_GENERAL axlUIMenuFind not working correctly for the 'bottom' option
; f" c, p/ r) C+ `1588736 PSPICE MODELEDITOR The Model Import wizard displays 'Invalid configuration' message when a .lib file is opened in Model Editor
: b. h/ r4 n% B1 [. g1588742 PSPICE PROBE Browse icon is missing from PSpice File - Export - text" {. \7 A1 y9 ^
1590006 ALLEGRO_EDITOR UI_GENERAL PCB Editor 17.2 crashes when multiple browse windows are opened
' |, m- X: x, M! a1590597 PSPICE PROBE Problem with the adaption in the Probe Window icons7 a8 ~( q" w* `" F+ k" y
1591264 ALLEGRO_EDITOR UI_GENERAL Film order in Visibility View is sorted alphabetically and does not match the manufacturing artwork5 r0 g- I/ s, x
1592089 PSPICE MODELEDITOR Cannot get the PSpice DMI Model DLL while using PSpice DMI Template Code Generator
+ b' [0 f9 d7 U3 E% J" `2 g1593436 ADW DBEDITOR Cursor does not automatically move to the model name cell when creating a new model
3 U4 F p/ o" x# L1594076 TDA CORE TDO crashes on concurrent check-ins when one of the blocks was not modified.% S5 p3 G( B* I6 q
1595987 ALLEGRO_EDITOR PLACEMENT Subclasses not getting updated in Placement Edit mode+ K) |$ j' ?0 P A. E8 }. Z$ s0 M
1596162 ASDA IMPORT_DEHDL_SHE Importing sheets from DE-HDL imports the block as well5 N- X/ w& Z7 L# H B
1597000 CONCEPT_HDL INTERFACE_DESIGN Renaming a NetGroup does not work if several segments of the NetGroup trace have the same netnames assigned.. F3 g- z! G: q3 r' O
1597406 ALLEGRO_EDITOR SHAPE Dynamic Shape does not void the traces and voids open areas
( h+ ?7 {* P" j! `% D8 Z9 b7 l1597957 ALLEGRO_EDITOR PLACEMENT Quickplace: placed and unplaced counts not getting updated) c f3 z1 V+ ^2 Z# E# n
1600194 ALLEGRO_EDITOR DRC_CONSTR 'drc update' gives a different DRC count each time the command is given in a multiple-cpu system
+ s; C" e8 Z( ~( |1600800 ALLEGRO_EDITOR GRAPHICS LINUX 17.2 operation of Update DRC is not the same as Windows – graphics not updating/ a1 N3 }& @- e8 L$ W4 S9 ]8 n
1602605 CONSTRAINT_MGR OTHER OrCAD: constraints not getting saved
4 Z0 g- C3 k6 v6 d4 C- q+ t4 C1602801 SIG_INTEGRITY OTHER Dielectric Warning message when opening SiP tool.
% L$ `2 e0 _3 Z8 {5 T1603377 PSPICE ENVIRONMENT Running simulation with the 'At Markers Only' option does not generate the .dat file
0 k, `) ^- P6 a4 I, t3 w e2 e1604166 CONSTRAINT_MGR CONCEPT_HDL Audit ECSets does not work from 'Referenced Electrical CSet' column header3 n" o/ M" `! v
1604741 ASDA CANVAS_EDIT Tcl console changes the present working directory when you open Project Preferences and close it.
4 F, r' O% \( `- H5 E. M! N/ C1605310 TDA CORE Join Project wizard: Random crashes in the Team Design Authoring option
- H* K3 G) b% c l' Y- z7 X7 N1606861 CONCEPT_HDL CORE DE-HDL crashes on Linux during the Generate View operation
) M% ^0 _; M" k1606917 CONSTRAINT_MGR CONCEPT_HDL Importing tech file in DE-HDL Constraint Manager is creating a duplicate 'DEFAULT' cset
8 v# m# c6 y! a( j" H. {' {+ D1607157 ALLEGRO_EDITOR INTERACTIV Edit - Change allows lines to be copied to Cutout subclass, but that subclass requires closed polygons& \4 g5 r5 V$ n
1607330 CONCEPT_HDL CORE Variant view schematic PDF corrupted with attach_props set$ P2 ?# j3 ]( ?1 S/ ?: d
1607568 ALLEGRO_EDITOR NC PCB Editor shows wrong drill legend for Top-to-Top drill9 w q8 _" C: Y- F& b- v# ~
1607986 CONCEPT_HDL SKILL cnGetSetupProjFilePath: The SKILL routine does not deliver the full qualified path and name of the project in 17.2$ v; ?! ~' t, C/ y* E6 F$ Q
1608524 SIP_LAYOUT MANUFACTURING The Display Pin Text tool fails in the 16.6.073 version with a parseString error.( S) h9 K# P3 o+ Q' S0 I8 n
1609400 ASDA CANVAS_EDIT The 'Assign Differential Pair' right-click pop-up menu command should be grayed out when a single net is selected
4 `; F1 \5 H' X9 Z" J# G1609809 ALLEGRO_EDITOR UI_GENERAL Crash in Allegro PCB Designer version 17.2-2016 on Linux9 g; o5 P K3 ^: @: L& \! D9 e" A0 B7 ?
1609856 ALLEGRO_EDITOR ARTWORK Embedded paste and soldermask showing up in both top and bottom gerber files.
7 s% Q; e. n. B: j6 w( |; U ]1609922 CONCEPT_HDL INFRA Launching Model Assignment crashes DE-HDL when the temp/edbDump.txt is read-only
) H7 E9 O- c( d6 g% s3 L1611226 ALLEGRO_EDITOR SYMBOL PCB Editor gives a crash message while saving a flash symbol; Q# {* e1 G7 ]8 E4 q) e
1612108 ALLEGRO_EDITOR OTHER Netlist Import is crashing with the .SAV message.
! T" [. q, b# F J( E) f1613123 ALLEGRO_EDITOR SKILL DrillType for Oval Slot should be 'OVAL_SLOT' not 'OVAL SLOT'8 B3 j7 G0 v! j0 Z: b
1614000 ADW LIBDISTRIBUTION Library distribution (lib_dist) does not complete; lib_dist.lck cannot be deleted when Configuration Manager is running$ W9 l9 H1 {. m$ @( z1 j
1614667 SIG_INTEGRITY SIMULATION Different results from Probe in Allegro Sigrity SI and SigXplorer* C2 \& O$ {$ K7 m9 o& ]
1615601 GRE IFP_INTERACTIVE Delete Bundle then try to delete plan lines results in fatal error
9 o$ A5 H2 x# g; s' T0 T/ M7 n9 e/ ?1616235 ORBITIO ALLEGRO_SIP_IF oio2sip import does not map layers correctly
6 |6 l6 }9 g- v5 E# Y1616540 SIP_LAYOUT DRC_CONSTRAINTS Same net DRC Line-to-Line reappearing after dyn shape update& R, G) ?4 Y" W
1616733 ALLEGRO_EDITOR INTERFACES 'genrad output' no longer working in 17.2. Gives the Error 'extracta process failed. Command terminated'
( t( L w% _; L5 C* P+ o- f9 h1618751 ASDA DRC Zero Node Net errors flagged when DRC checks are run, though RETAIN_ZERONODE_NET is set to 'NO' in Site CPM file
$ ]4 d, s( j1 [% m1618797 ADW FLOW_MGR Flow Manager cannot execute a specific command in 17.2.
: w V: j V; N9 k9 B1618930 CONSTRAINT_MGR INTERACTIV Hovering over row column cell causes the application to go into a not responding state.
) M4 }" o" X' A5 U" J1620350 ASDA EDIT_OPERATIONS Pin number is lost on updating the version of a connector pin
! J- j9 ~, p# x* o. n1621963 ASDA SELECTION_FILTER Selection filter: Pins in the symbol used in connectors are not selected
# H, [$ `2 b. \: h* k1622715 CONCEPT_HDL CONSTRAINT_MGR Extracting an XNet crashes DE-HDL
: o, @/ T6 w: r1625209 ASDA IMPORT_PCB File Import from PCB Editor shows board differences9 q3 j9 p( b. A
8 ^" \) g2 E7 K+ `) C Z# Z) `1 s$ e+ |( U
Fixed CCRs: SPB 17.2 HF003* ?* C# x# R3 ^& y9 s" l
07-28-2016
) H/ C. [5 c1 y8 e: V5 v6 b===================================================================================================================================
% _8 u+ E3 i m$ PCCRID PRODUCT PRODUCTLEVEL2 TITLE
. _5 t3 [2 m7 ~* [1 e* o===================================================================================================================================) k/ F/ ]8 Z$ X4 U
1423889 ALLEGRO_EDITOR EDIT_ETCH AiDT gets poor routing result* g( c9 p2 K7 V K
1461626 CONCEPT_HDL CREFER Cross-references shown to the same pin on different block instances though the signal names differ0 F e9 m: ?# M: H6 X* c
1472456 CONCEPT_HDL CORE The design connectivity (XCON) file and design data are not in sync
5 o$ _( W# h" R& e+ W. X6 o1546151 CONCEPT_HDL CORE Add port, Genview, move pin on block - the pin name disappears
6 d2 O0 d' S. E% P1547356 ALLEGRO_EDITOR EDIT_ETCH AiDT gives different results in ISR S034 and S066 w1 v) c9 g% e. `/ H m
1560102 ADW FLOW_MGR Flow Manager: None of the eval commands working: a3 ~- s5 [% @0 m
1570032 ALLEGRO_EDITOR GRAPHICS 3D Viewer shows flat LED for a specific design% B6 e; l3 o2 @6 D% X
1574676 ORBITIO ALLEGRO_SIP_IF Updating the OrbitIO database with a modified .sip file gives errors
1 E: B& Q! M' N7 |) S1578876 ADW ADWSERVER Component Browser crashes when trying to show details of a part number
8 r9 Q5 i3 H+ k1580744 F2B PACKAGERXL Running Export Physical results in error SPCODD-114# A9 r7 W9 \0 J/ ^4 i
1582863 CONCEPT_HDL CORE Generate View creates non-existent ports
" s$ E& q v% _+ U' T' g1584317 CONCEPT_HDL CORE Provide an option to open pxl.log from the Design Sync window when packaging does not complete successfully0 E" u' ]6 D2 _7 M' u) [+ y* j$ _
1587018 ADW FLOW_MGR User is prompted to specify the flow name each time the project is updated
/ O- p7 o: B2 E3 Z% k1587157 CONCEPT_HDL CONSTRAINT_MGR pstprop.net reports conflicts on nets with VOLTAGE properties# [5 f9 v% E4 K1 J) D6 B* |2 y
1587498 CONCEPT_HDL INTERFACE_DESIGN Need the ability to tap individual bus bits& E" [" H/ o D2 Y
1587718 ADW LIBIMPORT Library Import - The Pre-analyze tool does not report errors4 M& {8 `" i% Y3 S1 x1 U
1588197 ALLEGRO_EDITOR INTERFACES STEP export fails when External copper is selected on Windows 103 q) o; R$ w/ D5 F+ U4 z2 ^
1588786 ALLEGRO_EDITOR OTHER strip_design reports 'Design has been corrupted'/ u# u5 G6 H* i1 ^
1589252 CONCEPT_HDL CORE Search results zoom into the page origin instead of the selected components
3 Q# Y) t' j E+ o1589318 ALLEGRO_EDITOR DRC_CONSTR Via to SMD Fit DRC reported between embedded pin and via which do not share layers
# j% K g4 `' v% G# Q. j3 m5 t1589979 ADW FLOW_MGR Design Name change does not reflect in Flow Manager in the same session of a project
( O; m; I W& h# z3 d3 V+ f% ~# S1590538 CONCEPT_HDL DOC Open Archive: Some observations on the random behavior
% p/ h$ V5 l. b# Q F( v- ~1590639 CONCEPT_HDL OTHER Importing a design in DE-HDL results in a crash/ q) G% X/ q- f: n6 I! C4 P
1590651 CONCEPT_HDL INTERFACE_DESIGN DE-HDL: Duplicate NetGroups created in Interface Browser and Constraint Manager+ |9 Y4 I @7 {' L, y
1590720 ALLEGRO_EDITOR INTERFACES Exported Text Size Parameter file does not load names into the text table
0 W) Y. O$ H& F: B8 k! t2 @( t1591070 PSPICE PROBE PSpice crashes when using the Trace - Measurements - Evaluate command
7 b& i; f$ g: V: Y3 C+ z% l1591223 CONCEPT_HDL CORE Variant information for lower-level schematic not displayed
& K5 L; e4 z) V, l. Y; r1594240 CONCEPT_HDL ARCHIVER Archiver is not able to change the permissions of the cells archived0 F3 N6 s- @* ^" c/ f4 C
1594416 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor crashes when you create a new pad
1 W% k& ?( u# y& f3 T- k. h6 t; h1596615 ADW DBEDITOR Unable to search parts: Component Browser did not launch; Database Editor did not return search results
& r& x0 q& y/ C- Z$ _1596780 ALLEGRO_EDITOR SKILL PCB Editor crashes after doing SRM update and save! T" V3 y! r8 M* x# u
1597153 F2B DESIGNVARI ERROR SPCODD-53 in Variant Editor
$ a% J$ a. @' \: F/ [1597385 F2B DESIGNVARI Some 16.5 variant DNI parts appear in 16.6 as X-OUT and some without X-OUT or DNI
- G. ?7 h- f: `; o r1 s1598629 F2B PACKAGERXL Export Physical crashes after flagging error SPCOPK-14586 c6 j( w. I" G& V
1599452 ALLEGRO_EDITOR ARTWORK Import Artwork with Mirror option does not import pins or shapes6 J1 [: v8 a! o$ U5 q$ J% F
1599744 ADW FLOW_MGR Flow Manager: Commands associated with some of the buttons not working
+ |. I, @& Q; U/ f) W. R* m1599950 SCM OTHER Adding the GND net to parts/pins takes a long time.
( |3 f. G, }- }1 M. K1600226 RF_PCB AUTO_PLACE Fail to auto-place RF group5 D6 B+ N; a: n1 f( q
1600618 ALLEGRO_EDITOR DRC_CONSTR Casing of property names is affecting results when working with Physical Constraint Set9 v$ k5 R7 r9 L) q+ ^8 \8 k
1600914 ALLEGRO_EDITOR INTERFACES Exported PDF has unfilled shapes despite enabling the 'Filled Shapes' option: E; N3 l; ]. x% j8 ^
1601165 ALLEGRO_EDITOR DATABASE Thermal Relief is not added for Rounded Rectangle pad" w2 ^9 x3 S* L7 s4 C; ~
1601281 ALLEGRO_EDITOR OTHER STEP model link gets corrupted with SKILL axlLoadSymbol! Y; S* ]; e! O% u
1601282 ALLEGRO_EDITOR OTHER Export Libraries will not export device files when there is a space in the folder name." ]7 A" ^* }! I% I3 @5 |, q) @* R: b6 O% N
1602514 PCB_LIBRARIAN METADATA References to some primitives missing in block metadata;TDA errors reported for missing parts after joining a project3 _+ Y2 q; o% W' u1 K: X0 b
1602823 SIP_LAYOUT WIREBOND SiP crashes when using the Add Wire command! y# S) s F6 F7 i: ]
1602955 ALLEGRO_EDITOR SHAPE Shape to Route Keepout DRC not reported for attached database/ x3 M6 o$ `" [+ n- C. P
1604223 CONCEPT_HDL CORE Tool stops responding after error SPCOCD-553: Connectivity Server Error# S; Y, c2 @ k9 w* y8 w9 Z
1604746 ALLEGRO_EDITOR OTHER In 17.2, layer data is getting changed when importing extracta files into other thirty-party extraction tools
2 o# @/ _( A7 m# K+ Q; `9 [1605322 ALLEGRO_EDITOR TECHFILE Generating tech file in 17.2 takes much longer as compared to 16.67 t0 s' q8 t4 `2 E1 H
# Z/ T# F0 D) n, w; ]8 u$ \, v# H3 h: m$ h! S4 h; v
Fixed CCRs: SPB 17.2 HF002
0 e3 D5 F/ Z2 Q" [3 C2 l06-31-20168 l0 q9 ~& d4 G1 O
===================================================================================================================================: c& ]( l, F' w; w
CCRID PRODUCT PRODUCTLEVEL2 TITLE2 i) b& j6 z8 t+ k; Y9 y& k+ b
===================================================================================================================================: L$ ^* J- k3 F0 @& f- \
1452838 CONCEPT_HDL CORE Apparent discrepancy between Bus names and other nets( Q" E. Z" R5 l# O8 q" n8 \9 Q& Y
1469146 ADW LRM Packaging error reported after updating the design using LRM) V1 e: ^" Y( h; n9 U J
1481802 ORBITIO ALLEGRO_SIP_IF Import of an OrbitIO file to an existing SiP file offsets the results incorrectly" w, i4 T* D2 l( C9 g8 E0 R: v
1518957 APD SHAPE Shape void result incorrect r, G7 F, z; ]
1519155 ALLEGRO_EDITOR OTHER IPC-2581-B Negative Plane Error
$ g. V3 a2 V) O0 `1524947 SIG_INTEGRITY SIGNOISE Custom Stimulus is not recognized correctly in Allegro Sigrity SI or PCB SI.9 o6 I4 [0 l9 \( Y
1532162 CONCEPT_HDL CORE The Rename Signal command does not update split symbols.
9 E* P \; p; f8 t1543997 CONSTRAINT_MGR OTHER Import Logic is overwriting the constraints in the attached design." y4 x2 B7 @5 ^7 E
1544675 ALLEGRO_EDITOR OTHER Export Libraries corrupts symbols if paths do not include the current directory (.)
$ U' }8 N* E0 _7 x0 k! E1549097 CONSTRAINT_MGR XNET_DIFFPAIR Show warning message if differential pairs are created for nets with voltage properties9 ?/ K* T& E: p+ a9 J
1551934 ALLEGRO_EDITOR SKILL axlBackDrill command is not analyzing new layer set when application mode is set to 'None'
& m7 ~6 T1 [3 S1 G3 f! H6 u1554919 ADW LRM LRM does not find PTF data for cell 'res' in the reference library
W( [; J6 w: e1555009 CONCEPT_HDL INTERFACE_DESIGN Unable to rename a NetGroup.: w# a0 p6 Q6 s6 @6 @% T5 f
1559136 ALLEGRO_EDITOR EDIT_ETCH Cannot connect floating clines to vias with nets
, w; |' m* K6 L2 _1559552 SIP_LAYOUT ORBITIO_IF device offset in oio2sip translation6 b. o9 Q" C4 o. m* ^& }) t
1560301 CONCEPT_HDL CORE DE-HDL hangs when Edit menu commands are called on Linux if xclip is open
" k6 K4 o7 A0 W2 O, Q& K1560804 ALLEGRO_EDITOR OTHER Film records order gets reversed when using File - Import - Parameters after File - Export - Parameters
6 O+ G$ X# B5 M8 L! w1561501 ORBITIO OTHER OrbitIO stops responding when refreshing a design in SiP Layout
% ^: J5 {) F7 c' ?1564036 CONCEPT_HDL CORE User-defined custom variables are not getting populated in the TOC
) W" F7 J& [3 x P& f+ g1564545 CONCEPT_HDL OTHER Signal model property deleted from an instance is not deleted from the instance pins% X( L/ `1 {2 ^! o7 a8 z: U
1564552 CONCEPT_HDL CORE Find Net should zoom to the nets on schematic canvas
: f% }" f/ q* F1566119 CONCEPT_HDL CORE Right-clicking the schematic to add a component does not show all the schematic symbol versions6 [6 R; r4 y7 |! I! \' U9 m+ Z
1566848 ALLEGRO_EDITOR ARTWORK Board Outline artwork is incomplete
' \2 w- d" h N- N1566942 ASDA MISCELLANEOUS Several extra files in the /tmp/ folder on Linux
4 m, O6 d$ o0 Q3 h5 }1567290 ALLEGRO_EDITOR MANUFACT Import Artwork fails to import a shape.
0 ~0 K0 [ z$ q# H* S7 a0 ]% c/ |1567587 ALLEGRO_EDITOR MANUFACT Extended tool name in header of drill file is not correct
5 i& o' }- c9 k0 `% X1569056 CONCEPT_HDL CORE Opening the same drawing in multiple cascading windows view displays non-existent artifacts
0 i' m$ j: h2 v# s- i1569087 ALLEGRO_EDITOR DRC_CONSTR Running DRC Update gives the message 'Figure outside of drawing extents. Cannot continue.'
9 D5 ^+ j" K! z& \4 F1569147 CONCEPT_HDL CORE The signal name auto-complete drop-down list is not displayed correctly- \2 t; `* I9 G1 u9 u
1569394 ALLEGRO_EDITOR SKILL axlPadSuppressSet( 'on 1 '(via)) not working on SPB17.2' M) e5 _" R9 T# N4 g
1569924 CONCEPT_HDL CHECKPLUS Checking in a large BGA into ADW results in an error related to negative signals' D' c3 j- z7 U& B% ^
1570398 SIP_LAYOUT DATABASE Diestack layers cannot be deleted if there are unplaced symbols in the design
& Q+ `# U2 s9 A' N+ W% n1570419 CONSTRAINT_MGR CONCEPT_HDL Need to add a customized worksheet custom property weblink in Constraint Manager! X6 T" _; {9 C% e
1570624 APD ARTWORK Artwork file has missing voids on a layer and is causing a short+ r2 d, B2 S/ j) M- N/ c
1570678 F2B DESIGNVARI Variant Editor: Error when adding an RSTATE property
8 S* H$ P" g" Y0 C- L1571113 CONSTRAINT_MGR DATABASE Reports generated from cmDiffUtility show the differences in mm units only1 h+ ~! ^7 S6 ? |- ?5 @9 t
1572593 ALLEGRO_EDITOR ARTWORK ARTWORK: 'Draw holes only' option does not match display
$ R y- x" {/ w" I K+ y; z1573127 CONCEPT_HDL COPY_PROJECT The CopyProject functionality creates an incorrect 'view_pcb' directive value+ R, R: w& w! w8 h* P
1573205 CONCEPT_HDL CORE dsreportgen is unable to resolve the physical net names (PHYSNET)
/ l7 }( L) `* e) r4 x( U0 F1573625 CAPTURE PROJECT_MANAGER Toolbar customization is reset when Capture is re-invoked in SPB 17.2
5 ]' a6 T2 q1 A9 l, R5 _1573755 ALLEGRO_EDITOR CROSS_SECTION Changing a layer's type is also changing its material in Cross Section Editor
: r* l/ \. [/ v" k& v1573970 CONCEPT_HDL ARCHIVER archcore fails to archive the project CPM.arch file
/ y2 b' ^- b- G/ Y+ V( T1574381 CONCEPT_HDL OTHER Packager crashes on repackaging a design with RefDes related advanced settings/ K* m1 s' ]1 X7 e3 T3 n8 v
1576100 ALLEGRO_EDITOR SYMBOL Update symbol crashes, creates '.sav' file, but shows update was successful in 'refresh.log'' \- Z7 }- S- t# q% g) s i
1577381 CONCEPT_HDL CORE ERROR(SPCOCN-2128): The NetGroup structure does not match the PortGroup structure
7 O6 w9 L9 X. c1580103 ALLEGRO_EDITOR DATABASE dbstat of 16.6 does not recognize 17.X files
# t+ K/ C% `1 x% V4 _3 x; w q1580891 SCM REPORTS Dsreportgen crashes in different scenarios# K+ V5 a* r) z0 M5 L
1581254 SIP_LAYOUT CROSS_SECTION Cross Section Editor crashes when adding a layer. a# r T, R: A+ s, [4 u
1584957 ADW FLOW_MGR 17.2 Flow Manager, JavaScript - Tool Launch Error! ^0 D$ V6 F, D: L& g0 A
1588823 ADW FLOW_MGR Flow Manager: In 17.2, using back slashes in the UNC path results in problems in working with the tool9 q) F1 k$ N1 d; a& s
1590064 ADW LRM Allegro EDM Flow Manager - An empty LRM dialog opens on design load in 17.2) H5 D$ @5 d' h
/ l9 s9 h* C' \. q5 W& G1 \* z: ~4 b7 s
Fixed CCRs: SPB 17.2 HF001
" h1 I% [4 D* U05-06-2016
, @% T% e1 [. Y5 ]- x4 y. r===================================================================================================================================
" a0 k) @! \, S" ~8 zCCRID PRODUCT PRODUCTLEVEL2 TITLE2 c8 A! Y4 b) c; Y [ m2 ?' v1 h
===================================================================================================================================
" E7 }7 x4 T1 Z1272355 F2B DESIGNVARI Property changes on replaced component shows incorrect result in BOM output! D8 r. R D: w- e
1482953 ALLEGRO_EDITOR DATABASE Part change disassociates parts from Group
8 w" B) J H, T" ?1484075 ALLEGRO_EDITOR PADS_IN 'pads_in' imports ASSEMBLY_TOP and PLACE_BOUND_TOP outlines that are defined as shapes as lines' T/ N* l- v6 K" ]
1488909 ALLEGRO_EDITOR DRC_CONSTR Test Via causes net scheduling verification to fail* I; d! M( s% L
1498389 SIP_LAYOUT DIE_GENERATOR Provide the ability in the 'die in' command to specify flip chip as a DIE symbol
. `. ?. ]$ \! o! O1499515 ADW COMPONENT_BROWSE The Search Criteria property value is automatically being set in the ADW Component Browser
" a8 z6 X/ W1 `, b0 O i1 E, h1506672 ALLEGRO_EDITOR INTERACTIV In the attached board file, when using Replicate Place, some shapes are missing from some layers( i a+ T0 q2 ]6 M6 O" Z
1522411 FLOWS PROJMGR License selection should persist on invoking Layout from Project Manager
* @6 i) D' ^9 @1523532 F2B PACKAGERXL Adding subdesign names in the 'Use subdesign' or 'Force subdesign' sections hangs for more than a minute& j- q: J w6 O7 H) p9 f
1525783 CONCEPT_HDL CORE '\BASE' scope does not work for SYNONYMed global signals! t: |8 J9 p1 ^" T- X
1526729 SPIF OTHER Exporting a dsn file causes PCB Editor to crash in the interactive and batch modes
/ j$ g9 h3 [4 @, e& M, b' q1529846 ALLEGRO_EDITOR SHAPE Some shapes are not generated in the artwork
4 }6 o: K% o4 c- F1537499 CONCEPT_HDL CORE Adding the same version (already placed) with the same split block name should not be allowed
# a$ S0 L) h0 q, y) u3 q1541589 ALLEGRO_EDITOR INTERFACES STEP model incorrectly shown in 3D viewer. Shows pins as angled.+ J9 C- H4 V9 T# _' w5 I- Y% x0 ~
1542334 CONCEPT_HDL CREFER creferhdl leaving lock files in sch_1 folder
7 ?, a% g, z4 b1542722 ALLEGRO_EDITOR INTERFACES IDX export: RefDes and PART_NUMBER missing for mechanical symbols
+ T6 Z+ R/ u% o/ w2 t: D1543410 ADW LRM LRM shows confusing part status; reports that update is needed but clicking update does not work
/ A5 r) A6 P I/ R7 e1544614 ALLEGRO_EDITOR SKILL Associative dimension data reaches the 'psm' file despite deleting the layer on which it was set in the 'dra' file
7 m; @, U6 u! i% v. n9 r6 p1545370 APD OTHER Pads in .mdd file getting placed on different layers as compared to the design
. l* m. h! F$ J) b1545909 ALLEGRO_EDITOR UI_FORMS Show 'microvia' checkbox in 'Blind/Buried Vias' form only with the 'Allegro_PCB_Mini' license
. a/ z( B+ r5 |8 s, d- T1546141 ALLEGRO_EDITOR SHAPE Shapes missing from Artwork7 O- C+ O* x5 v. e) i/ x
1546877 CONCEPT_HDL CORE Align Left on wires fails with incorrect error message
1 \/ r7 ^2 {; [6 {1547224 CONCEPT_HDL CORE Lock the 'PATH' property once it is assigned by system
1 q S2 O) u% e ?1547584 SIP_LAYOUT OTHER SiP - Design Variant: Delete embedded layer if not selected6 Q6 Y$ n6 Y i6 K. G+ k9 {7 [4 X
1548116 CONCEPT_HDL CORE Some versions of Technology Independent Library do not appear when adding a symbol
( h, i5 U' O% z- t& q1548151 ALLEGRO_EDITOR INTERFACES Exporting a step file gives a component rotation mismatch in the *.stp file7 h7 F$ t0 v1 p, A) m
1548421 F2B BOM Parts with same 'BOM_IGNORE' set do not behave the same way in the BOM report: q# a( ]) V1 ?0 B7 P
1548978 ALLEGRO_EDITOR MANUFACT Shape not voiding clines- s- Q. N5 e. P# W
1549662 ALLEGRO_EDITOR OTHER Import Parameters Path fails if parampath does not have the current directory (.) set
8 w. d( R* Y6 Z/ V* x ]! Z& ]1549836 CONCEPT_HDL CORE Tools - Customize - Keys - Reset does not reset keyboard shortcuts9 D" C4 [! ~; B) ^" b
1550941 PCB_LIBRARIAN PTF_EDITOR PDV Part Table Editor new column sorting causing problems
0 q9 o; r; u4 U- S H6 X6 f+ t1551713 ALLEGRO_EDITOR DRC_CONSTR Hole to Hole DRC between via and pin not shown* [! s- K4 Z4 H
1553950 ALLEGRO_EDITOR SKILL Executing axlUIControl(pixel2UserUnits) crashes PCB Editor
- n. P, P, q# o: y1 s& k6 O1554333 CONCEPT_HDL CORE Changed connectivity error when aligning ports attached to NetGroups$ L. ?7 b) X- M
1555092 SIP_LAYOUT DEGASSING Degas offset is not working with hexagons3 b7 D p+ j+ J% v/ O/ i$ U
1556261 ALLEGRO_EDITOR DATABASE DBDoctor crashes with the error 'Illegal database pointer encountered, Exiting DBDOCTOR.'
" B' s8 V: o9 n. R% V- o4 u1557716 APD OTHER Stream out fails with request to terminate detected - Program aborted& X9 R3 t( T1 m$ B
1559951 SIP_LAYOUT SYMB_EDIT_APPMOD Wrong bump locations after Symbol Editor - Refresh co-design die
- U* ~& e& V2 g1560197 CONCEPT_HDL CORE BOM-HDL adds extra characters to subdesign_suffix when generating hierarchical BOM
7 j* f: Q& u2 Z" O: s8 q1561077 ALLEGRO_EDITOR INTERFACES Beta - IDX User Layer export fails on Linux
" U# c* S; i1 m% K' v4 w" C# ]! {1562537 ALLEGRO_EDITOR MENTOR Using mbs2brd in 16.6 gives a fatal error
, u( k( H- d! R/ }& e1564203 ALLEGRO_EDITOR ARTWORK Cannot generate negative artwork& A3 J- U& z1 |' A& e& H" p
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发表于 2019-11-5 13:54
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