|
|
EDA365欢迎您登录！
您需要 登录 才可以下载或查看，没有帐号？注册
x
AGM AG6K(mcu) SoC is targeted to high-volume, cost-sensitive, applications, enabling system designers to meet increasing peRFormance requirements while lowering costs. It is based on AGM SoC architecture. This device integrate one MCU core, AGM programmable logic, 12-bit ADC, 64Mbits SDRAM and 12Mbits SPI NOR FLASH in single device.; F. [, i$ n+ F9 i
- B2 `% R1 c6 o9 b% Z
$ H" u( y l0 [4 D
Features
9 c/ }8 P7 B( d- ` n# D$ J) z- x% f3 M
8 i) T& D- Z4 ~2 [8 hMCU Architecture:& f* O" X* s" s. j' p; n* S$ a
• One-core MCU: Working frequency up to 250 MHz# Y+ e/ g5 S2 a
• On-Chip Memory: 128Kbytes SRAM) Q7 i8 W! F, m' k9 }
• I/O Interfaces:
3 d9 P7 M7 g, r: `! x; w5 \• External AHB Slave Interface
6 K" p9 y' Y# d6 ~) w9 ]" ^( X• On-Chip Memory Access Ports0 W2 ]& k+ j$ u; N; l
• UART Interface% }7 n/ L U7 S' Q& \8 L _
• GPIOs0 L9 |3 z! Q8 p6 f: N; e d+ f. Q5 G
• JTAG Debug Ports
9 E4 J" X" i' p) H7 a9 R- h• SPI Flash Interface
3 V7 i. @! F! [+ ^; a7 D' B' ^• Interconnect: ARM AMBA® AHB based- M( c1 F$ U' v" s8 q
% f& f8 d3 y& r* B6 g; v! [
8 V5 L1 r8 s% |0 g" fSDRAM:
2 w+ q9 D# B0 Y1 w$ C• 16bits datawidth
* t- L2 X0 G' a5 l• 64Mbits capability9 P1 D) Q' C7 a! m, {8 T3 f
• up to 166MHz working frequency
2 ^0 j; g) n2 {* S5 M, m% Q: T% ]# W ^5 h
& D1 s" B7 x/ c/ x
SPI Flash:, ~' z* L5 W& k' B! D
• 12Mbits capability, v8 o& y( |2 ?# O: A. [2 ~8 H
% [( k" }; y2 o7 ?) g
8 W2 Q+ N" R# z/ C8 @* D8 z! g
Analog-to-Digital Converters（ADC）:7 G$ Q$ Q& {% t0 a7 V0 x" [' a" z
• 12bits accuracy t2 r" S- k0 l
• 1MHz sampling frequency
+ S8 |8 G% f( S( p8 S• On-chip temperature sensing+ A5 E: l* w- F2 a2 p
• Up to 10 channels (include internal temperature sensor channel)- J/ ^$ ~, L4 ^* E
$ ^5 l1 }6 m( |6 p( `
, B+ u( K" b$ [5 x) f5 K1 xFPGA Architecture:* ^, A' _- Y6 E/ c
• High-density architecture with 6K LEs# V: e5 n' m) i9 E: E% m
• M9K embedded memory blocks, up to 504 Kbits of RAM space/ I+ v7 v& X$ V/ C: n
• Up to 56 18 x 18-bit embedded multipliers are each configurable as two independent 9 x 9-bit multipliers1 e' f7 ^; d3 ?2 Q; I$ x
• Provides 4 PLLs per device provide clock multiplication and phase shifting
( g+ J( j- x+ |! D. m. k4 l• High-speed differential I/O standard support, including LVDS, RSDS, mini-LVDS, LVPECL/ P/ a5 ~1 v- q3 ~6 i
• Support DDR, DDR2
; A$ G, m7 l" [5 }6 C: |& ]• Single-ended I/O standard support, including 3.3V, 2.5V, 1.8V, and 1.5V LVCMOS and LVTTL3 D* D2 B; l( K6 T
• Flexible device configuration mode: JTAG and AS, PS
! e ^: q! @' c: D/ ?3 e. B( m• Support remote update, by “dual-boot” like implementation
0 a2 g- U. K# `3 ]5 P9 b4 |4 W7 B, F) Z d) d1 |
2 m5 D; @' k- O5 _2 \$ B& ?& b* p, f% ]
. d$ T) Y& p. J/ t! f
5 R/ {) y% {3 ~: `" T4 O; d
# s) w9 U6 ~& H+ ]
4 z5 t" z! E" P) O/ d
$ R' Q$ p( k& \2 T# N8 t$ L2 w- W9 ^ |
|
/1 
发表于 2019-8-5 14:34
收藏
淘帖
支持！
反对！