AGM CPLD Family

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General Description
) T% r8 @1 n  H% b# eAGM cpld family provides low-cost instant-on, non-volatile CPLDs, with densities from 256, 272 to 576 logic LUTs and
) s3 m7 ~- i8 M; qnon-volatile flash storage of 256Kbits. The devices offer up to 144 I/O pins featuring with a user flash memory (UFM), and
( H4 Q. L6 C0 q0 t4 fin-system programming. The devices are designed to reduce cost and power while providing programmable solutions for a
wide range of applications.
Features
 Low-Cost and low-power CPLD
 Instant-on, non-volatile Compatible FPGA architecture.
 Up to 4 global clock lines in the global clock network that drive throughout the entire device.
7 g# M/ S# X& {: o! s/ R1 d Provides programmable fast propagation delay and clock-to-output times.
* t5 m# c% m! f/ q1 V4 [; t Provides PLL per device provide clock multiplication and phaseshifting (AG256 has no PLL).
 UFM supports non-volatile storage up to 256 Kbits.
 Supports 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic level
 Programmable slew rate, drive strength, bus-hold, programmable pull-up resistors, open-drain output, Schmitt triggers and programmable input delay.
 Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry complaint with IEEE Std. 1149.1-1990
1 t2 I& W  K  b  L. Q$ t ISP circuitry compliant with IEEE Std. 1532
# q! X% T+ v! d8 h5 O 3.3-V, 2.5-V, 1.8-V, 1.5-V LVCMOS and LVTTL standards
 Emulated LVDS output (LVDS_E_3R)
 Emulated RSDS output (RSDS_E_3R)
' C8 g, `- K3 L* Q; c2 w1 E Operating junction temperature from -40 to 100 ℃

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9 V$ Q9 g5 ^+ q: W8 ]
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/ J2 P" o* ]. a3 C' v100 or 144 Pins for 256/272/576 LUTs




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