看一下AGM FPGA，pin to pin兼容Altera

mytomorrow

AGM FPGA，pin to pin兼容Altera
国内最好的FPGA，有cpld，FPGA等多种规格器件
) r/ [3 o# R: q0 ^  v4 z6 [目前大尺寸LED控制，大屏控制器，小屏驱动器应用领域巨大
完美兼容Altera
EPM240T100系列；EPM570T100系列；EPM576T144系列
( ?; B4 P6 X1 N* E. y" v0 L) ?EP3C5E144
EP3CE6E22
EP3C5F256
EP4CE6F17
' _' r3 t* m: G2 |EP3C10E144
2 x: R& Q( p2 S  bEP4CE10E22
EP3C16F256
EP4CE15F17
5 l2 v) U% V1 G+ T8 @( D, L中国芯，民族魂
0 J( K" z6 }) Z" r9 l: J5 |0 f

0 G! Q# Y+ w3 A& }" W- WAG256 CPLDs is the low cost CPLDs. This instant-on, non-volatile CPLD family targets general-purpose and low-density logic. The logic density is 256 Logic Elements with LQFP-100 package.
  ]4 I, S6 P! @- v- z0 M
! [. }, U8 g2 Q7 q& A  l5 K/ N
Low-Cost and low-power CPLD
Instant-on, non-volatile standard compatible architecture.
  r7 W: W  ]* ]0 ~2 Z- cUp to 4 global clock lines in the global clock network that drive throughout the entire device.
Provides programmable fast propagation delay and clock-to-output times.
UFM supports non-volatile storage up to 256 Kbits.
9 c2 ]4 A# v0 q' d3 u- PSupports 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic level
Programmable slew rate, drive strength, bus-hold, programmable pull-up resistors, open-drain output, Schmitt triggers and programmable input delay.
/ q( [. c( V. O6 _7 Y) p% \7 pBuilt-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry complaint with IEEE Std. 1149.1-1990
ISP circuitry compliant with IEEE Std. 1532
) J' D4 n/ X: `& J; v; w. @3 M3.3-V, 2.5-V, 1.8-V, 1.5-V LVCMOS and LVTTL standards
% c2 k6 k1 r4 B' `$ `5 u6 `Emulated LVDS output (LVDS_E_3R)
/ ^: T. ]1 I; ^+ G& [Emulated RSDS output (RSDS_E_3R)

3 P; B" z) x$ I6 [8 |4 {& S; k! |

! g5 S6 D. Y* C! `/ w

& `, {8 [& ?6 C% y( ?
# ]* [% S# t, X: ]) X% o

kinidrily

谢谢分享