FPGA错误总结

pulbieup

1. 设计顶层测试文件时报错误！

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- V# b' E% f  }. [3 ]Started : "Behavioral Check Syntax".
" H1 ^# G# c) `% q, GDetermining files marked for global include in the design...
- }+ P; U" B$ _2 z, L* a" pRunning vlogcomp...
8 `6 I/ K' M- e; uCommand Line: vlogcomp -work isim_temp -intstyle ise -prj {E:/FPGA Projects/Test1/TestFig_stx_beh.prj}
Determining compilation order of HDL files
% ~/ v4 t  z/ r) ~- SAnalyzing Verilog file "E:/FPGA Projects/Test1/Source/Module1.v" into library isim_temp
' e) q' ?  o/ Q# ~0 NERROR:HDLCompiler:806 - "E:/FPGA Projects/Test1/Source/Module1.v" Line 1: Syntax error near " ".
WARNING:HDLCompiler:1591 - "E:/FPGA Projects/Test1/Source/Module1.v" Line 1: Root scope declaration is not allowed in verilog 95/2K mode
Verilog file E:/FPGA Projects/Test1/Source/Module1.v ignored due to errors

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Process "Behavioral Check Syntax" failed
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% @) r/ [5 c# {) O5 [- q& @Process "Behavioral Check Syntax" failed


- D+ l( O9 d6 K& W8 G, H( Z找了各种方法，查了各种语法，无果。。。
最后问题找到：语法没写错，公司电脑ISE软件加密问题！！！坑爹。。
& V! m3 e- I  V1 q* T- v( J% z果断弃之，在外部编辑器中写代码！


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) T& {, y$ K$ i# R% W! n2. 报错：Signal count[24] in unit led1 is connected to following multiple drivers:
  B0 F2 `$ m7 x   原因：在多个always块里对同一个reg型变量进行赋值；
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3. 报错：Port connections cannot be mixed ordered and named
  原因：语法问题，查找！ 比如实例化时 少了.
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relchhiclty

还有记录，好习惯啊