Verilog锁存器，锁存6组数据后为什么读取时第一组数据为什么是锁存的第二组数据？？？

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Verilog锁存器，锁存6组数据后为什么读取时第一组数据为什么是锁存的第二组数据？？？

/ t; T' f9 _1 C$ a) i7 t  s

/* en为使能端，get为锁存/显示数据按键，rst为置零按键 */
module suocun(

en,get,rst,s1_1,s2_1,s3_1,s1_2,s2_2,s3_2,key,n1_1,n2_1,n3_1,n1_2,n2_2,n3_2

);

input en,get,rst;
input [3:0] s1_1,s2_1,s3_1,s1_2,s2_2,s3_2;

output reg key;
output reg[3:0] n1_1,n2_1,n3_1,n1_2,n2_2,n3_2;

reg[2:0] cnt1;
reg[2:0] cnt2;

reg[3:0] data1_1_1,data1_1_2,data1_2_1,data1_2_2,data1_3_1,data1_3_2;
reg[3:0] data2_1_1,data2_1_2,data2_2_1,data2_2_2,data2_3_1,data2_3_2;
reg[3:0] data3_1_1,data3_1_2,data3_2_1,data3_2_2,data3_3_1,data3_3_2;
reg[3:0] data4_1_1,data4_1_2,data4_2_1,data4_2_2,data4_3_1,data4_3_2;
: y9 o' G7 V- Freg[3:0] data5_1_1,data5_1_2,data5_2_1,data5_2_2,data5_3_1,data5_3_2;
$ }2 A8 R7 V% [reg[3:0] data6_1_1,data6_1_2,data6_2_1,data6_2_2,data6_3_1,data6_3_2;

always @(posedge get or negedge rst)
' K  R7 o" q' N* H! R$ ubegin
if(!rst)
begin
- r4 w- n( G& f6 ]cnt1<=3'd0;
cnt2<=3'd0;
+ `: }  C0 T# Qend
8 o* K4 w0 \( H3 ]# P6 y5 kelse
begin
; a# p. h  c- D3 v8 W8 n2 cif(en)
3 C' u: P2 Z7 y% |) J' ~& I8 Pbegin
) z# p* m) o  g0 f3 vif(cnt1==3'd7)
cnt1<=3'd0;
8 O& V. K9 y7 U& y2 F2 _else
( r/ z) J1 e  \: Q+ f+ j( jcnt1<=cnt1+1'b1;
! T5 N3 q* M/ V( z  E/ f# \end
else
begin
0 y+ h, x+ x* c& _if(cnt2==3'd7)
7 h% S' ~4 N' Q) y" Zcnt2<=3'd0;
& l; [/ ~7 P2 C% W: s  ?8 R9 Jelse
cnt2<=cnt2+1'b1;
2 x1 t2 ^$ e# [* @end
end
end

always @(*)
begin
& q9 v5 c3 o/ gif(!rst)
  a0 G% ^# ]. f8 Jbegin
) M2 B, T5 Z0 K7 ^, T5 }# Odata1_1_1<=0;data1_1_2<=0;data1_2_1<=0;data1_2_2<=0;data1_3_1<=0;data1_3_2<=0;
data2_1_1<=0;data2_1_2<=0;data2_2_1<=0;data2_2_2<=0;data2_3_1<=0;data2_3_2<=0;
data3_1_1<=0;data3_1_2<=0;data3_2_1<=0;data3_2_2<=0;data3_3_1<=0;data3_3_2<=0;
3 V& A5 @+ m) U0 \- d$ odata4_1_1<=0;data4_1_2<=0;data4_2_1<=0;data4_2_2<=0;data4_3_1<=0;data4_3_2<=0;
7 W3 I, C9 A! P0 q- wdata5_1_1<=0;data5_1_2<=0;data5_2_1<=0;data5_2_2<=0;data5_3_1<=0;data5_3_2<=0;
+ g: u5 _% L( Q7 j- [4 s! ]data6_1_1<=0;data6_1_2<=0;data6_2_1<=0;data6_2_2<=0;data6_3_1<=0;data6_3_2<=0;
! ^+ U! X  _! \: D2 [2 i% ^end
! {& G& J/ N: G7 ?$ M( |else
begin
if(en)
4 L' h6 n3 d$ n& W2 y5 xbegin
case(cnt1)
4 a9 ^# A$ e8 f0 B6 ~/ g3'd1:
$ ?6 ]3 r3 ~! U. r3 A' Gbegin
9 O* ^' [0 o/ o! u  ~7 mdata1_1_1<=s1_1;data1_1_2<=s1_2;data1_2_1<=s2_1;
data1_2_2<=s2_2;data1_3_1<=s3_1;data1_3_2<=s3_2;
+ x- s. m5 g- E9 Qend
3'd2:
% i, v6 c, ]; r+ Xbegin
data2_1_1<=s1_1;data2_1_2<=s1_2;data2_2_1<=s2_1;
+ ~* Q8 Z. W. J* s. L( A2 Tdata2_2_2<=s2_2;data2_3_1<=s3_1;data2_3_2<=s3_2;
end
3'd3:
7 _! [2 I4 v* K* }  P4 kbegin
. o1 K- f+ c( n$ I' K: M' _data3_1_1<=s1_1;data3_1_2<=s1_2;data3_2_1<=s2_1;
9 z! I& p2 [4 {1 h; h% F9 Mdata3_2_2<=s2_2;data3_3_1<=s3_1;data3_3_2<=s3_2;
& t6 s$ c& \. F5 Zend
3'd4:
% Y6 b- |  O6 b: v' w, X! Y& A; pbegin
. m- f! }* u6 L+ a" y0 F4 Q. wdata4_1_1<=s1_1;data4_1_2<=s1_2;data4_2_1<=s2_1;
data4_2_2<=s2_2;data4_3_1<=s3_1;data4_3_2<=s3_2;
end
3'd5:
begin
6 [( }1 c8 U$ e2 k% c: i  Ddata5_1_1<=s1_1;data5_1_2<=s1_2;data5_2_1<=s2_1;
data5_2_2<=s2_2;data5_3_1<=s3_1;data5_3_2<=s3_2;
end
# @& m& {( p( j4 _) k3'd6:
begin
data6_1_1<=s1_1;data6_1_2<=s1_2;data6_2_1<=s2_1;
data6_2_2<=s2_2;data6_3_1<=s3_1;data6_3_2<=s3_2;
2 d. V5 n1 o. y/ x6 `2 T3 Tend
default: ;
/ l7 ]7 t5 A& c( n$ p6 f4 \endcase
end
end
7 J" |: T# t) D% a! |$ E+ n& Pend

always @(*)
; a3 J2 M7 V6 l% @  z8 ^; o, S0 ebegin
if(!en)
8 r  n- @/ V. ibegin
case(cnt2)
3'd1:
begin
1 N6 X4 @9 o$ Y' _/ d4 v8 w' cn1_1<=data1_1_1;n1_2<=data1_1_2;n2_1<=data1_2_1;
n2_2<=data1_2_2;n3_1<=data1_3_1;n3_2<=data1_3_2;
end
3'd2:
begin
" h. ?; o4 ?: r, j" |: In1_1<=data2_1_1;n1_2<=data2_1_2;n2_1<=data2_2_1;
- c# b; ?0 u2 B1 On2_2<=data2_2_2;n3_1<=data2_3_1;n3_2<=data2_3_2;
0 F! D  `* x" [end
4 |- _! H, G' P) i5 Q2 Q3'd3:
8 \7 I/ |& @) ^begin
n1_1<=data3_1_1;n1_2<=data3_1_2;n2_1<=data3_2_1;
6 y8 p5 \1 q; Nn2_2<=data3_2_2;n3_1<=data3_3_1;n3_2<=data3_3_2;
end
3'd4:
5 q  l& Z5 u& ~9 K: ]7 V8 Ibegin
n1_1<=data4_1_1;n1_2<=data4_1_2;n2_1<=data4_2_1;
/ Q# a4 E; u' \+ wn2_2<=data4_2_2;n3_1<=data4_3_1;n3_2<=data4_3_2;
5 W' l2 v: Q8 \3 k  Xend
5 c6 Z' u9 Y0 ?* i1 T* g3'd5:
begin
. L9 f# `" J0 E/ h% fn1_1<=data5_1_1;n1_2<=data5_1_2;n2_1<=data5_2_1;
n2_2<=data5_2_2;n3_1<=data5_3_1;n3_2<=data5_3_2;
1 Q6 r- F- h+ O1 I6 p3 kend
; T# Y4 `1 U# c; F3'd6:
begin
9 R& B/ S2 E/ @  }n1_1<=data6_1_1;n1_2<=data5_1_2;n2_1<=data6_2_1;
- G2 M8 Y* R, M! D* g) o2 @n2_2<=data6_2_2;n3_1<=data5_3_1;n3_2<=data6_3_2;
% Y& Q: v! S0 v- G$ h$ send
' u5 n! D( G" e, t. edefault:
$ Q4 f0 c9 e+ ?9 K+ Fbegin
n1_1<=s1_1;n1_2<=s1_2;n2_1<=s2_1;
3 q. K. q: m$ G; tn2_2<=s2_2;n3_1<=s3_1;n3_2<=s3_2;
end
0 S, V9 A! V2 G* r2 ?" U8 Y! Aendcase
end
else
begin
, m' Z' v$ w* }n1_1<=s1_1;n1_2<=s1_2;n2_1<=s2_1;
4 x5 V/ i9 X: @5 On2_2<=s2_2;n3_1<=s3_1;n3_2<=s3_2;
& `8 k) p! x! oend
end

always @(*)
3 D/ W4 }7 {$ x% I, o, t. n5 L8 ybegin
& n2 }8 B9 A3 w8 D, I# z5 T$ tif(cnt1==3'd5 || cnt2==3'd6)
key=1'd1;
else
key=1'd0;
5 t$ s2 L! S/ u! M3 Cend

endmodule

helendcany

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