FPGA ------- Buffer之BUFGP

thinkfunny

BUFGP
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用于驱动时钟或延长线的主要全局缓冲器


8 q+ b% U" o5 b: W- @% }3 [This design element is a primary global buffer that is used to distribute high fan-out clock or control signals throughout in FPGA devices. It is equivalent to an IBUFG driving a BUFG.
( t6 N+ e' X5 j  O) k4 uThis design element provides direct access to Configurable Logic Block (CLB) and Input Output Block (IOB) clock pins and limited access to other CLB inputs. The input to a BUFGP comes only from a dedicated IOB.
4 e4 ?0 a& J$ Q! ~: S! kBecause of its structure, this element can always access a clock pin directly. However, it can access only one of the F3, G1, C3, or C1 pins, depending on the corner in which the BUFGP is placed. When the required pin cannot be accessed directly from the vertical line, PAR feeds the signal through another CLB and uses general purpose routing to access the load pin.
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fanichicl

这是英文版的？