FPGA ------- Buffer之BUFGMUX and BUFGMUX_1

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BUFGMUX and BUFGMUX_1
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9 Q/ d" N) ^9 k# [, q" JBUFGMUX is a multiplexed global clock buffer that can select between two input clocks: I0 and I1. When the select input (S) is Low, the signal on I0 is selected for output (O). When the select input (S) is High, the signal on I1 is selected for output.
, y4 b3 d$ t; P( Z. VBUFGMUX and BUFGMUX_1 are distinguished by the state the output assumes when that output switches between clocks in response to a change in its select input. BUGFMUX assumes output state 0 and BUFGMUX_1 assumes output state 1.

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