错误如下:
( H1 W$ K" ^# B, YError (10839): Verilog HDL error at TEST.v(26): using implicit port connections is a SystemVerilog feature
+ N! J4 `; n9 f代码如下:
1 {( V- U% x- n* L2 M/ r6 Qmodule TEST9 C: f3 @4 Q" N
(9 _5 d4 Z0 e' A
phase_a,
* l' O% Z- h6 s" Y! B& j, rphase_b,
8 U1 I5 J7 y; F4 F7 V( j& Y& ~7 w( s8 r2 U
dq,
, b, g! m) Q3 a- u- J! ^% k5 ^);
input phase_a;
* ~, \0 ^- J) ^3 E. r) K+ O$ }input phase_b;8 y2 G5 e D7 p+ z* ]6 s* d
inout [15:0] dq;
DECODER(8 d) C4 [: B0 S% q# G
.reset(reset),3 [) p$ U6 }$ v; q" r
.enable(enable),
7 Z* {5 k ^1 {/ t& W" O.phase_a(phase_a), ^ c4 G7 |& M' |
.phase_b(phase_b),
: i4 \" M M |1 s7 l& ~; g8 [9 U) f.counter(counter)" s ?1 A t! R4 ?
" ?( a4 }; h; G0 H) ~ Y
);
RAM(
! ]. _/ d& o1 {* i0 I' k) h% l7 n' G.dq(dq),9 ^; h9 Q9 N+ v& o
.address(address),- p$ K4 O4 z) a9 Z5 ^( K
.n_e(n_e),
2 z: z s2 t1 }" n+ k! a.n_w(n_w),
- e+ E, c! z$ ]' i) x.output_enable5 D8 a. @) y0 N+ k
);2 Z5 l, q* W, V* A, l1 [# j
endmodule