转——ZRtech Altera CycloneIV FPGA开发板——计时时钟

Zedd · 发表于 2019-4-26 09:38

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转——ZRtech Altera CycloneIV FPGA开发板——计时时钟

本实验是用数码管显示一个计时时钟，由于数码管只有4位，所以只显示秒和分，时类似，由于控制数码管的段是复用的，所以每一时间只有选中的数码管才亮，其中左边两个数码管显示分，右边两个数码管显示秒。
1、同样新建工程，
2、本实验的代码如下：
//clock
module clock(clk,DS_EN4,DS_EN3,DS_EN2,DS_EN1,DS_A,DS_B,DS_C,DS_D,DS_E,DS_F,DS_G,DS_DP);

input clk;
output wire DS_EN4,DS_EN3,DS_EN2,DS_EN1;
output wire DS_A,DS_B,DS_C,DS_D,DS_E,DS_F,DS_G,DS_DP;

wire [3:0]wei;
wire [7:0]duan;
reg [3:0]wei_r;
reg [7:0]duan_r;

reg [5:0]Hour;
reg [5:0]Minute;
reg [5:0]Second;
reg [31:0]Cout;
reg Clk_En;
wire [3:0]Second_bit,Second_ten,Minute_bit,Minute_ten,Hour_bit,Hour_ten;

wire clk_1k,clk_1s;

assign {DS_EN1,DS_EN2,DS_EN3,DS_EN4}=wei;
assign {DS_DP,DS_G,DS_F,DS_E,DS_D,DS_C,DS_B,DS_A}=duan; //数码管共阴极

fp_k fp_1k(clk,clk_1k);
fp_s fp_1s(clk_1k,clk_1s);

initial
begin
  wei_r<=4'b0000;
  duan_r<=8'b00111111;
  Second<=5'd0;
  Minute<=5'd0;
  Hour<=5'd0;
end

always @(posedge clk_1s)
begin
  if(Second<59)
begin
Second<=Second+1;
end
  else if(Second==59)
begin
Second<=0;
if(Minute<59)
   begin
   Minute<=Minute+1;
   end
else if(Minute==59)
   begin
   Minute<=0;
   if(Hour<23)
   begin
      Hour<=Hour+1;
   end
   else if(Hour==23)
   begin
      Hour<=0;
   end
   end
end
end

binary_to_digit time1(clk,wei,Hour,Minute,Second,Second_bit,Second_ten,Minute_bit,Minute_ten,Hour_bit,Hour_ten,duan);

endmodule

//分频1k-----1s
module fp_s(clk_1k,clk_1s);
input clk_1k;
output reg clk_1s;
reg [10:0]cout;
//reg clk_en;
initial
begin
  cout<=10'd0;
  clk_1s<=1'd0;
end
always @(posedge clk_1k)
begin
  if(cout==10'd500)
begin
cout<=10'd0;
clk_1s<=~clk_1s;
end
  else
begin
cout<=cout+1;
end
  //clk_1s<=clk_en;
end

endmodule
//分频48M-----1k
module fp_k(clk,clk_1k);
input clk;
output reg clk_1k;
reg [31:0]cout;
//reg clk_en;
initial
begin
  cout<=32'd0;
  clk_1k<=1'd0;
end
always @(posedge clk)
begin
  if(cout==32'd24000)
begin
cout<=32'd0;
clk_1k<=~clk_1k;
end
  else
begin
cout<=cout+1;
end
  //clk_1s<=clk_en;
end

endmodule

module binary_to_digit(clk,wei_r,Hour,Minute,Second,Second_bit,Second_ten,Minute_bit,Minute_ten,Hour_bit,Hour_ten,HEX);
input clk;
output reg [3:0]wei_r;
input [5:0]Hour,Minute,Second;
output reg [3:0]Second_bit,Second_ten,Minute_bit,Minute_ten,Hour_bit,Hour_ten;
output reg [7:0]HEX;
wire clk_1k;
fp_s fp_1s(clk,clk_1k);
always @(posedge clk_1k)
begin
  Second_bit<=Second%10;
  Second_ten<=Second/10;
  Minute_bit<=Minute%10;
  Minute_ten<=Minute/10;
  Hour_bit<=Hour%10;
  Hour_ten<=Hour/10;
  if((Second_bit==4'd0)&&(Second_ten!=4'd0))
begin
wei_r<=4'b1101;
case(Second_ten)
   0: HEX=7'b00111111;
   1: HEX=7'b00000110;
   2: HEX=7'b01011011;
   3: HEX=7'b01001111;
   4: HEX=7'b01100110;
   5: HEX=7'b01101101;
   6: HEX=7'b01111101;
   7: HEX=7'b00000111;
   8: HEX=7'b01111111;
   9: HEX=7'b01101111;
   //a: HEX=7'b01110111;
   //b: HEX=7'b01111100;
   //c: HEX=7'b00111001;
   //d: HEX=7'b01011110;
   //e: HEX=7'b01111001;
   //f: HEX=7'b01110001;
   //default: HEX=7'b00000000;
endcase
end
  else if((Second_bit==4'd0)&&(Second_ten==4'd0)&&(Minute_bit!=4'd0))
begin
wei_r<=4'b1011;
case(Minute_bit)
   0: HEX=7'b00111111;
   1: HEX=7'b00000110;
   2: HEX=7'b01011011;
   3: HEX=7'b01001111;
   4: HEX=7'b01100110;
   5: HEX=7'b01101101;
   6: HEX=7'b01111101;
   7: HEX=7'b00000111;
   8: HEX=7'b01111111;
   9: HEX=7'b01101111;
   //a: HEX=7'b01110111;
   //b: HEX=7'b01111100;
   //c: HEX=7'b00111001;
   //d: HEX=7'b01011110;
   //e: HEX=7'b01111001;
   //f: HEX=7'b01110001;
   //default: HEX=7'b00000000;
endcase
end
  else if((Second_bit==4'd0)&&(Second_ten==4'd0)&&(Minute_bit==4'd0)&&(Minute_ten!=4'd0))
begin
wei_r<=4'b0111;
case(Minute_ten)
0: HEX=7'b00111111;
1: HEX=7'b00000110;
2: HEX=7'b01011011;
3: HEX=7'b01001111;
4: HEX=7'b01100110;
5: HEX=7'b01101101;
6: HEX=7'b01111101;
7: HEX=7'b00000111;
8: HEX=7'b01111111;
9: HEX=7'b01101111;
//a: HEX=7'b01110111;
//b: HEX=7'b01111100;
//c: HEX=7'b00111001;
//d: HEX=7'b01011110;
//e: HEX=7'b01111001;
//f: HEX=7'b01110001;
//default: HEX=7'b00000000;
endcase
end
  else
begin
wei_r<=4'b1110;
case(Second_bit)
   0: HEX=7'b00111111;
   1: HEX=7'b00000110;
   2: HEX=7'b01011011;
   3: HEX=7'b01001111;
   4: HEX=7'b01100110;
   5: HEX=7'b01101101;
   6: HEX=7'b01111101;
   7: HEX=7'b00000111;
   8: HEX=7'b01111111;
   9: HEX=7'b01101111;
   //a: HEX=7'b01110111;
   //b: HEX=7'b01111100;
   //c: HEX=7'b00111001;
   //d: HEX=7'b01011110;
   //e: HEX=7'b01111001;
   //f: HEX=7'b01110001;
   //default: HEX=7'b00000000;
endcase
end
end
endmodule

3、实验结果如下：

此图对应第8秒

此图对应第40秒

此图对应第1分钟

gaoxings · 发表于 2019-4-26 18:38

很棒的资料谢谢楼主分享

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转——ZRtech Altera CycloneIV FPGA开发板——计时时钟

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