求大神解释储物柜电子密码程序VHDL

ygcgsa · 发表于 2019-4-23 11:14

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity matrix is
port(       clk: in std_logic;
            row:in std_logic_vector(3 downto 0);
            col

ut std_logic_vector(3 downto 0);
keyout

ut std_logic_vector(3 downto 0);
flag

ut std_logic;
            clkreg: buffer std_logic
            );
end matrix;

architecture behave of matrix is
signal colreg:  std_logic_vector(3 downto 0);
signal con: std_logic_vector(7 downto 0);
signal cnt: std_logic_vector(2 downto 0) :="000";--(15 downto 0);
--signal clkreg: std_logic;

begin
process(clk)
begin
      if clk'event and clk = '1' then
            if cnt = "111" then--1100001101001111
                     cnt<="000";--"0000000000000000";
                     clkreg<='0';
            elsif cnt = "011" then--0110000110100111
                     cnt<=cnt+"001";--"0000000000000001";
                     clkreg<='1';
            else
                     cnt<=cnt+"001";--"0000000000000001";
            end if;
      end if;
end process;

process(clkreg)
      begin
      if clkreg'event and clkreg = '1' then
                     case colreg is
                              when "1110" => colreg<="1101";
                              when "1101" => colreg<="1011";
                              when "1011" => colreg<="0111";
                              when "0111" => colreg<="1110";
                              when others => colreg<="1110";
                     end case;
            end if;
end process;

col<=colreg;
con<= colreg & row;
process(clkreg)
begin
      if clkreg'event and clkreg = '1' then
            case con is
                     when "11101110" => keyout<="0000";flag<='1';--0
                     when "11011110" => keyout<="0001";flag<='1';--1
                     when "10111110" => keyout<="0010";flag<='1';--2
                     when "01111110" => keyout<="0011";flag<='1';--3
                     when "11101101" => keyout<="0100";flag<='1';--4
                     when "11011101" => keyout<="0101";flag<='1';--5
                     when "10111101" => keyout<="0110";flag<='1';--6
                     when "01111101" => keyout<="0111";flag<='1';--7
                     when "11101011" => keyout<="1000";flag<='1';--8
                     when "11011011" => keyout<="1001";flag<='1';--9
                     when "10111011" => keyout<="1010";flag<='1';--delete button,pull once delete one num;
                     when "01111011" => keyout<="1011";flag<='1';--clear button, pull this button will clear all num of ur input]
                     when "11100111" => flag<='0';--keyout<="1100";flag<='1';
                     when "11010111" => flag<='0';--keyout<="1101";flag<='1';
                     when "10110111" => flag<='0';--keyout<="1110";flag<='1';
                     when "01110111" => flag<='0';--keyout<="1111";flag<='1';
                     when "11101111" => flag<='0';
                     when "11011111" => flag<='0';
                     when "10111111" => flag<='0';
                     when "01111111" => flag<='0';
                     when others => flag<='0';
            end case;
      end if;
end process;

end behave;

fanichicl · 发表于 2019-4-23 17:16

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求大神解释储物柜电子密码程序VHDL

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