求助大神帮看看CPLD做SPI从的程序，非常感谢！

ygcgsa · 发表于 2019-4-22 10:45

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本帖最后由 ygcgsa 于 2019-4-22 11:16 编辑

我是用STM32和EPM240做SPI通信，STM32为主SPI,cpld为从SPI，8位通信，将always@(posedge CS_N or negedge rst_n) 下的
else
      begin
         txd_data <=txd_data+1'b1;
      end
换成 txd_data <=5'b11100;（固定赋值）或txd_data <=rxd_data，数据都可以正常传输给STM32，但是当换成txd_data+1'b1后，每次加的值都不对，我实测了几组数据大概如下：
1,5,9,13,17,22,24,27,30,16,35,38,41,46,48
1,5,9,13,17,22,24,27,30,16,35,39,42,47,51有一定的重复规律性
查了CS_N信号的边沿，也没有发现有多个上升沿，百思不得其解，情高手帮忙看看代码有没有问题

module spi(clk,rst_n,CS_N,SCK,MOSI,MISO,rxd_data);
input clk;             //CPLD时钟，50MHZ
input rst_n;
input CS_N;
input SCK;          //STM32发送的SPI时钟，实测周期2uS
input MOSI;
reg [7:0] txd_data;
output reg MISO;
reg [7:0] rxd_data;
output [7:0] rxd_data;

//-------------------------capture the sck-----------------------------
reg sck_r0,sck_r1;
wire sck_n,sck_p;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
      begin
         sck_r0 <= 1'b1; //sck of the idle state is high
         sck_r1 <= 1'b1;
      end
else
      begin
         sck_r0 <= SCK;
         sck_r1 <= sck_r0;
      end
end

assign sck_n = (~sck_r0 & sck_r1)? 1'b1:1'b0; //capture the sck down
assign sck_p = (~sck_r1 & sck_r0)? 1'b1:1'b0; //capture the sck up

//-----------------------spi_slaver read data-------------------------------
reg rxd_flag_r;
reg [2:0] rxd_state;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
      begin
         rxd_data <= 1'b0;
         rxd_flag_r <= 1'b0;
         rxd_state <= 1'b0;
      end
else if(sck_n && !CS_N)
      begin
         case(rxd_state)
            3'd0:begin
                     rxd_data[7] <= MOSI;
                     rxd_flag_r <= 1'b0;  //reset rxd_flag
                     rxd_state <= 3'd1;
                  end
            3'd1:begin
                     rxd_data[6] <= MOSI;
                     rxd_state <= 3'd2;
                  end
            3'd2:begin
                     rxd_data[5] <= MOSI;
                     rxd_state <= 3'd3;
                  end
            3'd3:begin
                     rxd_data[4] <= MOSI;
                     rxd_state <= 3'd4;
                  end
            3'd4:begin
                     rxd_data[3] <= MOSI;
                     rxd_state <= 3'd5;
                  end
            3'd5:begin
                     rxd_data[2] <= MOSI;
                     rxd_state <= 3'd6;
                  end
            3'd6:begin
                     rxd_data[1] <= MOSI;
                     rxd_state <= 3'd7;
                  end
            3'd7:begin
                     rxd_data[0] <= MOSI;
                     rxd_flag_r <= 1'b1;  //set rxd_flag
                     rxd_state <= 3'd0;
                  end
            default: ;
         endcase

      end
end
always@(posedge CS_N or negedge rst_n)       //当CPLD捕捉到SPI_CS信号的上升沿时，要给STM32发送的数据加1
begin
if(!rst_n)
      begin
         txd_data <= 1'b0;
      end
else
      begin
         txd_data <=txd_data+1'b1;
      end
end
//---------------------spi_slaver send data---------------------------
reg [2:0] txd_state;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
      begin
         txd_state <= 1'b0;
         MISO <=1'b0;

      end
else if(sck_p && !CS_N)
      begin
         case(txd_state)
            3'd0:begin
                     MISO <= txd_data[7];
                     txd_state <= 3'd1;
                  end
            3'd1:begin
                     MISO <= txd_data[6];
                     txd_state <= 3'd2;
                  end
            3'd2:begin
                     MISO <= txd_data[5];
                     txd_state <= 3'd3;
                  end
            3'd3:begin
                     MISO <= txd_data[4];
                     txd_state <= 3'd4;
                  end
            3'd4:begin
                     MISO <= txd_data[3];
                     txd_state <= 3'd5;
                  end
            3'd5:begin
                     MISO <= txd_data[2];
                     txd_state <= 3'd6;
                  end
            3'd6:begin
                     MISO <= txd_data[1];
                     txd_state <= 3'd7;
                  end
            3'd7:begin
                     MISO <= txd_data[0];
                     txd_state <= 3'd0;

                  end
            default: ;
         endcase
      end
else if(CS_N)
   begin
      MISO <=1'b0;
   end

end

endmodule

Demyar · 发表于 2019-4-22 17:36

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求助大神帮看看CPLD做SPI从的程序，非常感谢！

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