FPGA编程这些常见的错误终于会解决了(三)

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Quartus 常见警告和错误

1. Warning:        VHDLProcess  Statement warning at        random.vhd(18):        signal        reset is in
statement, but is not in sensitivity list
----        没把 singal        放到 process （）中

2. Warning: Found pins ing as undefined clocks and/or memory enables Info: Assuming node CLK is an undefined clock
-=-----        可能是说设计中产生的触发器没有使能端

3. Error:        VHDLInteRFace        Declaration        error        in        clk_gen.vhd(29):        interface object
"clk_scan" of mode out cannot be read. Change object mode to buffer or inout.
# w8 L4 H* l: O+ D$ E+ D$ o' q4 G------        信号类型设置不对，        out 当 作 buffer        来定义

4. Error:        Nodeinstance        "clk_gen1"        instantiates        undefined        entity        "clk_gen"
-------        引用的例化元件未定义实体－－        entity "clk_gen"

5. Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or
7 _9 C7 ]; ~( Ngated clocks -- node(s) analyzed as buffer(s) resulting in clock skew Info: Detected ripple clock "clk_gen:clk_gen1|clk_incr" as buffer Info: Detected ripple clock "clk_gen:clk_gen1|clk_scan" as buffer

6. Warning: VHDL Process Statement warning at ledmux.vhd(15): signal or variable
4 b; w9 ]7 F4 R0 G) v( x3 `"dataout" may not be assigned a new in every possible path through the Process
4 ^2 u" k% h. K1 P. k- vStatement.        Signal        or        variable        "dataout"        holds        its        previous        in        every        path with no
* C7 E% K( F9 k/ |3 @new assignment, which may create a combinational loop in the current design.

7. Warning:        VHDLProcess  Statement warning        at        divider_10.vhd(17):        signal "cnt" is
read inside the Process Statement but isn't in the Process Statement's sensivitity list
9 t5 g2 g" |" ~/ @! C-----        缺少敏感信号

8. Warning: No clock transition on "counter_bcd7:counter_counter_clk|q_sig[3]" register

" x) A$ i, F, y7 @7 ~' x% N) g

9. Warning:        Reducedregister        "counter_bcd7:counter_counter_clk|q_sig[3]" with
; ]; n6 x" E' |) ~7 _stuck clock port to stuck GND

10. Warning:        Circuit        may not        operate.        Detected        1 non-operational        path(s) clocked
by clock "class[1]" with clock skew larger than data delay. See Compilation
: A2 \" E- {$ GReport for details.

11. Warning:        Circuit        may not        operate.        Detected        1 non-operational        path(s) clocked
by clock "sign" with clock skew larger than data delay. See Compilation Report
, j* J# i3 }  x1 g$ Kfor details.

12. Error:        VHDLerror        at        counter_clk.vhd(90):        actual        port        "class"        of        mode "in"
cannot be associated with formal port "class" of mode "out"
------        两者不能连接起来

2 t, A% i- a) P1 p% o

13. Warning:        Ignored        node in        vector        source        file.        Can't        find        corresponding node
# O% v* d- S3 o! S+ \name "class_sig[2]" in design.
------        没有编写  testbench        文件，或者没有编辑输入变量的值        testbench        里是元件申明和映射

14. Error:        VHDLBinding        Indication        error        at        freqdetect_top.vhd(19):        port "class"
in design entity does not have std_logic_vector type that is specified for the
same generic in the associated component
& u3 M# @- m9 S; u5 y---        在相关的元件里没有当前文件所定义的类型

15. Error: VHDL error at tongbu.vhd(16): can't infer register for signal "gate"
because signal does not hold its outside clock edge

16. Warning: Found clock high time violation at 1000.0 ns on register "|fcounter|lpm_counter:temp_rtl_0|dffs[4]"

3 i) `5 [+ A& }: Z# x1 W! ?3 j9 ?' O

17. Warning: Compiler packed, optimized or synthesized away node "temp[19]".
6 F7 B1 e" j1 T  i* b: b8 LIgnored vector source file node.
4 g0 ^! Q, E9 z' h! f) X- F---"temp[19]"        被优化掉了

: s+ i) M: J' R+ c; m( N

18. Warning:        Reduced register        "gate~reg0"        with        stuck        data_in        port        to stuck GND

19. Warning: Design contains 2 input pin(s) that do not drive logic Warning: No output dependent on input pin "clk"
5 w2 _' F4 s+ h' bWarning: No output dependent on input pin "sign"
5 d9 T+ f: h* [- I. Y% p9 K------        输出信号与输入信号无关，

20. Warning: Found clock high time violation at 16625.0 ns on register "|impulcomp|gate1"

21. Error:        VHDLerror        at        impulcomp.vhd(19):        can't        implement        clock        enable condition specified using binary operator "or"

22. Error: VHDLAssociation List  error  at  period_counter.vhd(38):  actual parameter  assigned  to  formal  parameter  "alARM",  but  formal  parameter  is   not
# b' q( g* c) ^: t3 ^) z' m8 e) k& x5 Bdeclared
+ t/ }* @7 s! u$ K) l0 x% h-------        连接表错误， 形参"alarm"        赋值给实参， 形参没定义， 可能是形参与实参的位置颠倒了，规定形参在实参之前。

23. Error: Ignored construct behavier at period_counter.vhd(15) because of
' U3 J  {1 W# wprevious errors
2 _8 S: V: W6 m, r% g3 v) o4 z. c－－－－－－－－因为前一个错误而导致的错误

24. Error: VHDL error at period_counter.vhd(38): type of identifier "alarm" does
7 ?( x: j6 N% q- z' ^% knot agree with its usage as std_logic type
－－－－－－－－        "alarm" 的定义类型与使用的类型不一致

) q* g* e* [9 j9 E

25Error: VHDL error at shift_reg.vhd(24): can't synthesize logic for statement
with conditions that test for the edges of multiple clocks
$ z7 g8 f' B% K-------        同一进程中含有两个或多个        if(edge)        条件，（一个进程中之能有一个时钟沿）

26. Error: Can't resolve multiple constant drivers for net "datain_reg[22]" at
: {# B4 Z, S$ K2 T3 \$ Yshift_reg.vhd(19)

27. can't        infer        register        for        signal        "num[0]"        because signal        does not        hold its
2 B2 R2 T# Q7 U7 k0 F' g5 F- o9 Ioutside clock edge

28. Error: Can't elaborate top-level user hierarchy

' G$ L2 i- V  c/ t

29. Error: Can't resolve multiple constant drivers for net "cs_in" at led_key.vhd(32) ----------        有两个以上赋值语句，不能确定“        cs_in ” 的 值

( e' |8 F0 @# e% A: W! g7 U! s/ t

30. Warning:        Ignored        node in        vector        source        file.        Can't        find        corresponding node
name "over" in design.
. S" i( r+ @0 s# q# H( `---------------        在源文件中找不到对应的节点“        over ”。

31. Error: Can't access JTAG chain
2 Z1 S$ t; q; q! v: S3 v, K4 m无法找到下载链

* {: h3 q8 ^8 E5 ^  c$ N/ f

32. Info: Assuming node "clk" is an undefined clock

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